This application is related to U.S. Publication No. 2010/0161948, titled, “PARALLEL PROCESSING OF A SEQUENTIAL PROGRAM USING HARDWARE GENERATED THREADS AND THEIR INSTRUCTION GROUPS EXECUTING ON PLURAL EXECUTION UNITS AND ACCESSING REGISTER FILE SEGMENTS USING DEPENDENCY INHERITANCE VECTORS ACROSS MULTIPLE ENGINES” (now U.S. Pat. No. 8,677,105 issued Mar. 18, 2014), which is the national stage of International Application No. PCT/US07/84710 filed Nov. 14, 2007, which are hereby incorporated by reference.
This application is related to U.S. Publication No. 2009/0113170, titled, “PLURAL MATRICES OF EXECUTION UNITS FOR PROCESSING MATRICES OF ROW DEPENDENT INSTRUCTIONS IN SINGLE CLOCK CYCLE IN SUPER OR SEPARATE MODE” (now U.S. Pat. No. 8,327,115 issued Dec. 4, 2012), which is the national stage of International Application No. PCT/US2007/066536 filed Apr. 12, 2007, which are hereby incorporated by reference.
This application is related to U.S. Provisional Application No. 61/384,198, titled, “SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION,” filed Sep. 17, 2010, which is hereby incorporated by reference.
This application is related to U.S. Provisional Application No. 61/467,944, titled, “EXECUTING INSTRUCTION SEQUENCE CODE BLOCKS BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES,” filed Mar. 25, 2011, which is hereby incorporated by reference.
The present invention is generally related to digital computer systems, more particularly, to a system and method for selecting instructions comprising an instruction sequence.
Processors are required to handle multiple tasks that are either dependent or totally independent. The internal state of such processors usually consists of registers that might hold different values at each particular instant of program execution. At each instant of program execution, the internal state image is called the architecture state of the processor.
When code execution is switched to run another function (e.g., another thread, process or program), then the state of the machine/processor has to be saved so that the new function can utilize the internal registers to build its new state. Once the new function is terminated then its state can be discarded and the state of the previous context will be restored and execution resumes. Such a switch process is called a context switch and usually includes 10's or hundreds of cycles especially with modern architectures that employ large number of registers (e.g., 64, 128, 256) and/or out of order execution.
In thread-aware hardware architectures, it is normal for the hardware to support multiple context states for a limited number of hardware-supported threads. In this case, the hardware duplicates all architecture state elements for each supported thread. This eliminates the need for context switch when executing a new thread. However, this still has multiple draw backs, namely the area, power and complexity of duplicating all architecture state elements (i.e., registers) for each additional thread supported in hardware. In addition, if the number of software threads exceeds the number of explicitly supported hardware threads, then the context switch must still be performed.
This becomes common as parallelism is needed on a fine granularity basis requiring a large number of threads. The hardware thread-aware architectures with duplicate context-state hardware storage do not help non-threaded software code and only reduces the number of context switches for software that is threaded. However, those threads are usually constructed for coarse grain parallelism, and result in heavy software overhead for initiating and synchronizing, leaving fine grain parallelism, such as function calls and loops parallel execution, without efficient threading initiations/auto generation. Such described overheads are accompanied with the difficulty of auto parallelization of such codes using state of the art compiler or user parallelization techniques for non-explicitly/easily parallelized/threaded software codes.
In one embodiment the present invention is implemented as a method for accelerating code optimization in a microprocessor. The method includes fetching an incoming macroinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit to the optimized microinstruction sequence.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.
Although the present invention has been described in connection with one embodiment, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.
In the following detailed description, numerous specific details such as specific method orders, structures, elements, and connections have been set forth. It is to be understood however that these and other specific details need not be utilized to practice embodiments of the present invention. In other circumstances, well-known structures, elements, or connections have been omitted, or have not been described in particular detail in order to avoid unnecessarily obscuring this description.
References within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase “in one embodiment” in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.
Some portions of the detailed descriptions, which follow, are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals of a computer readable storage medium and are capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “processing” or “accessing” or “writing” or “storing” or “replicating” or the like, refer to the action and processes of a computer system, or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories and other computer readable media into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
In one embodiment the present invention is implemented as a method for accelerating code optimization in a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit to the optimized microinstruction sequence.
In the
The macroinstruction sequence is decoded into a resulting microinstruction sequence by the native decode component 102. This microinstruction sequence is then transmitted to the instruction scheduling and optimizing component 110 through a multiplexer 103. The instruction scheduling and optimizer component functions by performing optimization processing by, for example, reordering certain instructions of the microinstruction sequence for more efficient execution. This results in an optimized microinstruction sequence that is then transferred to the remaining pipeline 105 (e.g., the allocation, dispatch, execution, and retirement stages, etc.) through the multiplexer 104. The optimized microinstruction sequence results in a faster and more efficient execution of the instructions.
In one embodiment, the macroinstructions can be instructions from a high level instruction set architecture, while the microinstructions are low level machine instructions. In another embodiment, the macroinstructions can be guest instructions from a plurality of different instruction set architectures (e.g., CISC like, x86, RISC like, MIPS, SPARC, ARM, virtual like, JAVA, and the like), while the microinstructions are low level machine instructions or instructions of a different native instruction set architecture. Similarly, in one embodiment, the macroinstructions can be native instructions of an architecture, and the microinstructions can be native microinstructions of that same architecture that have been reordered and optimized. For example X86 macro instructions and X86 micro-coded microinstructions.
In one embodiment, to accelerate the execution performance of code that is frequently encountered (e.g., hot code), copies of frequently encountered microinstruction sequences are cached in the microinstruction cache 121 and copies of frequently encountered optimized microinstruction sequences are cached within the sequence cache 122. As code is fetched, decoded, optimized, and executed, certain optimized microinstruction sequences can be evicted or fetched in accordance with the size of the sequence cache through the depicted eviction and fill path 130. This eviction and fill path allows for transfers of optimized microinstruction sequences to and from the memory hierarchy of the microprocessor (e.g., L1 cache, L2 cache, a special cacheable memory range, or the like).
It should be noted that in one embodiment, the microinstruction cache 121 can be omitted. In such an embodiment, the acceleration of hot code is provided by the storing of optimized microinstruction sequences within the sequence cache 122. For example, the space saved by omitting microinstruction cache 121 can be used to implement a larger sequence cache 122, for example.
One objective of the optimization process is to locate and identify instructions that depend upon one another and move them into their respective dependency groups so that they can execute more efficiently. In one embodiment, groups of dependent instructions can be dispatched together so that they can execute more efficiently since their respective sources and destinations are grouped together for locality. It should be noted that this optimization processing can be used in both an out of order processor as well as an in order processor. For example, within an in order processor, instructions are dispatched in-order. However, they can be moved around so that dependent instructions are placed in respective groups so that groups can then execute independently, as described above.
For example, the incoming instructions include loads, operations and stores. For example, instruction 1 comprises an operation where source registers (e.g., register 9 and register 9) are added and the result stored in register 5. Hence, register 5 is a destination and register 9 and register 5 are sources. In this manner, the sequence of 16 instructions includes destination registers and source registers, as shown.
The
Referring still to
The algorithm begins by looking for true dependencies first. To identify true dependencies, each destination of the 16 instruction sequence is compared against other subsequent sources which occur later in the 16 instruction sequence. The subsequent instructions that are truly dependent on an earlier instruction are marked “_1” to signify their true dependence. This is shown in
The algorithm then looks for output dependencies. To identify output dependencies, each destination is compared against other subsequent instructions' destinations. And for each of the 16 instructions, each subsequent destination that matches is marked “1_” (e.g., sometimes referred to as a red one).
The algorithm then looks for anti-dependencies. To identify anti-dependencies, for each of the 16 instructions, each source is compared with earlier instructions'sources to identify matches. If a match occurs, the instruction under consideration marks its self “1_” (e.g., sometimes referred to as a red one).
In this manner, the algorithm populates a dependency matrix of rows and columns for the sequence of 16 instructions. The dependency matrix comprises the marks that indicate the different types of dependencies for each of the 16 instructions. In one embodiment, the dependency matrix is populated in one cycle by using CAM matching hardware and the appropriate broadcasting logic. For example, destinations are broadcasted downward through the remaining instructions to be compared with subsequent instructions'sources (e.g., true dependence) and subsequent instructions' destinations (e.g., output dependence), while destinations can be broadcasted upward through the previous instructions to be compared with prior instructions'sources (e.g., anti dependence).
The optimization algorithm uses the dependency matrix to choose which instructions to move together into common dependency groups. It is desired that instructions which are truly dependent upon one another be moved to the same group. Register renaming is used to eliminate anti-dependencies to allow those anti-dependent instructions to be moved. The moving is done in accordance with the above described rules and hazard checks. For example, stores cannot move past earlier loads without dependency checks. Stores cannot past earlier stores. Loads cannot pass earlier stores without dependency checks. Loads can pass loads. Instructions can pass prior path predicted branches (e.g., dynamic the constructed branches) by using a renaming technique. In the case of non-dynamically predicted branches, movements of instructions need to consider the scopes of the branches.
In one embodiment, a priority encoder can be implemented to determine which instructions get moved to be grouped with other instructions. The priority encoder would function in accordance with the information provided by the dependency matrix.
In this manner,
Process 500 begins in step 501, where an incoming macroinstruction sequence is fetched using an instruction fetch component (e.g., fetch component 20 from
In step 502, the fetched macroinstructions are transferred to a decoding component for decoding into microinstructions. The macroinstruction sequence is decoded into a microinstruction sequence in accordance with the branch predictions. In one embodiment, the microinstruction sequence is then stored into a microinstruction cache.
In step 503, optimization processing is then conducted on the microinstruction sequence by reordering the microinstructions comprising sequence into dependency groups. The reordering is implemented by an instruction reordering component (e.g., the instruction scheduling and optimizer component 110). This process is described in the
In step 504, the optimized microinstruction sequence is an output to the microprocessor pipeline for execution. As described above, the optimized microinstruction sequence is forwarded to the rest of the machine for execution (e.g., remaining pipeline 105).
And subsequently, in step 505, a copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit to that sequence. In this manner, the sequence cache enables access to the optimized microinstruction sequences upon subsequent hits on those sequences, thereby accelerating hot code.
Process 600 begins in step 601, where an incoming macroinstruction sequence is fetched using an instruction fetch component (e.g., fetch component 20 from
In step 602, the fetched macroinstructions are transferred to a decoding component for decoding into microinstructions. The macroinstruction sequence is decoded into a microinstruction sequence in accordance with the branch predictions. In one embodiment, the microinstruction sequence is then stored into a microinstruction cache.
In step 603, the decoded micro instructions are stored into sequences in a micro instruction sequence cache. Sequences in the micro instruction cache are formed to start in accordance with basic block boundaries. These sequences are not optimized at this point.
In step 604, optimization processing is then conducted on the microinstruction sequence by reordering the microinstructions comprising sequence into dependency groups. The reordering is implemented by an instruction reordering component (e.g., the instruction scheduling and optimizer component 110). This process is described in the
In step 605, the optimized microinstruction sequence is an output to the microprocessor pipeline for execution. As described above, the optimized microinstruction sequence is forwarded to the rest of the machine for execution (e.g., remaining pipeline 105).
And subsequently, in step 606, a copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit to that sequence. In this manner, the sequence cache enables access to the optimized microinstruction sequences upon subsequent hits on those sequences, thereby accelerating hot code.
Additionally, with respect to dynamically unrolled sequences, it should be noted that instructions can pass prior path predicted branches (e.g., dynamically constructed branches) by using renaming. In the case of non-dynamically predicted branches, movements of instructions should consider the scopes of the branches. Loops can be unrolled to the extent desired and optimizations can be applied across the whole sequence. For example, this can be implemented by renaming destination registers of instructions moving across branches. One of the benefits of this feature is the fact that no compensation code or extensive analysis of the scopes of the branches is needed. This feature thus greatly speeds up and simplifies the optimization process.
Additional information concerning branch prediction and the assembling of instruction sequences can be found in commonly assigned U.S. patent application Ser. No. 61/384,198, titled “SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION” by Mohammad A. Abdallah, filed on Sep. 17, 2010, which is incorporated herein in its entirety.
In the
It should be noted that the software optimizer 1000 can comprise code residing in the memory hierarchy as both input to the optimization and output from the optimization process.
It should be noted that in one embodiment, the microinstruction cache can be omitted. In such an embodiment, only the optimized microinstruction sequences are cached.
In step 1201, an input sequence of instructions is accessed by using a software-based optimizer instantiated memory.
In step 1202, a dependency matrix is populated, using SIMD instructions, with dependency information extracted from the input sequence of instructions by using a sequence of SIMD compare instructions.
In step 1203, the rows of the matrix are scanned from right to left for the first match (e.g., dependency mark).
In step 1204, each of the first matches are analyzed to determine the type of the match.
In step 1205, if the first marked match is a blocking dependency, renaming is done for this destination.
In step 1206, all first matches for each row of the matrix are identified and the corresponding column for that match is moved to the given dependency group.
In step 1207, the scanning process is repeated several times to reorder instructions comprising the input sequence to produce an optimized output sequence.
In step 1208, the optimized instruction sequence is output to the execution pipeline of the microprocessor for execution.
In step 1209, the optimized output sequence is stored in a sequence cache for subsequent consumption (e.g., to accelerate hot code).
It should be noted that the software optimization can be done serially with the use of SIMD instructions. For example, the optimization can be implemented by processing one instruction at a time scanning instructions'sources and destinations (e.g., from earlier instructions to subsequent instructions in a sequence). The software uses SIMD instructions to compare in parallel current instruction sources and destinations with prior instruction sources and destinations in accordance with the above described optimization algorithm and SIMD instructions (e.g. to detect true dependencies, output dependencies and anti-dependencies).
The software scheduling process of
The
With the second group, instruction numbers are loaded into the first register, instruction destination numbers are loaded into the second register, and the values in the first register are broadcast to positions in the third register (e.g., the result register) in accordance with the position number in the second register. Positions in the third register can over write the result that was written during the processing of the first group. Positions in the third register that have not been written to are bypassed. In this manner, the second group updates the base from the first group, and thereby produces a new base for the processing of a third group, and so on.
Instructions in the second group can inherit dependency information generated in the processing of the first group. It should be noted that the entire second group does not have to be processed to update dependency in the result register. For example, dependency for instruction 12 can be generated in the processing of the first group, and then processing instructions in the second group up to instruction 11. This updates the result register to a state up to instruction 12. In one embodiment, a mask can be used to prevent the updates for the remaining instructions of the second group (e.g., instructions 12 through 16). To determine dependency for instruction 12, the result register is examined for R2 and R5. R5 will be updated with instruction 1, and R2 will be updated with instruction 11. It should be noted that in a case where all of group 2 is processed, R2 will be updated with instruction 15.
Additionally, it should be noted that all the instructions of the second group (e.g., instructions 9-16) can be processed independent of one another. In such case, the instructions of the second group depend only on the result register of the first group. The instructions of the second group can be processed in parallel once the result register is updated from the processing of the first group. In this manner, groups of instructions can be processed in parallel, one after another. In one embodiment, each group is processed using a SIMD instruction (e.g., a SIMD broadcast instruction), thereby processing all instructions of said each group in parallel.
The dependency level of each instruction is used by a second-level hierarchical scheduler to dispatch instructions in such a manner as to ensure resources are available for dependent instructions to execute. For example, in one embodiment, L0 instructions are loaded into instruction queues that are processed by the second-level schedulers 1-4. The L0 instructions are loaded such that they are in front of each of the queues, the L1 instructions are loaded such that they follow in each of the queues, L2 instructions follow them, and so on. This is shown by the dependency levels, from L0 to Ln in
In this manner, embodiments of the present invention intimate dependency group slot allocation for the instructions of the instruction sequence. For example, to implement an out of order microarchitecture, the dispatching of the instructions of the instruction sequence is out of order. In one embodiment, on each cycle, instruction readiness is checked. An instruction is ready if all instructions that it depends upon have previously dispatched. A scheduler structure functions by checking those dependencies. In one embodiment, the scheduler is a unified scheduler and all dependency checking is performed in the unified scheduler structure. In another embodiment, the scheduler functionality is distributed across the dispatch queues of execution units of a plurality of engines. Hence, in one embodiment the scheduler is unified while in another embodiment the scheduler is distributed. With both of these solutions, each instruction source is checked against the dispatch instructions' destination every cycle.
Thus,
It should be noted that the functionality diagrammed in the
As described above, the dependency level of each instruction is used by a second-level hierarchical scheduler to dispatch instructions in such a manner as to ensure resources are available for dependent instructions to execute. L0 instructions are loaded into instruction queues that are processed by the second-level schedulers 1-4. The L0 instructions are loaded such that they are in front of each of the queues, the L1 instructions are loaded such that they follow in each of the queues, L2 instructions follow them, and so on, as shown by the dependency levels, from L0 to Ln in
In this manner,
As depicted in
As described above, moving window scheduler processes the instructions in the queues to dispatch instructions in such a manner as to ensure resources are available for dependent instructions to execute. The bottom of
In this manner, the dependency groups shown in
In accordance with embodiments of the present invention, it should be appreciated that instructions are abstracted into dependency groups or blocks or instruction matrices in accordance with their dependencies. Grouping instructions in accordance with their dependencies facilitates a more simplified scheduling process with a larger window of instructions (e.g., a larger input sequence of instructions). The grouping as described above removes the instruction variation and abstracts such variation uniformly, thereby allowing the implementation of simple, homogenous and uniform scheduling decision-making. The above described grouping functionality increases the throughput of the scheduler without increasing the complexity of the scheduler. For example, in a scheduler for four engines, the scheduler can dispatch four groups where each group has three instructions. In so doing, the scheduler only handles four lanes of super scaler complexity while dispatching 12 instructions. Furthermore, each block can contain parallel independent groups which further increase the number of dispatched instructions.
The memory global interconnect comprises a routing matrix that allows a plurality of cores (e.g., the address calculation and execution units 121-124) to access data that may be stored at any point in the fragmented cache hierarchy (e.g., L1 cache, load store buffer and L2 cache).
The execution global interconnect 110b similarly comprises a routing matrix allows the plurality of cores (e.g., the address calculation and execution units 121-124) to access data that may be stored at any of the segmented register files. Thus, the cores have access to data stored in any of the fragments and to data stored in any of the segments through the memory global interconnect 110a or the execution global interconnect 110b.
In one embodiment, a non-centralized access process is implemented for using the interconnects and the local interconnects employ the reservation adder and a threshold limiter control access to each contested resource, in this case, the ports into each segment. In such an embodiment, to access a resource, a core needs to reserve the necessary bus and reserve the necessary port.
For purposes of explanation, the foregoing description refers to specific embodiments that are not intended to be exhaustive or to limit the current invention. Many modifications and variations are possible consistent with the above teachings. Embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, so as to enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as may be suited to their particular uses.
This application is a divisional of to U.S. application Ser. No. 14/360,282, which is the national stage of International Application No. PCT/US2011/061957 filed Nov. 22, 2011, which are hereby incorporated by reference.
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Number | Date | Country | |
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20170024219 A1 | Jan 2017 | US |
Number | Date | Country | |
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Parent | 14360282 | US | |
Child | 15283836 | US |