Claims
- 1. In a pipelined computer processor, which executes pipelined instructions, including a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode method for loading operands and testing for access exceptions while retaining millicode control of the operation, including the steps of:
- storing a millicode load and test access instruction that includes a field specifying a millicode register address and a field specifying a storage address for an access exception to a second operand fetch access exception;
- fetching said millicode load and test access instruction;
- testing a load operand operation;
- setting one condition code when no access exception is found;
- blocking an interrupt when an access exception is found and setting another condition code;
- forcing a serialization in response to said another condition code to purge the instruction pipeline and reset a pipeline control without redirection of the instruction stream.
DESCRIPTION
This application is a division of application Ser. No. 08/414,154 of Charles F. Webb et al., filed Mar. 31, 1995, entitled "Specialized Millicode Instruction", now U.S. Pat. No. 5,694,587.
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Divisions (1)
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Number |
Date |
Country |
Parent |
414154 |
Mar 1995 |
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