Claims
- 1. A method of forming a polymeric barrier layer on an interconnect structure comprising applying a polymeric barrier layer on at least a polymer scratch guard/stress buffer layer which is present atop an interconnect structure, wherein said polymeric barrier layer comprises a fluoropolymer, a polychlorofluoropolymer or a hydrocarbon polymer selected from the group consisting of polynorbonenes, polyphenylenes and parylene.
- 2. The method of claim 1 wherein said polymeric barrier layer is applied by dip coating, spin coating, Langmuir-Blodget film fabrication, plasma deposition, evaporation, sputtering or chemical vapor deposition.
- 3. The method of claim 2 wherein said polymeric barrier layer is applied by dip coating.
- 4. The method of claim 3 wherein said dip coating includes providing a dilute solution of said polymeric material and immersing the previously fabricated interconnect structure therein.
- 5. The method of claim 4 wherein said dilute polymeric solution comprises said polymeric barrier layer dissolved in a perfluorinated alkane or alkane ether.
- 6. The method of claim 1 wherein said applied polymeric barrier layer has a thickness of from about 0.1 nanometer to about 5 micrometers.
- 7. The method of claim 6 wherein said applied polymeric barrier layer has a thickness of from about 1 nanometer to about 1.5 micrometers.
- 8. The method of claim 1 wherein said interconnect structure is present atop an integrated circuit, said interconnect structure comprising an organic dielectric having metallic vias, lines and pads embedded therein, wherein said metallic pads are connected to a next level package by a connection technology.
- 9. The method of claim 1 wherein said polymeric barrier layer is a fluoropolymer selected from the group consisting of polytetrafluoroethylene (PTFE) and amorphous copolymers of PTFE and perfluro 2,2-dimethyl-1,3-dioxole.
- 10. A method for protecting a diced edge of a semiconductor chip from ion and moisture ingress, comprising applying a polymeric barrier layer to an edge of a semiconductor die after dicing, wherein said polymeric barrier layer comprises a fluoropolymer, a polychlorofluoropolymer or a hydrocarbon polymer selected from the group consisting of polynorbonenes, polyphenylenes and parylene.
RELATED APPLICATION
This application is a divisional of U.S. application Ser. No. 09/122,353, filed Jul. 24, 1998 now U.S. Pat. No. 6,130,472
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