1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more particularly to integrated circuit device fabrication process control.
2. Description of the Background Art
Integrated circuit (IC) devices are generally fabricated on a substrate, such as a semiconductor wafer. The wafer is subjected to various fabrication processing steps to form dopant regions, dielectric layers, metal layers with metal lines, vias providing electrical connection between metal lines on different levels, trenches, and other regions and structures. The fabrication processing steps are generally well known and may include diffusion, implantation, deposition, electroplating, chemical-mechanical polishing (CMP), annealing, lithography, and etching, for example. The fabrication processing steps result in an integrated circuit device formed in one or more levels of the wafer. Several integrated circuit devices are typically formed on a single wafer. The integrated circuit devices are tested at different steps in the fabrication process to insure that they operate as designed. The tests allow for identification of defective devices so that they may be separated from good devices. The yield of a fabrication process is a measure of the number of good structures, self-contained devices, or regions relative to defective ones fabricated using the process.
Various process control mechanisms may be employed to monitor and control fabrication processes. However, fabrication processes remain relatively difficult to monitor and control due to their complexity and the large number of processing variables involved. Embodiments of the present invention provide process control techniques that may be effectively used to monitor and control fabrication processes to meet yield requirements for particular devices.
An integrated circuit (IC) device fabrication process may be monitored by processing product wafers to fabricate product IC devices, collecting process tool data from tools used to fabricate the product IC devices, and testing the product IC devices. To predict and monitor yield, the process tool data collected during processing and the defectivity data from testing the product IC devices may be input to a yield model that also takes into account design information particular to the product devices. The design information may comprise layout attributes of the product devices. The yield model may be generated from a defectivity model created by processing test wafers to fabricate test structures, collecting process tool data from tools used to fabricate the test structures, and testing the test structures. The test structures may have varying test layout attributes to cover a design space allowed by design rules for particular product IC devices.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
The use of the same reference label in different drawings indicates the same or like components.
In the present disclosure, numerous specific details are provided, such as examples of apparatus, components, and methods, to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.
In the example of
Each test wafer 150 may be run through the process steps 100 of a process module 110 to build the test structures. For example, tool 1 in process step 100-1 may process a test wafer 150 to build a portion of a test structure, tool 12 in process step 100-2 may process the test wafer 150 to build another portion of the test structure, and so on. In one embodiment, the process tool data (PTD) 121, also referred to as “Fault Detection and Classification” data, comprise process parameters by which a wafer is processed by a tool and may cause a defect in the processed wafer. That is, each data in the PTD 121 may be a process parameter that may impact the fabricated structure or region on the wafer, and it also may be the statistics calculated from the time trace of such process parameters. The PTD 121 may depend on the type of the tool and may include, for example, process temperature, CMP pad pressure, slurry flow, bias voltage, etc., and the statistics may be mean values, minimum values, etc. of the process parameters. As a particular example, assuming tool 1 of the process step 100-1 is a PVD tool and the process step 100-2 is an etcher, the PTD 121 may include gas flow and coil current of tool 1 and etch bias voltage and chamber pressure of tool 2. The PTD 121 may be provided by their respective tools, and may be collected from the tools' sensor and configuration data for collection in the computer 140 over a computer network, for example.
The PTD 121 may include high frequency or low frequency data of the tools. High frequency data are those that occur whenever a wafer is processed. Examples of high frequency data include pad pressure, slurry flow, gas flow, chamber pressure, etch bias voltage, etc. In contrast, low frequency data are those that only occur from time to time and not during every wafer run. Examples of low frequency data include preventive maintenance schedules, time intervals between wafer processing, etc.
Test structures in the test wafers 150 may be tested after processing through one or more process modules 110. The tests may be performed by probing or non-probing means (e.g., e-beam by voltage contrasts). In the example of
The defectivity data 130 may comprise defects found in the test wafers 150. Particular examples of defectivity data may include an open via, a shorted metal line on a metal level, an open metal line on a metal level, etc. The defectivity data 130 may be in the form of fail rate or defect density (D0), for example. Fail rate may be expressed in number of fails per feature count (e.g., contact fail rate of 1 fail per 1 billion contacts), and defect density may be expressed in defects per cm2.
Each test wafer 150 may comprise a plurality of test structures that cover the design space allowed by a particular set of design rules. In one embodiment, a test wafer 150 includes test structures that incorporate design information, such as layout attributes, of product devices that may be processed in one or more process modules. The layout attributes may comprise physical arrangements of features of a product device, including metal line width, pitch, spacing, density, etc. The test structures may be designed to satisfy an experiment to determine the effect of varying layout attributes to defectivity. For example, the test structures in a test wafer 150 may be fabricated with different line widths, pitch, spacing, etc. to cover the range of variations these features may be fabricated per the design rules.
The computer 140 may comprise a computer or interconnected computers configured to collect PTD 121 and defectivity data 130. The computer 140 may also receive design information, such as layout attributes 160 of test structures in the test wafers 150. The computer 140 may include software packages for performing statistical analysis and other data processing to allow for generation of a yield impact model that takes into account layout attributes, process tool data, and defectivity data.
In the example of
One or more defectivity models describing the relationship between layout attributes, defectivity data, and process tool data are built after the testing of the test wafers (step 304). In one embodiment, a defectivity model may be created by performing regression analysis and fitting to the collected process tool data and defectivity data to express defectivity as a function of process tool data and layout attribute.
In the example of
Similarly, in the example of
The plots of
D
0
=k
0
+k
1
M1DENSITY+k2M2DENSITY (EQ. 1)
where D0 is the defect density of opens and shorts in the second metal level, k0 is a constant coefficient, k1 is the slope of the plot of defect density versus density of the first metal level, k2 is the slope of the plot of defect density versus density of the second metal level, M1DENSITY is the density of the first metal level, and M2DENSITY is the density of the second metal level. Equation 1 assumes a linear relationship in this example, but this is not necessarily the case. As can be appreciated, the principles disclosed herein may be extended to non-linear relationships.
k0, k1, k2 can be further expressed as a function of process tool data based on defectivity data and process tool data for a given layout attribute, either as a linear relationship or non-linear relationship. For example, equation 1 may be expanded as in equation 2 to take into account process tool data,
where a1a2a3 . . . an, b1b2b3 . . . bn, c1c2c3 . . . cn etc. are coefficients and PTD1, PTD2, PTD3 . . . PTDn are process tool data, M1DENSITY is the density of the first metal level, and M2DENSITY is the density of the second metal level.
Equation 1 may be generalized as a defectivity model as shown in equation 3,
where D is the defectivity in defect density or fail rate depending on the defect, C0 is a constant coefficient, S1 is the slope of the plot of defectivity versus the first layout attribute, S2 is the slope of the plot of defect density versus the second layout attribute, Sn is the slope of the plot of defect density versus the nth layout attribute, Attribute1 is the first layout attribute, Attribute2 is the second layout attribute, and Attributen is the nth layout attribute. Here, C0, S1, S2 are functions of process tool data. One way of determining the relationship between C0, S1, S2 and process tool data is to align the process tool data with corresponding defectivity data for a given layout attribute using a regression algorithm, such as stepwise regression, for example.
Referring back to
In general, the yield Y for a specific product may be represented as:
Where Aic(p) is the critical area for a given layout attribute i, D0i is defect density or defect density penalty for a given layout attribute i, λi is the fail rate or fail rate penalty for a given layout attribute i, and Ni is the feature count for the fail rate for a given layout attribute i. The defectivity model of equation 3 provides the defectivity, which may be in defect density D0i or fail rate λi, and may be substituted in either equation 4 or 5 to give the yield impact model.
The above-described yield impact model provides several advantages heretofore unrealized. Firstly, taking into account layout attributes in generating the yield impact model allows for a better estimate of the effect of particular process tool data that impact several defectivity data. Secondly, when the differential impact of particular process tool data depends on a layout attribute, the yield impact model provides more information about that differential impact. Thirdly, because the defectivity model incorporates process tool data and layout attributes, the yield impact model may be employed to determine the yield impact of process tool data for particular layout attributes. For example, layout attribute data of a particular product device may be input to the yield impact model. During processing of the product device, process tool data from a tool processing the device may be input to the yield impact model to determine if the operating process conditions of the tool detrimentally impact the yield. By inputting layout attributes of the product device into the yield impact model, the yield impact model generates a response tailored for the product device. As can be appreciated, this advantageously allows tool monitoring to be optimized for particular devices, each of which may have particular layout attributes.
The method 400 begins with product wafers being processed in tools to fabricate product integrated circuit devices (step 401). Process tool data are collected from the tools during processing (402). Product information for the product wafers is collected (step 403). The product information may identify the product devices being fabricated in the product wafers and where to obtain design information for the product devices. Product information may be retrieved from a server computer in the fabrication facility, or recorded in a production manual or in documentation accompanying the product wafers. Design information particular to the product devices, such as pre-calculated layout attributes of the product devices, are obtained (step 404). Design information may be obtained from the factory server computer or looked up in design documents, for example.
The predicted yield of the fabrication process may be calculated by inputting the process tool data and the layout attributes of the product devices into the yield impact model (step 405). Alarms may be triggered based on the calculated predicted yield or defectivity (step 406). For example, alarms may be set to trigger when collected process tool data and layout attributes of the product devices being fabricated result in the yield impact model generating a predicted yield that is below a minimum yield requirement. As another example, alarms may be set to trigger when the defectivity is beyond a maximum defectivity requirement. For a device fabrication facility that processes many different types of products, the same process tool data may trigger an alarm for one type of product but not for another type of product, due to the difference of their layout attributes.
While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure.