Patent Application
20060190757
Application specific integrated circuits (ASICs) may use a set of input/output (I/O) pins to observe internal signals for monitoring, observation, counting, and debug, among other functions. Such I/O pins or “ports” are sometimes referred to as monitor/observation/debug ports. Typically, these ports view signals from the perspective of one clock domain. In some cases, a particular port may allow signals to be viewed “live” without going through any flip-flops. In some instances, no debug operations are performed on some clock domains such as on smaller clock domains, but rather, are focused on the main or core clock domain. This does not allow for signals to be observed in the other clock domains if there is a problem.
Embodiments of the invention cover methods, systems, and circuits for signal crossing multiple clock domains. One method embodiment includes monitoring multiple clock domains. The example method includes pipelining different sets of signals from different clock domains on an application specific integrated circuit (ASIC) to a particular input/output (I/O) port on the ASIC using an associated clock from each different clock domain. The method also includes selecting a particular set of signals from among the different sets of signals to send out of the particular I/O port. The different sets of signals in the destination clock domain can be monitored and observed by a logic analyzer, oscilloscope, and/or other test equipment.
As shown in the embodiment of
As illustrated with example ASIC 110-1, a given ASIC can include a number of different clock domains, 112-1, . . . , 112-M, having similar and/or dissimilar clock frequencies. The designator “M” is used to indicate that a number of different clock domains may be included with a given ASIC 110-1. On ASIC 110-1 each of the “M” different clock domains can have a different clock associated therewith.
So, for example, one clock domain 112-1 may have a different clock frequency from another clock domain, e.g., 112-2. The clock associated with clock domain 112-2 may again be different from the clock associated with clock domain 112-3. At the same time, a clock associated with a given clock domain may be equivalent to the clock used in another clock domain. For example, the clock associated with clock domain 112-5 may have the same clock frequency as the clock associated with clock domain 112-6. Embodiments are not limited to the examples described here in connection with ASIC 110-1.
As shown in
As shown in the embodiment of
The pipelining or routing of signals from several of the different clock domains 112-1, . . . , 112-M to an area of a particular I/O port, e.g., 113-3, on the ASIC 110-1 for monitoring, observation, and/or debug by a logic analyzer, e.g., 114, is described in more detail below.
In the embodiment illustrated in
With respect to the other channels, in the embodiment shown, a pre-selection is made by multiplexer 230 and that selection is provided to the multiplexer 228. Multiplexer 230 selects one or more channels 219-1, 219-2, 219-3, and a flash static random access memory (SRAM) channel 223 in which to route on to multiplexer 228. Such embodiments, having a pre-selection multiplexer can be useful, for example, when the channels to be pre-selected exist in the same clock domain.
Embodiments can also be used where the I/O port 226 can provide signals other than those associated with clock signals. For example, as shown in
Multiplexer 229 selects which clock is to be used with the channel that has been selected by multiplexer 228. In this way, a clock signal corresponding to the channel selected can also be selected. The control of the multiplexers and, therefore, the selections made thereby, can be accomplished through use of one or more control signals 221. The control signals can be used to instruct one or more of the multiplexers which of the channels or clock signals is to be routed through to the I/O port 226.
The controller can provide instructions in a variety of formats. For example, an instruction can be one or more bits of data. For instance, the multiplexer can receive a two bit instruction (e.g., having a value such as 0, 1, 2, or 3) indicating the routing of information that is assigned to a channel corresponding to that number. In the illustrated case, a 0 represents the flash SRAM channel 223, a 1 represents channel 219-2, a 2 represents channel 219-1, and an N represents channel 219-3. In this example the N can represent any value and is used to indicate that multiplexers can be used to select from various numbers of channels. These control signals can be provided to the multiplexers via connections 234-1, 234-2, and 234-3, for example.
In this embodiment, a multiplexer 330 pre-selects from channels 319-1 and 319-2 which of these two channels will be routed to the multiplexer 328. In addition to the channel selected by multiplexer 330, the multiplexer 328 also selects from channels 319-3 and 319-4. These channels are routed directly to multiplexer 328. The clock signal that corresponds to the selected channel is selected by multiplexer 329. As with the embodiment of
Monitoring of multiple clock domains can be aided through use of a number of signal crossing FIFOs. Such embodiments are described briefly with respect to
As the reader will appreciate, the embodiments of the invention can use localized signal crossing FIFOs, e.g., 444-1, . . . , 444-Q as shown in
The embodiment of
The output of each multiplexer 442-1, . . . , 442-Q for clock domains 441-1, . . . , 441-P, are input to a signal crossing FIFO, illustrated as 444-1, . . . , 444-Q respectively. In each case the signal crossing FIFO includes a clock input associated with a particular, different clock domain (represented in
As shown in the example embodiment of
One of ordinary skill in the art will appreciate upon reading this disclosure the manner in which signals from one clock domain can be input to a signal crossing FIFO to be output according to another clock frequency. For an example illustration of the same reference is made to commonly assigned, issued U.S. Pat. No. 6,208,703, issued to Cavanna et al., Mar. 27, 2001, which is incorporated herein in full by reference.
In the illustrative embodiment of
In other words, for signal crossing FIFO 444-1 “the clock (CLK) associated with the destination clock domain” has a lower clock frequency than “a clock associated with the source clock domain”, e.g., clock domain 441-1. The designator “Q” is used to indicate that a number of different clock domains may be provided with signal crossing FIFOs including a clock (CLK) associated with a particular, different, e.g., destination, clock domain on a given ASIC 110-1. In the example of
As noted above, within each respective clock domain 441-1, . . . , 441-P, different sets of signals can be connected to a multiplexer, shown as 442-1, . . . , 442-P. In each respective clock domain the multiplexer 442-1, . . . , 442-P can select, from among the different sets of signals received thereto, which signals from within that clock domain are of interest, e.g., for monitoring, observation, counting, debug, etc. In the example embodiment of
In the example of
In the above example for clock domain 441-2 a selected set of signals selected from among the different sets of signals received to the multiplexer 442-2 could be loaded into the signal crossing FIFO 444-2 each clock cycle of the clock associated with the destination clock domain, e.g., 441-P, since the signal crossing FIFO 444-2 can be unloaded faster than the rate at which data is arriving thereto. In this example, the signal crossing FIFO 444-2 can be relatively small in size, e.g., four word entries would suffice to capture all of the input data and synchronize to the destination clock domain.
As will be appreciated by the reader, data output signals 452-1, . . . , 452-Q can be unloaded from these signal crossing FIFOs 444-2 and 444-Q every cycle there is valid data in the FIFO. Thus, the valid output signals 450-1, 450-2, . . . , 450-Q are illustrated as input back into the clock crossing FiFOs 444-1, . . . , 444-Q to unload the FIFOs.
In the above example for clock domain 441-1 a selected set of signals selected from among the different sets of signals received to the multiplexer 442-1 can be loaded into the signal crossing FIFO 444-1 when there is room available in the signal crossing FIFO 444-1, i.e., the “full signal” 451-1 is not asserted. In this scenario, selected signals may be dropped or “lost” since the signal crossing FIFO 444-1 cannot unload data as fast as the rate at which data is arriving thereto, i.e. CLK is slower than CLK_F. That is, as the reader will appreciate, pointers have to be synchronized to the destination clock domain and there has to be enough word entries that each set of signals can go through the FIFO without being dropped.
Moreover, in the case where the signal crossing FIFO 444-1 is full and data may be potentially lost, an overflow signal 451 could be written to the signal crossing FIFO 444-1. For example, the source clock domain can have a state machine, not shown, which detects a “full” state, e.g., there was valid data that couldn't be loaded into the FIFO. As the reader will appreciate, such a state machine could keep a bit to indicate this state and set an overflow signal which could be stored/read by a processor later. Similarly, the overflow signal could be written to the FIFO if the word width is widened by a bit. The next time signals were loaded to the FIFO the overflow bit could be set and passed along out of the FIFO to the destination clock domain.
In one embodiment of the above example for clock domain 441-1 a selected set of signals selected from among the different sets of signals received to multiplexer 442-1 can be loaded into to signal crossing FIFO 444-1 upon receipt of a load signal 448-1. In this scenario, the load signal 448-1 is asserted to load selected signals from multiplexer 442-1 at a rate which will not overflow the signal crossing FIFO 444-1 based on a difference between the CLK frequency of the signal crossing FIFO (i.e., the frequency at which the signal crossing FIFO unloads data) and the clock frequency of the faster clock domain 441-1.
A valid output signal 450-1, . . . , 450-Q will be asserted every cycle there is valid data in the FIFOs 444-1, . . . , 444-Q. This signal will indicate when a data output signal 452-1, . . . , 452-Q is valid. As the reader will appreciate the valid output signals 450-1, . . . , 450-Q can indicate a valid set of data output signals from the signal crossing FIFOs 444-1, . . . , 444-Q.
As shown in the example embodiment of
Thus, it has been shown that the set of data output signals and valid output signals from multiple clock domains can be properly synchronized and connected to an embedded logic analyzer and/or a counter, as the same are known and understood, in a destination clock domain 441-P. As the reader will appreciate, counters are often provided in one clock domain of an ASIC and are useful for counting how many times events happen on the ASIC. Desirably, the counter would be provided in as fast a clock domain as possible. It will also be appreciated that after the set of data output signals and valid output signals have been moved to a particular destination clock domain they can be provided to buffers 457 to pipeline particular port on the ASIC used for monitoring, observation, and/or debugging, as illustrated more in
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same techniques can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the invention. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the invention includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the invention should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
