Timing aspects

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CPC
G01R31/31725

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31725Timing aspects

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Signal test
- Patent number 12,196,803
- Issue date Jan 14, 2025
- Infineon Technologies AG
- Muhammad Hassan
- G01 - MEASURING TESTING
Information Patent Grant
Method, arrangement, and computer program product for organizing th...
- Patent number 12,182,612
- Issue date Dec 31, 2024
- Minima Processor Oy
- Lauri Koskinen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System testing using partitioned and controlled noise
- Patent number 12,174,251
- Issue date Dec 24, 2024
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Grant
Circuit arrangement for validation of operation of a logic module i...
- Patent number 12,174,252
- Issue date Dec 24, 2024
- STMicroelectronics S.r.l.
- Diego Alagna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay measurement system and measurement method
- Patent number 12,169,222
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shang Hsien Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive body biasing or voltage regulation using slack sensors
- Patent number 12,169,221
- Issue date Dec 17, 2024
- Dolphin Design
- Sebastien Genevey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial test circuit for controllable Chiplets
- Patent number 12,135,354
- Issue date Nov 5, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,092,687
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applications of adaptive microelectronic circuits that are designed...
- Patent number 12,085,611
- Issue date Sep 10, 2024
- Minima Processor Oy
- Lauri Koskinen
- G01 - MEASURING TESTING
Information Patent Grant
Device interface board compliance testing using impedance response...
- Patent number 12,061,231
- Issue date Aug 13, 2024
- Celerint, LLC
- Howard H. Roberts
- G01 - MEASURING TESTING
Information Patent Grant
Sub-sampled based instrument noise correction for jitter measurements
- Patent number 12,055,585
- Issue date Aug 6, 2024
- Skyworks Solutions, Inc.
- Daniel de Godoy Peixoto
- G01 - MEASURING TESTING
Information Patent Grant
Silicon test structures for separate measurement of NMOS and PMOS t...
- Patent number 12,044,732
- Issue date Jul 23, 2024
- NVIDIA Corporation
- Prashant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flops and scan chain circuits including the same
- Patent number 12,044,733
- Issue date Jul 23, 2024
- Samsung Electronics Co., Ltd.
- Byounggon Kang
- G01 - MEASURING TESTING
Information Patent Grant
Low hold multi-bit flip-flop
- Patent number 12,040,800
- Issue date Jul 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and device for evaluating performance of sequential logic el...
- Patent number 12,019,120
- Issue date Jun 25, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zengquan Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Die-to-die and chip-to-chip connectivity monitoring
- Patent number 12,013,800
- Issue date Jun 18, 2024
- PROTEANTECS LTD.
- Eyal Fayneh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D stacked die test architecture
- Patent number 12,007,441
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit including test circuit and method of manufacturi...
- Patent number 12,000,888
- Issue date Jun 4, 2024
- Samsung Electronics Co., Ltd.
- Changho Han
- G01 - MEASURING TESTING
Information Patent Grant
Adaptive port ceiling assignment for background I/O operations betw...
- Patent number 11,994,557
- Issue date May 28, 2024
- Dell Products, L.P.
- Ananthakrishnan Anirudhan
- G01 - MEASURING TESTING
Information Patent Grant
Test compression in a JTAG daisy-chain environment
- Patent number 11,965,930
- Issue date Apr 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for detecting glitch at high sampling rate
- Patent number 11,965,929
- Issue date Apr 23, 2024
- UESTC (Shenzhen) Advanced Research Institute
- Zhijian Dai
- G01 - MEASURING TESTING
Information Patent Grant
Multi-die debug stop clock trigger
- Patent number 11,946,969
- Issue date Apr 2, 2024
- Apple Inc.
- Charles J. Fleckenstein
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-test for die-to-die physical interfaces
- Patent number 11,940,491
- Issue date Mar 26, 2024
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Grant
Benchmark circuit on a semiconductor wafer and method for operating...
- Patent number 11,927,628
- Issue date Mar 12, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chu-Feng Liao
- G01 - MEASURING TESTING
Information Patent Grant
Fan-out buffer with skew control function, operating method thereof...
- Patent number 11,921,158
- Issue date Mar 5, 2024
- Samsung Electronics Co., Ltd.
- Byung-Sung Kim
- G01 - MEASURING TESTING
Information Patent Grant
Burn-in resilient integrated circuit for processors
- Patent number 11,921,157
- Issue date Mar 5, 2024
- International Business Machines Corporation
- Andreas H. A. Arp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Register circuit with detection of data events, and method for dete...
- Patent number 11,894,848
- Issue date Feb 6, 2024
- Minima Processor Oy
- Navneet Gupta
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
GENERATING A TEST PROGRAM
- Publication number 20240426906
- Publication date Dec 26, 2024
- Teradyne, Inc.
- Charles J. Carline
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE INCLUDING A PLURALITY OF PADS AND METHOD OF DETECTING...
- Publication number 20240402248
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- Dojong CHUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS
- Publication number 20240369631
- Publication date Nov 7, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G01 - MEASURING TESTING
Information Patent Application
Low Hold Multi-Bit Flip-Flop
- Publication number 20240333265
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY TIMING CHARACTERIZATION CIRCUITRY
- Publication number 20240319269
- Publication date Sep 26, 2024
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DATA INTEGRITY CHECKING
- Publication number 20240319272
- Publication date Sep 26, 2024
- Imagination Technologies Limited
- Ross Martin Torkington
- G01 - MEASURING TESTING
Information Patent Application
MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION
- Publication number 20240310436
- Publication date Sep 19, 2024
- SILICON MOTION, INC.
- Tse-Yen Liu
- G01 - MEASURING TESTING
Information Patent Application
DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME
- Publication number 20240295603
- Publication date Sep 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-En Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES
- Publication number 20240288494
- Publication date Aug 29, 2024
- Meta Platforms Technologies, LLC
- Sri Harsha Manjunath
- G01 - MEASURING TESTING
Information Patent Application
ACCURATE CLOCK EDGE CALIBRATION OVER PVT CORNERS
- Publication number 20240288831
- Publication date Aug 29, 2024
- Meta Platforms Technologies, LLC
- Sri Harsha Manjunath
- G01 - MEASURING TESTING
Information Patent Application
MICROELECTRONIC CIRCUIT WITH DYNAMICALLY ADJUSTABLE COVERAGE FOR IN...
- Publication number 20240288495
- Publication date Aug 29, 2024
- Minima Processor Oy
- Markus Hiienkari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
- Publication number 20240264230
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR AND METHOD OF IMPROVING THE YIELD OF INTEGRATED CIRCUITS
- Publication number 20240264227
- Publication date Aug 8, 2024
- ZINITE CORPORATION
- Manoj SACHDEV
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUES FOR INFIELD TESTING OF CRYPTOGRAPHIC CIRCUITRY
- Publication number 20240264231
- Publication date Aug 8, 2024
- Intel Corporation
- Rakesh KANDULA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Insertion Delay Systems and Methods
- Publication number 20240183902
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G01 - MEASURING TESTING
Information Patent Application
CHIP WITH CLOCK MASKING CIRCUIT
- Publication number 20240175921
- Publication date May 30, 2024
- Realtek Semiconductor Corp.
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Application
BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...
- Publication number 20240175920
- Publication date May 30, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- CHU-FENG LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TESTING METHOD AND TESTING SYSTEM
- Publication number 20240161847
- Publication date May 16, 2024
- NANYA TECHNOLOGY CORPORATION
- Bo Jung PENG
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE AND METHOD FOR PERFORMING CLOCK GATING IN ELECTRO...
- Publication number 20240110976
- Publication date Apr 4, 2024
- Realtek Semiconductor Corp.
- Ching-Feng Huang
- G01 - MEASURING TESTING
Information Patent Application
GRPC-Based Chip Test Method, GRPC-Based Chip Test Apparatus, and St...
- Publication number 20240103075
- Publication date Mar 28, 2024
- Beijing ESWIN Computing Technology Co., Ltd.
- Zeliang Xie
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT SCREENING SYSTEM AND CIRCUIT SCREENING METHOD
- Publication number 20240094288
- Publication date Mar 21, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- CHI-CHE WU
- G01 - MEASURING TESTING
Information Patent Application
Adaptive Port Ceiling Assignment for Background I/O Operations Betw...
- Publication number 20240085474
- Publication date Mar 14, 2024
- Dell Products, L.P.
- Ananthakrishnan Anirudhan
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION
- Publication number 20240085475
- Publication date Mar 14, 2024
- MEDIATEK SINGAPORE PTE LTD
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION
- Publication number 20240077533
- Publication date Mar 7, 2024
- MEDIATEK SINGAPORE PTE LTD
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Serial Protocol-Based Event Trigger
- Publication number 20240061042
- Publication date Feb 22, 2024
- NXP USA, Inc.
- Tiefei Zang
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME
- Publication number 20240061039
- Publication date Feb 22, 2024
- Samsung Electronics Co., Ltd.
- Byounggon Kang
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240019489
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20240012050
- Publication date Jan 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Timing aspects

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Device access port selection

Signal test

Method, arrangement, and computer program product for organizing th...

System testing using partitioned and controlled noise

Circuit arrangement for validation of operation of a logic module i...

Delay measurement system and measurement method

Adaptive body biasing or voltage regulation using slack sensors

Selectable JTAG or trace access with data store and output

Serial test circuit for controllable Chiplets

Interface to full and reduced pin JTAG devices

Selectable JTAG or trace access with data store and output

Applications of adaptive microelectronic circuits that are designed...

Device interface board compliance testing using impedance response...

Sub-sampled based instrument noise correction for jitter measurements

Silicon test structures for separate measurement of NMOS and PMOS t...

Flip-flops and scan chain circuits including the same

Low hold multi-bit flip-flop

Method and device for evaluating performance of sequential logic el...

Die-to-die and chip-to-chip connectivity monitoring

3D stacked die test architecture

Integrated circuit including test circuit and method of manufacturi...

Adaptive port ceiling assignment for background I/O operations betw...

Test compression in a JTAG daisy-chain environment

Method and system for detecting glitch at high sampling rate

Multi-die debug stop clock trigger

Built-in self-test for die-to-die physical interfaces

Benchmark circuit on a semiconductor wafer and method for operating...

Fan-out buffer with skew control function, operating method thereof...

Burn-in resilient integrated circuit for processors

Register circuit with detection of data events, and method for dete...

Patents Applicationslast 30 patents

GENERATING A TEST PROGRAM

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

MEMORY DEVICE INCLUDING A PLURALITY OF PADS AND METHOD OF DETECTING...

SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS

Low Hold Multi-Bit Flip-Flop

MEMORY TIMING CHARACTERIZATION CIRCUITRY

3D STACKED DIE TEST ARCHITECTURE

DATA INTEGRITY CHECKING

MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION

DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME

ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES

ACCURATE CLOCK EDGE CALIBRATION OVER PVT CORNERS

MICROELECTRONIC CIRCUIT WITH DYNAMICALLY ADJUSTABLE COVERAGE FOR IN...

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

SYSTEM FOR AND METHOD OF IMPROVING THE YIELD OF INTEGRATED CIRCUITS

TECHNIQUES FOR INFIELD TESTING OF CRYPTOGRAPHIC CIRCUITRY

Clock Insertion Delay Systems and Methods

CHIP WITH CLOCK MASKING CIRCUIT

BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...

TESTING METHOD AND TESTING SYSTEM

ELECTRONIC DEVICE AND METHOD FOR PERFORMING CLOCK GATING IN ELECTRO...

GRPC-Based Chip Test Method, GRPC-Based Chip Test Apparatus, and St...

CIRCUIT SCREENING SYSTEM AND CIRCUIT SCREENING METHOD

Adaptive Port Ceiling Assignment for Background I/O Operations Betw...

CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION

CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION

Serial Protocol-Based Event Trigger

FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS