Timing aspects

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CPC
G01R31/31725

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31725Timing aspects

Industries

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Patents Grantslast 30 patents

Information Patent Grant
System and method for automatic fault detection in an electronic de...
- Patent number 12,332,304
- Issue date Jun 17, 2025
- Cadence Design Systems, Inc.
- Sushobhit Singh
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method to measure simulation to silicon timing correlation
- Patent number 12,332,305
- Issue date Jun 17, 2025
- MediaTek Singapore Pte Ltd.
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electronic device and method for performing clock gating in electro...
- Patent number 12,320,846
- Issue date Jun 3, 2025
- Realtek Semiconductor Corp.
- Ching-Feng Huang
- G01 - MEASURING TESTING
Information Patent Grant
Operating voltage adjustment for aging circuits
- Patent number 12,314,106
- Issue date May 27, 2025
- Advanced Micro Devices, Inc.
- Sriram Sambamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive voltage scaling using temperature and performance sensors
- Patent number 12,301,229
- Issue date May 13, 2025
- Texas Instruments Incorporated
- Jose Luis Flores
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating a signal test specification, data processing...
- Patent number 12,287,368
- Issue date Apr 29, 2025
- Rohde & Schwarz GmbH & Co. KG
- Markus Herdin
- G01 - MEASURING TESTING
Information Patent Grant
Detection circuit and detection method
- Patent number 12,270,856
- Issue date Apr 8, 2025
- Realtek Semiconductor Corporation
- Chun-Yi Kuo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mechanism capable of performing on-chip test and verification
- Patent number 12,253,564
- Issue date Mar 18, 2025
- Silicon Motion, Inc.
- Tse-Yen Liu
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for detecting defective logic devices
- Patent number 12,248,022
- Issue date Mar 11, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chi-Che Wu
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for capture clock control to minimize toggling...
- Patent number 12,241,931
- Issue date Mar 4, 2025
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Testing method and testing system
- Patent number 12,237,029
- Issue date Feb 25, 2025
- NANYA TECHNOLOGY CORPORATION
- Bo Jung Peng
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die aging measurements for dynamic timing modeling
- Patent number 12,216,150
- Issue date Feb 4, 2025
- Altera Corporation
- Dheeraj Subbareddy
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method to measure simulation to silicon timing correlation
- Patent number 12,216,159
- Issue date Feb 4, 2025
- MediaTek Singapore Pte Ltd.
- Ashish Kumar Nayak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Signal test
- Patent number 12,196,803
- Issue date Jan 14, 2025
- Infineon Technologies AG
- Muhammad Hassan
- G01 - MEASURING TESTING
Information Patent Grant
Method, arrangement, and computer program product for organizing th...
- Patent number 12,182,612
- Issue date Dec 31, 2024
- Minima Processor Oy
- Lauri Koskinen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System testing using partitioned and controlled noise
- Patent number 12,174,251
- Issue date Dec 24, 2024
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Grant
Circuit arrangement for validation of operation of a logic module i...
- Patent number 12,174,252
- Issue date Dec 24, 2024
- STMicroelectronics S.r.l.
- Diego Alagna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay measurement system and measurement method
- Patent number 12,169,222
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shang Hsien Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive body biasing or voltage regulation using slack sensors
- Patent number 12,169,221
- Issue date Dec 17, 2024
- Dolphin Design
- Sebastien Genevey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial test circuit for controllable Chiplets
- Patent number 12,135,354
- Issue date Nov 5, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,092,687
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applications of adaptive microelectronic circuits that are designed...
- Patent number 12,085,611
- Issue date Sep 10, 2024
- Minima Processor Oy
- Lauri Koskinen
- G01 - MEASURING TESTING
Information Patent Grant
Device interface board compliance testing using impedance response...
- Patent number 12,061,231
- Issue date Aug 13, 2024
- Celerint, LLC
- Howard H. Roberts
- G01 - MEASURING TESTING
Information Patent Grant
Sub-sampled based instrument noise correction for jitter measurements
- Patent number 12,055,585
- Issue date Aug 6, 2024
- Skyworks Solutions, Inc.
- Daniel de Godoy Peixoto
- G01 - MEASURING TESTING
Information Patent Grant
Silicon test structures for separate measurement of NMOS and PMOS t...
- Patent number 12,044,732
- Issue date Jul 23, 2024
- NVIDIA Corporation
- Prashant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flops and scan chain circuits including the same
- Patent number 12,044,733
- Issue date Jul 23, 2024
- Samsung Electronics Co., Ltd.
- Byounggon Kang
- G01 - MEASURING TESTING
Information Patent Grant
Low hold multi-bit flip-flop
- Patent number 12,040,800
- Issue date Jul 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TIME-ALIGNED RF ANALYSIS FROM GEOGRAPHICALLY DISTRIBUTED RECEIVERS
- Publication number 20250237699
- Publication date Jul 24, 2025
- Tektronix, Inc.
- G01 - MEASURING TESTING
Information Patent Application
TESTING CIRCUIT FOR TESTING ELECTRICAL DEVICES AND DEVICE UNDER TEST
- Publication number 20250216455
- Publication date Jul 3, 2025
- WINBOND ELECTRONICS CORP.
- Lih-Wei Lin
- G01 - MEASURING TESTING
Information Patent Application
DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD
- Publication number 20250216452
- Publication date Jul 3, 2025
- GETAC TECHNOLOGY CORPORATION
- CHIEN-CHIH HU
- G01 - MEASURING TESTING
Information Patent Application
TEST DEVICE PERFORMING TEST OPERATION ON LATCH CIRCUIT, OPERATING M...
- Publication number 20250216457
- Publication date Jul 3, 2025
- Samsung Electronics Co., Ltd.
- Sangin PARK
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE MULTILAYERED OVERRIDE SYSTEM AND METHOD FOR CIRCUMVENT...
- Publication number 20250216454
- Publication date Jul 3, 2025
- NXP B.V.
- Neha Srivastava
- G01 - MEASURING TESTING
Information Patent Application
ARCHITECTURE FOR TESTING MULTIPLE SCAN CHAINS
- Publication number 20250199069
- Publication date Jun 19, 2025
- STMicroelectronics International N.V.
- Enea Dimroci
- G01 - MEASURING TESTING
Information Patent Application
ERROR DETECTION SYSTEM APPLICABLE TO RTL MODULE AND OPERATION METHO...
- Publication number 20250189578
- Publication date Jun 12, 2025
- TELECHIPS INC.
- Yeongbeen KIM
- G01 - MEASURING TESTING
Information Patent Application
MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER
- Publication number 20250180645
- Publication date Jun 5, 2025
- QUALCOMM Incorporated
- Jais ABRAHAM
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and Method for Clock Frequency Estimation With Delayed Me...
- Publication number 20250180642
- Publication date Jun 5, 2025
- MICROCHIP TECHNOLOGY INCORPORATED
- Gary Qu Jin
- G01 - MEASURING TESTING
Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20250155502
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING METHOD AND MEMORY MODULE UNDER TEST
- Publication number 20250157557
- Publication date May 15, 2025
- NANYA TECHNOLOGY CORPORATION
- Bo Jung PENG
- G01 - MEASURING TESTING
Information Patent Application
ELECTRONIC DEVICE
- Publication number 20250147102
- Publication date May 8, 2025
- INFINEON TECHNOLOGIES AG
- Wei Wang
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND DEVICES FOR ANALYZING A DEVICE-UNDER-TEST
- Publication number 20250138089
- Publication date May 1, 2025
- ROHDE & SCHWARZ GMBH & CO. KG
- Gerd BRESSER
- G01 - MEASURING TESTING
Information Patent Application
CLOCK SYNCHRONIZATION CIRCUIT
- Publication number 20250116702
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David P MAGEE
- G01 - MEASURING TESTING
Information Patent Application
Scan Data Transfer Circuits for Multi-die Chip Testing
- Publication number 20250093416
- Publication date Mar 20, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
SUB-SAMPLED BASED INSTRUMENT NOISE CORRECTION FOR JITTER MEASUREMENTS
- Publication number 20250067801
- Publication date Feb 27, 2025
- Skyworks Solutions, Inc.
- Daniel de Godoy Peixoto
- G01 - MEASURING TESTING
Information Patent Application
DELAY MEASUREMENT SYSTEM AND MEASUREMENT METHOD
- Publication number 20250060410
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- SHANG HSIEN YANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHODS FOR VOLTAGE DROOP DETECTION IN DIE ARCHITECTURES
- Publication number 20250052812
- Publication date Feb 13, 2025
- QUALCOMM Incorporated
- Amit ANEJA
- G01 - MEASURING TESTING
Information Patent Application
GENERATING A TEST PROGRAM
- Publication number 20240426906
- Publication date Dec 26, 2024
- Teradyne, Inc.
- Charles J. Carline
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE INCLUDING A PLURALITY OF PADS AND METHOD OF DETECTING...
- Publication number 20240402248
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- Dojong CHUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS
- Publication number 20240369631
- Publication date Nov 7, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G01 - MEASURING TESTING
Information Patent Application
Low Hold Multi-Bit Flip-Flop
- Publication number 20240333265
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY TIMING CHARACTERIZATION CIRCUITRY
- Publication number 20240319269
- Publication date Sep 26, 2024
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DATA INTEGRITY CHECKING
- Publication number 20240319272
- Publication date Sep 26, 2024
- Imagination Technologies Limited
- Ross Martin Torkington
- G01 - MEASURING TESTING
Information Patent Application
MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION
- Publication number 20240310436
- Publication date Sep 19, 2024
- SILICON MOTION, INC.
- Tse-Yen Liu
- G01 - MEASURING TESTING
Information Patent Application
DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME
- Publication number 20240295603
- Publication date Sep 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-En Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES
- Publication number 20240288494
- Publication date Aug 29, 2024
- Meta Platforms Technologies, LLC
- Sri Harsha Manjunath
- G01 - MEASURING TESTING

Timing aspects

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

System and method for automatic fault detection in an electronic de...

Circuit and method to measure simulation to silicon timing correlation

Electronic device and method for performing clock gating in electro...

Operating voltage adjustment for aging circuits

Adaptive voltage scaling using temperature and performance sensors

Method for generating a signal test specification, data processing...

Detection circuit and detection method

Mechanism capable of performing on-chip test and verification

Method and apparatus for detecting defective logic devices

Method and apparatus for capture clock control to minimize toggling...

Testing method and testing system

On-die aging measurements for dynamic timing modeling

Circuit and method to measure simulation to silicon timing correlation

Device access port selection

Signal test

Method, arrangement, and computer program product for organizing th...

System testing using partitioned and controlled noise

Circuit arrangement for validation of operation of a logic module i...

Delay measurement system and measurement method

Adaptive body biasing or voltage regulation using slack sensors

Selectable JTAG or trace access with data store and output

Serial test circuit for controllable Chiplets

Interface to full and reduced pin JTAG devices

Selectable JTAG or trace access with data store and output

Applications of adaptive microelectronic circuits that are designed...

Device interface board compliance testing using impedance response...

Sub-sampled based instrument noise correction for jitter measurements

Silicon test structures for separate measurement of NMOS and PMOS t...

Flip-flops and scan chain circuits including the same

Low hold multi-bit flip-flop

Patents Applicationslast 30 patents

TIME-ALIGNED RF ANALYSIS FROM GEOGRAPHICALLY DISTRIBUTED RECEIVERS

TESTING CIRCUIT FOR TESTING ELECTRICAL DEVICES AND DEVICE UNDER TEST

DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD

TEST DEVICE PERFORMING TEST OPERATION ON LATCH CIRCUIT, OPERATING M...

CONFIGURABLE MULTILAYERED OVERRIDE SYSTEM AND METHOD FOR CIRCUMVENT...

ARCHITECTURE FOR TESTING MULTIPLE SCAN CHAINS

ERROR DETECTION SYSTEM APPLICABLE TO RTL MODULE AND OPERATION METHO...

MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER

Apparatus and Method for Clock Frequency Estimation With Delayed Me...

DEVICE ACCESS PORT SELECTION

TESTING METHOD AND MEMORY MODULE UNDER TEST

ELECTRONIC DEVICE

METHODS AND DEVICES FOR ANALYZING A DEVICE-UNDER-TEST

CLOCK SYNCHRONIZATION CIRCUIT

Scan Data Transfer Circuits for Multi-die Chip Testing

SUB-SAMPLED BASED INSTRUMENT NOISE CORRECTION FOR JITTER MEASUREMENTS

DELAY MEASUREMENT SYSTEM AND MEASUREMENT METHOD

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

APPARATUS AND METHODS FOR VOLTAGE DROOP DETECTION IN DIE ARCHITECTURES

GENERATING A TEST PROGRAM

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

MEMORY DEVICE INCLUDING A PLURALITY OF PADS AND METHOD OF DETECTING...

SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS

Low Hold Multi-Bit Flip-Flop

MEMORY TIMING CHARACTERIZATION CIRCUITRY

3D STACKED DIE TEST ARCHITECTURE

DATA INTEGRITY CHECKING

MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION

DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME

ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES