Claims
- 1. A method for forming an insulated-gate field effect transistor in a surface of a semiconductor, comprising:
- forming an insulator layer over selected portions of said surface to define an active region;
- forming a gate dielectric over said active region;
- forming a gate electrode over a selected portion of said gate dielectric and extending onto said insulator layer;
- forming a source and a drain region of a first conductivity type on opposing sides of said gate electrode, said drain region extending to the edge of said insulator layer at a location adjacent to said gate electrode; and
- forming a guard region of a second conductivity type at a location between said source region and the edge of said said insulator layer at a location adjacent said gate electrode.
- 2. The method of claim 1 wherein said step of forming the guard region follows said step of forming the source and drain regions.
- 3. The method of claim 2, wherein said step of forming the guard region precedes said step of forming the source and drain regions.
- 4. The method of claim 1, further comprising:
- forming a silicide film over said source, drain and guard regions.
- 5. The method of claim 1, further comprising:
- forming a channel stop region of said second conductivity type at the locations of said insulator layer,
- prior to forming said insulator layer.
- 6. The method of claim 1, further comprising, prior to forming said insulator layer:
- forming an insulator layer over the surface of a body; and
- forming a semiconductor layer over said insulator layer;
- wherein said surface is the surface of the semiconductor layer.
Parent Case Info
This is a division of application Ser. No. 07/150,799, filed Feb. 11, 1988, now U.S. Pat. No. 4,974,051.
Government Interests
This invention was made with Government support under contract No. DNA 001-86-C-0090 awarded by the Defense Nuclear Agency. The Government has certain rights in this invention.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0010247 |
Jan 1982 |
JPX |
Non-Patent Literature Citations (3)
Entry |
Lee et al., "Island Effects in CMOS/SOS Transistors", IEEE Trans. E.D., vol. ED-25, No. 8 (Aug. 1978), pp. 971-978. |
Tihanyi, et al., "Properties of ESFI MOS Transistors Due to the Floating Substrate and the Finite Volume", IEEE Trans. E.D., vol. ED-22, No. 11, (Nov. 1975), pp. 1017-1023. |
Tihany, et al., "Influence of the Floating Substrate Potential on the Characteristics of EFSI MOS Transistors", Solid State Electrons, vol. 18 (Pergamon, 1975), pp. 309-314. |
Divisions (1)
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Number |
Date |
Country |
Parent |
150799 |
Feb 1988 |
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