Patent Application
20170358508
The present disclosure relates to the technical field of display, and more particularly, to a motherboard of an array substrate and a manufacturing method thereof.
Thin film transistor-liquid crystal display panel (TFT-LCD) is a flat panel display device. Because of its advantages of small size, low power consumption, no radiation, and relatively low production cost, it is applied in the field of high-performance display more and more.
A conventional liquid crystal display panel mainly includes an array substrate, a color film substrate, and a liquid crystal layer, wherein a plurality of thin film transistors (TFT) are formed on the array substrate. After the manufacturing process for the array substrate is completed, it is usually required to test characteristics of the thin film transistors on the array substrate. However, since thin film transistors on an array substrate are usually covered by a protective layer, the test of the characteristic of the thin film transistor is very inconveniently. Especially for a liquid crystal display panel in an advanced super-dimensional switching (ADS) mode, there is no effective way currently to confirm the characteristic of TFT in a display area, after the manufacturing process of the array substrate is completed. Thus, it cannot be determined accurately whether a characteristic of thin film transistor in a display area is abnormal, thereby resulting in great inconvenience to subsequent development work. The development efficiency is affected, and moreover, an occurred problem cannot be resolved in the first time. The production cost increases potentially.
Embodiments of the present disclosure provide a motherboard of an array substrate and a manufacturing method thereof, which may facilitate the test of a characteristic of a thin film transistor on the motherboard of an array substrate.
A first aspect of the present disclosure provides a motherboard of an array substrate including a plurality of display areas and a plurality of non-display areas. The non-display area is located between adjacent display areas. The display area includes a first pixel unit configured for display. The non-display area includes a second pixel unit configured to test a characteristic of a thin film transistor on the motherboard of an array substrate.
In embodiments of the present disclosure, the first pixel unit includes a first thin film transistor and a first pixel electrode connected to the first thin film transistor. The first pixel electrode is covered with an insulating protective layer. The second pixel unit includes a second thin film transistor and a second pixel electrode connected to the second thin film transistor. The second pixel electrode is exposed to input and/or output a test signal.
In embodiments of the present disclosure, the first thin film transistor and the second thin film transistor are formed simultaneously, and the first pixel electrode and the second pixel electrode are formed simultaneously.
In embodiments of the present disclosure, the second pixel electrode is located below or above a drain electrode of the second thin film transistor.
In embodiments of the present disclosure, a common electrode is provided on the insulating protective layer. Both the first pixel electrode and the second pixel electrode are planar electrodes, and the common electrode is a comb-shaped electrode.
A second aspect of the present disclosure provides a manufacturing method for a motherboard of an array substrate. The motherboard of an array substrate includes a plurality of display areas and a plurality of non-display areas. The non-display areas are located between adjacent display areas. The manufacturing method includes manufacturing a first pixel unit in the display area. The first pixel unit is configured for display. The manufacturing method further includes manufacturing a second pixel unit in the non-display area. The second pixel unit is configured to test a characteristic of a thin film transistor on the motherboard of an array substrate.
In embodiments of the present disclosure, the first pixel unit includes a first thin film transistor and a first pixel electrode connected to the first thin film transistor. The first pixel electrode is covered with an insulating protective layer. The second pixel unit includes a second thin film transistor and a second pixel electrode connected to the second thin film transistor. The second pixel electrode is exposed to input and/or output a test signal.
In embodiments of the present disclosure, the first thin film transistor and the second thin film transistor are formed simultaneously, and the first pixel electrode and the second pixel electrode are formed simultaneously.
In embodiments of the present disclosure, the second pixel electrode is located below or above a drain electrode of the second thin film transistor.
In embodiments of the present disclosure, a common electrode is provided on the insulating protective layer. Both the first pixel electrode and the second pixel electrode are planar electrodes, and the common electrode is a comb-shaped electrode.
Embodiments of the present disclosure provide a motherboard of an array substrate. A first pixel unit is provided in a display area, and a second pixel unit is provided in a non-display area between two adjacent display areas. In adjacent display area and non-display area, thin film transistors in the first pixel unit and in the second pixel unit have the same or similar characteristics. By testing the second pixel unit to understand a characteristic of a thin film transistor in the non-display area, it is possible to reflect a characteristic of a thin film transistor in the adjacent display area well. It is advantageous in finding a defect of the thin film transistors on the motherboard of an array substrate. The corresponding countermeasures may be taken to avoid a subsequence of a large number of bad products. Material may be saved, and product development may be improved.
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the drawings described below merely relate to some embodiments of the present disclosure, rather than limit the present disclosure, in which:
Hereinafter, the embodying manner of the present disclosure will be further described in detail, in combination with the accompanying drawings and embodiments. The following embodiments are intended to illustrate the disclosure, rather than limit the scope of the disclosure.
Embodiments of the present disclosure provide a motherboard of an array substrate, including a plurality of display areas and a plurality of non-display areas. The non-display area is located between adjacent display areas. The display area includes a first pixel unit configured for display. The non-display area includes a second pixel unit configured to test a characteristic of a thin film transistor on the motherboard of an array substrate.
In the motherboard of an array substrate provided in embodiments of the present disclosure, a second pixel unit is provided in a non-display area between two adjacent display areas. With the second pixel unit, it is possible to test a characteristic of a thin film transistor on the non-display area, which is able to reflect a characteristic of a thin film transistor on the display area. It is advantageous in finding defects of the thin film transistors on the motherboard of an array substrate. A subsequence of a large number of bad products may be avoided. Material may be saved, and product development may be improved.
The motherboard of an array substrate in the present disclosure may be cut to form a plurality of independent array substrates for display devices, each of which includes a display area and a peripheral non-display area on the motherboard of an array substrate. The display area of the array substrate corresponds to a display area of the display device, and the non-display area may correspond to a bezel position of the display device.
The display area 110 is provided with a plurality of crossed gate lines and data lines. A plurality of first pixel units are divided and arranged in a matrix by the plurality of crossed gate lines and data lines. Each of the plurality of first pixel units is used for controlling the twist of liquid crystal molecules in a corresponding area in the liquid crystal layer, so as to enable the display device to display the corresponding picture.
The non-display area 120 may likewise be provided with a plurality of crossed gate lines and data lines, so as to obtain a plurality of second pixel units arranged in a matrix, for testing a characteristic of a thin film transistor (also referred as TFT Character) on the motherboard of an array substrate.
In the non-display area 120, the second pixel unit includes a second thin film transistor and a second pixel electrode 124 connected to the second thin film transistor. The second thin film transistor includes a gate electrode 121, a gate insulating layer 122, an active layer 123, a source electrode 125, and a drain electrode 126 provided on the base substrate 130. The gate electrode 121 is connected to a gate line in this area, the source electrode 125 is connected to a data line in this area, and the drain electrode 126 is connected to the second pixel electrode 124. Unlike the first pixel unit in the display area, the second pixel electrode in the non-display area is exposed to input and/or output a test signal.
When testing a characteristic of a thin film transistor on the above-mentioned motherboard of an array substrate, the characteristic of the thin film transistor in the non-display area can be determined, only by applying a test signal to the second pixel electrode, a data driven chip (IC), a gate driven circuit (e.g. a GOA unit) in the non-display area, and detecting the corresponding feedback signal. Since the non-display area is located between two display areas, the characteristic of the thin film transistor in the display area can be also reflected well. Thus, more accurate test value of the characteristic of the thin film transistor in the display area may be obtained, and further, TFT-related defects may be found at the first time.
In embodiments of the present disclosure, to make the test value of the characteristic of the thin film transistor in the non-display area closer to the characteristic of the thin film transistor in the display area, the first thin film transistor is formed simultaneously with the second thin film transistor, and the first pixel electrode is formed simultaneously with the second pixel electrode.
In the motherboard of an array substrate provided by the present disclosure, the first thin film transistor has the same structure as the second thin film transistor, and the first pixel electrode has the same structure as the second pixel electrode. The test can be done well only by exposing the second pixel electrode in the non-display area. Therefore, in the manufacturing process for the insulating protective layer (PVX layer), the PVX material may not be deposited over the whole non-display area, or the PVX material may not be deposited only on the area of the second pixel electrode. For example, the manufacturing processes for the gate line, the data line, the thin film transistor, and the pixel electrode of the non-display area can be completed in synchronization with the display area in a conventional manufacturing process for array substrates. The subsequent manufacturing process of the insulating protective layer and the common electrode is performed only for the display area. Thus, the display area is formed with a capacitor composed of the common electrode and the first pixel electrode, and only the thin film transistor and the pixel electrode are manufactured in the non-display area. As a result, the second pixel electrode is exposed.
In addition, it is possible to make the non-display area and the display area identical in the existing manufacturing process. After all the existing processes are completed, the insulating protective layer and the common electrode layer on the entire non-display area are removed, or only the insulating protective layer and the common electrode layer on the second pixel electrode are removed. As a result, the above-mentioned motherboard of an array substrate is also obtained.
In addition, in the present disclosure, as shown in
The motherboard of an array substrate in embodiments of the present disclosure may be in an ADS mode. In the motherboard of an array substrate in this mode, both the first pixel electrode and the second pixel electrode are planar electrodes and the common electrode is a comb-shaped electrode.
Embodiments of the present disclosure provide the motherboard of an array substrate. A second pixel unit is provided in a non-display area between two adjacent display areas. A pixel electrode of the second pixel unit is exposed. Through the pixel electrode of the second pixel unit, a test signal may be inputted or outputted, to obtain a characteristic of the thin film transistor on the non-display area. Since the non-display area is located between two display areas, the characteristic of the thin film transistor in the display area are also well reflected. A test value closer to the characteristic of the thin film transistor on the display area may be obtained. It is advantageous in finding the TFT switch defects on the motherboard of an array substrate in time. The subsequence of a large number of bad products may be avoided. Material may be saved, and product development may be improved. In addition, since the second pixel unit is provided in the non-display area, the height difference between the non-display area and the display area can be reduced. Further, the rubbing Mura can be prevented in the subsequent rubbing orientation process.
Embodiments of the present disclosure further provide a manufacturing method for a motherboard of an array substrate. The motherboard of an array substrate includes a plurality of display areas and a plurality of non-display areas. The non-display area is located between adjacent display areas. The manufacturing method includes manufacturing a first pixel unit in a display area. The first pixel unit is configured for display. The manufacturing method further includes manufacturing a second pixel unit. The second pixel unit is configured to test the characteristic of the thin film transistor on the motherboard of an array substrate.
The first pixel unit includes a first thin film transistor and a first pixel electrode connected to the first thin film transistor. The first pixel electrode is covered with an insulating protective layer. The second pixel unit includes a second thin film transistor and a second pixel electrode connected to the second thin film transistor. The second pixel electrode is exposed to input and/or output a test signal.
In embodiments of the present disclosure, to make the test value of the thin film transistor obtained as described above closer to the characteristic of the thin film transistor in the display area, the first thin film transistor is formed simultaneously with the second thin film transistor, and the first pixel electrode is formed simultaneously with the second pixel electrode.
In embodiments of the present disclosure, the second pixel electrode may be located below or above the drain electrode of the second thin film transistor.
In embodiments of the present disclosure, the above method can be used for manufacturing an ADS mode product. In the motherboard of an array substrate in this mode, both the first pixel electrode and the second pixel electrode are planar electrodes, and the common electrode is a comb-shaped electrode.
The above embodiments are merely illustrative of the present disclosure and are not intended to limit the present disclosure, and various changes and modifications may be made by those of ordinary skill in the art without departing from the spirit and scope of the disclosure. Therefore, all the equivalent technical solutions are also within the scope of the present disclosure, and the scope of patent protection of the present disclosure is defined by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201510335191.1 | Jun 2015 | CN | national |
This patent application is a National Stage Entry of PCT/CN2016/078663 filed on Apr. 7, 2016, which claims the benefit and priority of Chinese Patent Application No. 201510335191.1 filed on Jun. 16, 2015, the disclosures of which are incorporated herein in their entirety as part of the present application.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2016/078663 | 4/7/2016 | WO | 00 |
