Patent Application
20080211568
Integrated circuits (ICs) contain many devices such as transistors, diodes and others, which may be arranged to perform different functions. Devices may be combined to form logic circuits, modules, function blocks, processor stages, etc. Commonly, many of the devices are not used for various periods of time, but still consume power at least because of leakage currents.
Leakage currents are a significant challenge for sub-100 nm CMOS (Complementary Metal-Oxide Semiconductor) technologies. To reduce leakage currents during standby modes, when selected portions of circuits are not being utilized, modern CMOS integrated circuits use CMOS power switches to disconnect them from on-chip power supplies. Power switches are an elementary part of leakage reduction strategies and are applied in a broad range of products, such as baseband-ICs, microcontrollers, DSPs (digital signal processors), memories and microprocessors.
In conventional planar bulk CMOS technologies, typically only one type of field effect transistor (FET), either an nFET or pFET type of power switch is used to implement power switches. Due to their better current driving abilities, nFET type power switches are preferred since they provide the same low-resistive connection of virtual power supply lines to unswitched power supply lines as pFET type power switches at a much smaller transistor width and hence have lower leakage current. However, nFET type power switches require a triple well isolation in order to isolate the floating body potential referred to as VSSBULK (voltage source bulk) within a deactivated circuit block from the remaining parts of the chip. On the other hand, if pFET type power switches are used, a natural isolation is provided due to the separation of n-wells but result in an area overhead of approximately twice compared to nFET type power switches is generated.
These tradeoffs require a designer to choose between low process complexity and larger area in the case of pFET type power switches and smaller area and increased process complexity for nFET type power switches. Both alternatives are suboptimal.
In the following description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments which may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the scope of the present invention. The following description of example embodiments is, therefore, not to be taken in a limited sense, and the scope of the present invention is defined by the appended claims.
MuGFET (multi-gate field effect transistor) power switches may be used to selectively isolate or disconnect circuits from various voltages, such as ground or supply voltages. Several example circuits, including sub-circuits are shown and described. One or more arrays of power switches are also described and may be formed with the same or different current characteristics to facilitate different operating levels and different timing for reactivating sub-circuits.
The circuit 110 is also coupled to a further voltage supply 125, which in one embodiment is ground or VSS. In one embodiment, a small voltage, ΔV, drop may occur across power switch 115, such that a virtual voltage 130, referred to as VDDV in one embodiment, is provided to power the circuit 110. This voltage drop may be caused by an ohmic resistance of the MuGFET power switch 115. In one embodiment, the circuit 110 includes MuGFET transistors.
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As described above with respect to circuit 110, the MuGFET power switches may be used to selectively isolate the circuits from various voltage supplies, or may be partially turned on to provide for operation of the circuit at a reduced voltage and hence reduced power level. The use of MuGFET power switches may provide for excellent isolation of the circuits due to their formation on a buried oxide layer on the substrate and no bulk contact. Other potential benefits that may be provided by the use of MuGFET power switches are fast turn on times and low substrate area requirements. Both n-type and p-type MuGFET power switches may have similar drive currents. This symmetry provides an additional degree of freedom for circuit designers since leakage current reduction is fairly independent of the type of MuGFET power switch used. Designs may be implemented in a flexible manner with both n-type and p-type types of MuGFET power switches.
Each power switch may result in a drop of ΔV from VDD, further resulting in the sub-circuits being provided a supply voltage of VDD-ΔV, referred to as a virtual voltage or VDDV as an operating supply voltage for the sub-circuit when the power switches are on. Turning the power switches off results in isolation of the sub-circuits from the supply voltage. In further embodiments, a single power switch may be used for all three sub-circuits. In still further embodiments, the power switches are controlled independently, allowing their corresponding sub-circuits to be activated or deactivated independently and in desired order, such as in a staggered manner. In still further embodiments, the power switch transistors may receive signals at the same time to switch on, but may have different current characteristic designed to provide a desired temporal order of reactivation of sub-circuits that are isolated, off, or partially turned on for power reduction.
Each power switch may result in a drop of ΔV from VSS, further resulting in the sub-circuits being provided a supply voltage of VSS+ΔV, referred to as a virtual voltage or VSSV as a ground supply voltage for the sub-circuit when the power switches are on. Turning the power switches off results in isolation of the sub-circuits from this supply voltage, and the sub-circuits float toward the other supply voltage, for example, VDD. In further embodiments, a single power switch may be used for all three sub-circuits. In still further embodiments, the power switches are controlled independently, allowing their corresponding sub-circuits to be turned on or off independently and in desired order, such as in a staggered manner. In still further embodiments, the transistors may receive signals at the same time to switch on, but may have different current characteristic designed to provide a desired temporal order of reactivation of sub-circuits that are isolated, off, or partially turned on for power reduction.
Each power switch may result in a difference of ΔV from respective supply voltages, such as for example VDD−ΔV or VSS+ΔV when the power switches are on. Turning the power switches off results in isolation of the sub-circuits from the supply voltage, and they tend to float toward the supply to which they are still coupled. In still further embodiments, the power switches are controlled independently, allowing their corresponding sub-circuits to be turned on or off independently and in desired order, such as in a staggered manner. In still further embodiments, the transistors may receive signals at the same time to switch on, but may have different current characteristic designed to provide a desired temporal order of reactivation of circuits that are isolated, off, or partially turned on for power reduction.
When second power switch 433 is off, an output 440 of the NAND gate 425 floats toward VSS. Output 440 is coupled to a second inverter 445, which is coupled to a third n-type MuGFET power switch 450, which in turn is coupled to VSS 455. The second inverter 445 is also coupled to VDD at 460 and has an output 465 that floats to VDD when the third power switch 450 is off.
Circuit 400 illustrates the use of n and p-type MuGFET power switches on individual devices in a circuit, and further illustrates that superior isolating characteristics of the MuGFET power switches enables such discrete device level power control with alternating chains of logic gates or elements connected to different supply voltages. In one embodiment, the logic gates may be selected from CMOS logic gates such as NAND gates, inverter gates, AND gates, OR gates or others. This is a very fine granularity that provides each input gate with a stable and full-swing input during standby or reduced power conditions. It also enables a faster reactivation which avoids intermediate voltage levels at gate inputs. The use of MuGFET power switches may reduce the need for separation between prior CMOS power switches, reducing overall demand for chip real estate. In one embodiment, the elements are formed with MuGFET transistors, further enhancing isolation of the circuits due at least to their formation on an insulating layer.
One motivation for a fine granular use of MuGFET power switches is that it may provide for very fast reactivation. If one million gates share a line, a large charge may be required to reactivate all the devices. With an individual power switch on each gate, or small numbers of gates, the need for a large charge is reduced, and such gates may be reactivated quickly.
In one embodiment, the core 510 is selectively coupled to a supply voltage such as VSS 525 by a n-type MuGFET power switch 530. The core 510 is also coupled to a second supply voltage such as VDD 535. Access circuitry 515 is coupled to VDD 545 via a p-type MuGFET power switch 550 and is coupled to VSS 545. ΔV drops across the power switches result in virtual supply levels being provided to the core 510 and access circuitry 515 in some embodiments. The use of p-type MuGFET power switch 550 to isolate the access circuitry from VDD, causes the word lines 520 to float toward VSS. As long as the n-type MuGFET power switch is active, i.e. couples VSSV to VSS, the content of the memory cells is preserved, as the word lines 520 float to VSS and ensure that the memory cells within array 510 are isolated from bit lines by stable wordline voltages that switches the n-type access devices in the memory cells off. When the n-type MuGFET power switch 530 is off, memory content of the cells is lost as the cells float toward VDD. This power switch granularity level may be thought of as medium granularity, since it is less granular than the individual logic element implementations.
The stages are each coupled to a first supply voltage, such as power supply VDD at 615, 617, 619, 621 and 623 and to a second supply voltage such as a ground or VSS at 625, 627, 629, 630 and 631. In one embodiment, instruction fetch stage 605 is coupled to VDD 615 via a p-type MuGFET power switch 635. Instruction decode stage 607 is coupled to VDD 617 via a p-type MuGFET power switch 637. Execute stage 609 is coupled to VSS 629 via an n-type MuGFET power switch 639. Memory access stage 611 is coupled to VDD 621 via a p-type MuGFET power switch 641. Register write 613 is coupled to VSS 631 via an n-type MuGFET power switch 643. As previously described, each power switch may result in a voltage drop, such as ΔV between the stages and the supplies, resulting in virtual supply voltages being provided to the stages.
Sharing of power switches of the same type is done in one embodiment if the stages are activated and deactivated simultaneously. In some embodiments, it may be desirable to activate and deactivate the different stages at different times. Where there are parallel stages, they may be activated and deactivated together, or independently if desired. The assignment of n type and p type MuGFET power switches may done to optimize or control overall leakage and provide selective reactivation as a function of workload and specific instructions of sub-components. These considerations may result in very different assignments of power switches in various embodiments.
Such power switches may be used in any pipeline system with an arbitrary number of stages. Each stage may have a register on an output. If clock gating is used to save active power in the registers, power supplies to the stages may also be gated. Controlling power switches and clock gating may be done using the same or a derived control signal. Reactivating stages may be done only if the stage is needed for current operations. In still further embodiments, different stages may be deactivated and reactivated during individual clock cycles.
An array 820 of n-type MuGFET power switches is provided. At 825, a further array of n-type MuGFET power switches having different turn-on characteristics may be provided. Power switches from the various arrays may be coupled to circuits 830 as desired.
Individual power switches may be coupled to different circuit elements, stages, devices, etc., and may provide desired turn-on times to result in such elements turning on at a desired time in relation to other elements without the need for staggering signals to the power switches. Staggering the signals to the power switches may also be done in some embodiments. Ramping of signals and providing different voltages may also result in providing different activation times.
In one embodiment, the arrays of p and n-type MuGFET power switches are physically separated to allow for different processing to provide such different characteristics. For example, different fin heights, different thickness oxide layers over gates, gate lengths and other means of providing MuGFET power switches with different figures of merit may be used.
In further embodiments, distributed power switches or a central block of power switches may be provided to power off different devices.
The Abstract is provided to comply with 37 C.F.R. §1.72(b) to allow the reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
