The present invention is directed toward a multi-bit magnetic tunnel junction memory and toward a method of forming same, and, more specifically, toward a multi-bit magnetic tunnel junction memory having a plurality of free magnetic elements associated with a unitary fixed magnetic layer and toward a method of forming same.
A spin-torque transfer (STT) magnetic tunnel junction (MTJ) element comprises a fixed magnetic layer, the magnetic state of which is fixed, and a free magnetic layer, the magnetic state of which is selectively reversible, The fixed and free layers are separated by a magnetic barrier or junction layer. The STT-MTI element is switchable between two mutually opposite, stable magnetization states—“parallel” (P) and “anti-parallel” (AP), by passing an electric write current through its layers. If the write current is above a given critical point the STT-MTJ will switch into the P or AP state induced by the direction of the write current. A conventional STT-MTJ memory cell stores one bit, with one of the P and AP states assigned to represent a first binary value, e.g., a “0”, and the other assigned to represent a second binary value, e.g., a “1.” The stored binary value can be read because STT-MTJ elements have a lower electrical resistance in the P state than the AP state.
Conventional STT-MTJ memory employs write circuitry designed to inject a write current having a magnitude high enough and duration long enough to ensure it switches the STT-MTJ element to the desired P/AP state. Conventional design philosophy for STT-MTI memory is therefore a “deterministic” writing confined to the design paradigm of conventional memories, such as SRAM, where the switching of memory elements is deterministic.
It is also known to provide a cluster of STT-MTJ cells to form a memory element that can take on one of a plurality of different states depending on how many of the STT--MTJ cells are in a parallel states and how many of the STT-MTJ cells are in an anti-parallel state. A cluster having N STT-MTJ cells can take on any one of 2n different states and thus present one of 2n different resistances to a measurement circuit,
Such a measurement only requires access to the input and output of the overall STT-MTJ cluster and does not require access to or knowledge of the states of any of the individual STT-MTJ cells.
A probabilistic programming current (PGC) source 110 controlled by a probabilistic programming (PPG) controller unit 112 couples to the BL line 104 and to the SL line 108. An N+1 level voltage detector 114 may have a sense input 114A coupled to the BL line 104 though a read enabling switch 116, and a sense input 114B coupled to an M-bit to Nil level converter 118. The M-bit data to N+1 level converter 118 may convert the M-bit data into an N+1 level target resistance voltage signal. The N+1 level converter 118 may provide a. compare signal to the PPG controller 112. It will be understood that the N+1 level voltage detector 114 may include a read current source (not explicitly shown) to inject a read current via the BL line 104 through the N-element STT-MTJ cluster cell 102.
In operation, the PPG controller 112 causes the PGC current source 110 to apply a current to the SL line 108 and the enabling switch 106 is activated to apply this current to the N-element STT-MTJ cluster cell 102. The current level and duration are selected such that, with each current application, there is a. predetermined chance of switching the state of one of the N STT-MTJ elements 102-1 through 102-N from a first state to a second state, based on the direction of the current. After a current is applied, the N+1 level voltage detector 114 measures the resistance of the N-element STT-MTJ cluster cell 102 to determine how many of the STT-MTJ cells are in the desired state, and current is applied in a required direction until the desired resistance level of the N-element STT-MTJ cluster cell 102 is obtained. In this manner, the N-element STT-MTI cluster cell 102 can represent 2n bits of information. The N-element STT-MTJ cluster cell 150 may be controlled and used to store multiple bits of data in a similar manner.
STT-MTJ cell clusters as discussed above are useful to provide multi-bit storage in a given area h is desirable to increase the density of STT-MTJ elements in an STT-MTJ cluster while maintaining the aforementioned functionalities.
An exemplary embodiment includes a spin-torque transfer (STT) magnetic tunnel junction (MTJ) memory having a first unitary fixed magnetic layer, a first magnetic barrier layer on the first unitary fixed magnetic layer, a first free magnetic layer comprising a first plurality of free magnetic islands on the first magnetic barrier layer, and a cap layer overlying the first free magnetic layer.
Another embodiment comprises a method of forming an STT-MTJ memory that includes providing a first unitary fixed magnetic layer, forming a first magnetic barrier layer on the first unitary fixed magnetic layer, forming a first free magnetic layer, comprising a plurality of free magnetic islands, on the first magnetic barrier layer, and providing a cap layer overlying the first free magnetic layer.
A further embodiment includes an STT-MTJ memory that include a first unitary fixed magnetic layer, a first magnetic barrier layer arrangement on the first unitary fixed magnetic layer, a first free magnetic layer arrangement comprising a first plurality of free magnetic islands on the first magnetic barrier layer arrangement and a cap layer arrangement overlying the first free magnetic layer arrangement.
Another embodiment comprises a method of forming an STT-MTJ memory that includes a step for providing a first unitary fixed magnetic layer, a step for forming a first magnetic barrier layer on the first unitary fixed magnetic layer, a step for forming a first free magnetic layer, comprising a plurality of free magnetic islands, on the first magnetic barrier layer, and a step for providing a cap layer overlying the first free magnetic layer.
The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments of the invention” does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example. “logic configured to” perform the described action.
Referring now to
A first magnetic barrier layer 206, sometimes referred to as a “junction layer,” comprising a unitary layer of material, is formed on the first unitary fixed magnetic layer 202, and a first free magnetic layer 208 is formed on the first magnetic barrier layer 206. The first free magnetic layer 208 comprises first plurality of individual free magnetic islands 210 each of which is in contact with the first magnetic barrier layer 206 but which are separated from one another by first regions 212 of electromagnetic insulating material, The first magnetic barrier layer 206 is substantially homogenous, and its properties are substantially similar in regions underlying the first free magnetic islands 210 and in regions beneath the first plurality of regions 212 of electromagnetic insulating material.
Each of the first plurality of free magnetic islands 210 has a footprint over the first unitary fixed magnetic layer 202 and forms, with the region of first magnetic barrier layer 206 between each of the first plurality of five magnetic islands 210 and the portion of the first unitary fixed magnetic layer 202 therebeneath, a magnetic tunnel junction 211, The general location of a single magnetic tunnel junction 211 is illustrated with a dashed outline in
The aforementioned first anti-ferromagnetic layer 204 is mounted on a connection layer 216, which may be formed, for example, of tantalum, and a first line 218 is electrically connected to the connection layer 216 and to a bit line/source line 220. A second line 222 connects the cap layer 214 to a switch 224 which in turn is controllable to selectably connect the cap layer 214 to a source line/bit line 226. Like the connection layer 216, the cap layer 214 may be formed from tantalum, or, alternately, may include layers of tantalum and other materials such as ruthenium or magnesium oxide, or may be formed of tantalum nitride or titanium nitride. The bit line/source line 220 and the source line/bit line 226 are connected to a control circuit generally similar to the circuit illustrated in
The use of a common or shared fixed magnetic layer in association with multiple free magnetic islands 210 beneficially lowers the energy required for switching an STT-MTJ, and the energy required for switching all the magnetic tunnel junctions 211 formed by the first plurality of free magnetic islands 210 is less than that required for switching an STT-MTJ having a free layer with an area equal to the combined areas of all the first plurality of free magnetic islands 210. Using unitary layers of material, such as the first unitary fixed magnetic layer 202 and the first magnetic barrier layer 206 also provides an improved yield and increases tolerance for manufacturing defects in these layers. Furthermore, the large area of the first unitary fixed magnetic layer 202 makes this layer more magnetically stable than individual regions of fixed magnetic material in conventional STT-MTJ's, and the size of the first unitary fixed magnetic layer 202 also increases the tunnel magnetoresistance of the STT-MTJ's formed by this layer.
The STT-MTJ cluster cells of the foregoing embodiments are useful in various fields and devices and may, for example, be integrated into one or more semiconductor dies. The STT-MTJ cluster cells may also be used in various devices including, without limitation, a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), fixed location data unit, or a computer.
A method according to an embodiment includes a block 800 of providing a first unitary fixed magnetic layer, a block 802 of forming a first magnetic barrier layer on the first unitary fixed magnetic layer, a block 804 of forming a first free magnetic layer, comprising a plurality of free magnetic islands, on the first magnetic barrier layer, and a block 806 of providing a cap layer overlying the first free magnetic layer.
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor,
While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order, Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.