Multi-chip package reducing peak power-up current

Abstract

A multi-chip package is disclosed comprising a plurality of memory chips, each of the memory chips comprising an internal circuit; and a power level detector for detecting a level of a power supply voltage to initialize the internal circuit, at a power-up. The power level detectors in the respective memory chips are configured to initialize corresponding internal circuits at different points of time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. (FIG.) 1 is a block diagram showing a multi-chip package according to an embodiment of the present invention.

FIG. 2 is a table illustrating exemplary voltage levels for bonding option signals useful in the context of embodiment shown in FIG. 1.

FIG. 3 shows a voltage/current consumption profile in the context of initialization signal waveforms for a multi-chip package such as the one illustrated in FIG. 1.

Claims

1. A multi-chip package comprising: a plurality of memory chips, each of the memory chips comprising an internal circuit, and a power level detector adapted to detect a level of a power supply voltage initializing the internal circuit during a power-up operation,wherein each power level detector in the respective memory chips is differently configured to initialize a corresponding internal circuit at a different activation point during a power supply voltage ramp interval.

2. The multi-chip package of claim 1, wherein each power level detector in the respective memory chips is configured to initialize the corresponding internal circuit at a different activation point using at least one delay element.

3. The multi-chip package of claim 1, wherein each power level detector in the respective memory chips is configured to initialize the corresponding internal circuit at different initialization voltage level.

4. The multi-chip package of claim 1, wherein each of the memory chips further comprises a plurality of bonding pads.

5. The multi-chip package of claim 4, wherein each one of the bonding pads in the plurality of bonding pads is connected in a particular bonding option to a power pin or a ground pin.

6. The multi-chip package of claim 5, wherein each power level detector in the respective memory chips differently determines an activation point during the power supply voltage ramp interval in accordance with a particular bonding option.

7. The multi-chip package of claim 1, wherein the memory chips are a NAND flash memory chip.

8. A multi-chip package comprising: a plurality of memory chips, each of the memory chips comprising an internal circuit, and a power level detector adapted to detect a level of a power supply voltage initializing the internal circuit during a power-up operation;wherein each power level detector in the respective memory chips is differently configured to initialize a corresponding internal circuit at a different activation point during a power supply voltage ramp interval in response to a different combination of signals indicating a unique bonding option for the corresponding memory chip.

9. The multi-chip package of claim 8, wherein each unique bonding option corresponds to at least two bonding pads respectively connected to a ground pin or a power pin.