The present invention relates to high speed signaling.
A memory system typically includes a master device, such as a memory controller or graphics controller, and a plurality of integrated circuit memory devices for storing data. An integrated circuit memory device typically includes a plurality of storage cells for storing data, such as pixel information. The plurality of storage cells may be arranged in an array or memory bank. The integrated circuit memory device may include a plurality of memory banks.
Data is written to and read from the integrated circuit memory device in response to one or more commands included in read and/or write transactions between the integrated circuit memory device and the master device. For example, data is generally transferred from memory banks to sense amplifiers in response to an ACTIVATION (ACT) command on a control interconnect. The data may then be transferred from the sense amplifiers thru an integrated circuit memory device interface and onto a data interconnect in response to a READ (RD) command on the control interconnect.
Data stored in the plurality of storage cells is typically transferred to the sense amplifiers one row of storage cells at a time. A row of storage cells is typically referred to as “a page”. A column address is often provided to an integrated circuit memory device by the master device to access data within a selected page. A column address may be included in a request packet or with a command provided by the master device to the integrated circuit memory device.
Memory systems are utilized in different manners depending upon whether the memory system is used for a computational application, such as a general-purpose computer, or graphics application, such as a game console. For example in a graphics application, a large portion of memory requests by a graphics controller, have small transfer sizes of 16 to 32 bytes and little spatial or temporal locality. This is because even though the image itself is large, the polygon fragments that make up the image are small, getting smaller over time, and are stored with little relation to each other. Only a small portion of a page may need to be accessed in rendering a current image in a graphics application. In contrast, computational applications may have 256 byte cache line block transactions. In a computational application, a control interconnect or bus is often shared across multiple integrated circuit memory devices; where a control bus is often dedicated to each integrated circuit memory device in a graphics application. In computational applications, address mapping is typically random across multiple memory banks; while address mapping is generally limited to pages of an integrated circuit memory device in graphics applications. Transaction queues in the master device are reordered to minimize memory bank conflicts in both computational applications and graphics applications, but also reordered to maximize memory bank hits in a graphics application. In a computational application, there are generally a limited number of outstanding read transactions in the transaction queue, for example 10; while there may be hundreds of transactions in a graphics application.
Memory systems in a graphics application have accommodated the need for small transfer granularity by having more transfers (reducing a column cycle time interval tCC.) However, this will cause the cost of the integrated memory circuit device to increase, since the performance of the memory core that contains the interface to the sense amplifiers will likely have to increase as well. In any case, this is an inefficient solution because the size of each transfer remains the same; the unused portion of the data fetched remains the same.
A memory system includes a master device, such as a graphics controller or memory controller, and at least one integrated circuit memory device operable in a dual or multi-column addressing mode. The integrated circuit memory device includes, among other circuit components, an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a first column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a second column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
Memory banks 101 include individual memory banks having a two dimensional array of storage cells. In an embodiment, memory banks 101 include 16 memory banks. In an embodiment, a memory bank includes 2048 rows of storage cells or pages. Each row includes 64 addressable columns that each store 16 bytes of information (or 1024 bytes per page). In embodiments, storage cells of memory banks 101 may be dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, read-only memory (ROM) cells, or other equivalent types of memory storage cells. In an embodiment, integrated circuit memory device 100 is an XDR™ DRAM integrated circuit memory device provided by Rambus Inc. of Los Altos, Calif., USA.
Reading and writing to memory banks 101 are initiated by row decoder 122 and dual column decoder 123 in response to row and column addresses, respectively. A plurality of storage cells or referred to as row 112 (also referred to as a page) outputs a plurality of data (or set of data) to sense amplifiers 121 in response to a row address provided to row decoder 122 followed by a column address or column addresses provided to dual column decoder 123 on internal interconnect A. Memory device 100 includes an internal interconnect A for providing control and address signals for addressing a storage location in memory banks 101. Interconnect A is coupled to circuitry 105 for coupling interface 100b to core 100a. Pipeline register 102 is coupled to circuitry 105 and receiver 108. External interconnect RQ is coupled to receiver 108 and carries external control and address signals between interface 100b and master device 130. In an embodiment, interconnect RQ is a twelve signal line unidirectional control/address bus. Internal interconnect S, in an embodiment, is an internal bidirectional bus for providing read/write data signals between sense amplifiers 121 memory banks 101. Interconnect S is coupled to circuitry 106 and 107 for coupling interface 100b to core 100a. Pipeline registers 103 and 104 are coupled to circuitry 106 and 107, respectively. Transmitter 109 and receiver 110 are coupled to pipeline registers 103 and 104, respectively. An external interconnect DQ transfers external bidirectional read/write data signals and is coupled to transmitter 109 and receiver 110 as well as master device 130. In an embodiment, interconnect DQ is a sixteen signal line bidirectional data bus.
Dual column decoder 123 allows independent access to one or more addressable columns in a selected row 112 during a column cycle time interval tCC in response to one or more column addresses provided on internal interconnect A. In an embodiment, dual column decoder 123 is initialized to a single, dual, quad or multiple columns addressing mode decoder in response to a mode control signal 125. In an embodiment, mode control signal 125 is provided from an initialization register at memory system 140 initialization or power-up. In an alternate embodiment, mode control signal 125 is provided by master device 130 by way of interconnect RQ and internal interconnect A at initialization or during typical operation.
The pipeline registers 102, 103, and 104 are used for synchronization of the information between the internal and external interconnects. Registers 102-104 may also be used for generating delay, as would be required if the internal and external interconnects used a different number of signals. Although memory device 100 shows a single level (clock cycle) of pipeline registers, two or more levels (clock cycles) of delay are used in alternative embodiments.
In an embodiment, differential signals are transferred between memory device 100 and master device 130 on interconnect RQ, interconnect DQ and a CLOCK (CLK) line.
A CLK line provides a clock signal Clk to registers 102-104 for synchronizing integrated circuit memory device 100 transactions. In an embodiment, a clock signal Clk is provided to integrated circuit memory device 100 by master device 130. In alternate embodiments, a clock signal Clk is provided by another source, such as a clock generator. In other embodiments, a clock signal Clk serves as a reference for a clock recovery circuit component, which generates the actual clocking signal used with integrated circuit memory device 100.
In an embodiment, interface 100b includes a plurality of conducting contacts, such as pins and/or balls, for coupling to interconnect RQ, interconnect DQ and one or more CLK lines. In an embodiment, interface 100b includes twelve pins for coupling to interconnect RQ and sixteen pins for coupling to interconnect DQ. As one of ordinary skill in the art would appreciate, more or less contacts may be provided in alternate embodiments.
In embodiments, interconnects described herein include a plurality of conducting elements or conducting paths such as a plurality of wires and/or metal traces/signal lines. In an embodiment, a single conducting path illustrated in the Figures may be replaced by multiple conducting paths and multiple signal paths illustrated in the Figures may be replaced by a single conducting path. In embodiments, an interconnect may include a bus and/or point-to-point connection. In an embodiment, interconnects include control and data signal lines. In an alternate embodiment, interconnects include only data lines or only control lines. In still other embodiments, interconnects are unidirectional (signals that travel in one direction) or bidirectional (signals that travel in two directions).
In embodiments, master device 130 is a general-purpose processor, memory controller, network controller or graphics processor.
In an embodiment, integrated circuit memory device 100 is positioned on a substrate in a memory module having multiple integrated circuit memory devices. In an alternate embodiment, master device 130, memory device 100 and associated interconnects are in an integrated monolithic circuit.
As one of ordinary skill in the art would appreciate, other embodiments of an integrated circuit memory device 100 and master device 130, singly or in combination are available.
To reconstruct the image of triangle 202, multiple column addresses are provided to an integrated circuit memory device 100 for independently accessing portions of a row or page of storage cells during a column cycle time interval tCC. Since each portion of the triangle that is to be retrieved is relatively small, it is desirable that small transfer granularities, or small transfer sizes per column address, be used for these types of graphics applications for the extensive rendering of images comprising small triangles. In particular memory device 100 includes a dual or generally multi-column decoder 123 that decodes one or more column addresses for accessing a plurality of storage cells in a row of a memory bank or page.
While certain timing constraints are illustrated in
In a first or a computational mode of operation (accessing a page using a single column address), one ACT command, one RD command and a PRECHARGE (PRE) command are asserted on interconnect RQ by master device 130 to integrated circuit memory device 100. Dual column decoder accesses a single column in row 112 responsive to a single column address. In this mode of operation, a mode control signal 125 has been asserted to dual column decoder 123 so that dual column decoder 123, operating as a single column decoder, decodes a single column address per each column cycle time interval tCC. A single column address is included in a COL or COLM request packet that also include a RD or WR command and is transferred from master device 130 to integrated circuit memory device 100 in an embodiment. In an embodiment, a COLM request is a masked operation that is used with a WR command and not a RD command. In an alternate embodiment, either a COL or COLM request may be used with a RD command.
In a second or a graphics mode of operation (accessing a page using two column addresses), one ACT command, one RD command and a PRE command are also asserted on interconnect RQ by master device 130 to integrated circuit memory device 100. In an alternate embodiment, two RD commands are provided. Dual column decoder accesses a first and second column in row 112 responsive to two respective column addresses. In this mode of operation, a mode control signal 125 has been asserted to dual column decoder 123 so that dual column decoder 123 decodes two column addresses per each column cycle time interval tCC. Two column addresses may be included in either a COL or COLM request packet, illustrated in
In response to a request packet that includes two independent column addresses, in particular, column address values in fields CP[8:4] (first column address) and C[8:4] (second column address) in either COL request packet 401 and COLM request packet 402, 256 bits or 32 bytes are read onto interconnect DQ (or on sixteen signal lines of interconnect DQ) per column cycle time interval tCC. In other words, 512 bits or 64 bytes are read onto interconnect DQ per time interval tRR.
Request packet formats 400-404 are distinguished by an opcode field (OP[X]), which specifies the opcode of a desired command. Reserved fields are identified by “rsrv”.
ROWA request packet 400 has opcode fields OP[3:2] for an ACT command. A memory bank address field BA[3:0] and a row address field R[10:0] are also included for providing a bank address and a row address.
COL request packet 401 has opcode field OP[3:0] for a RD command and WR commands. A memory bank address field BC[3:0], a first column address field C[8:4] (for example, for accessing data in a column address of a page selected by the row address values in R[10:0]), a second column address field CP[8:4] (for example, for accessing data in a second column address of the page selected by the same row address values in R[10:0]) and a sub-opcode field (WRX) are specified for the RD and WR commands. In an embodiment, more than two column addresses may be included in a request packet for accessing more that two columns in a page during a column cycle time interval tCC.
COLM request packet 402 has opcode field OP3 for a MASKED WRITE (WRM) command. A memory bank address field BC[3:0], a first column address field C[8:4], a second column address field CP[8:4], similar to COL request packet 401, and mask fields M[7:0].
ROWP request packet 403 has opcode fields OP[3:0] for PRE and REFRESH (REF) commands. A memory bank address field BP[3:0] and sub-opcode field POP[2:0] are specified for the PRE command. Sub-opcode fields ROP[2:0] are specified for a REF command.
COLX request packet 404 includes other opcode fields OP[3:0] and sub-opcode fields XOP[3:0].
In alternate embodiments, three memory bank address bits or two memory bank address bits may be used for a column address with the use of a SEL bit.
In the embodiment illustrated by
Memory transactions, in particular memory commands, are input to control logic 905 from interconnect RQ. Control logic 905 includes receiver 108, pipeline register 102 and circuitry 105 as seen in
Memory banks 901 and 903, as wells as memory banks 902 and 904, have dedicated read and write pipes for reading and writing data from and to storage cells. This grouping allows for master device 130 to provide alternate commands to alternate groups of memory banks that enable full external interconnect or bus DQ utilization. Read data is output and interleaved between the different groups of memory banks in an embodiment.
In an embodiment, a first data interconnect DQ-A having sixteen data signal lines is coupled to memory banks 901 and 903 by read pipe 906 and write pipe 907. A second data interconnect DQ-B having sixteen data signal lines is coupled to memory banks 902 and 904 by read pipe 908 and write pipe 909. A control interconnect RQ is also coupled to an interface of integrated circuit memory device 900 to provide control signals to control logic 905.
Memory banks 901 and 903, as well as memory banks 902 and 904, are able to operate independently. In other words, no timing constraint is imposed when one group of memory banks may be accessed relative to the other group of memory banks. This independent nature of memory bank groups is derived from the fact that the memory groups are isolated from each other. The memory groups are sufficiently decoupled from each other from an electrical noise standpoint that access to one memory group does not corrupt data in another memory group. More specifically, the activation of one set of sense amplifiers associated with a memory group does not corrupt the other set of sense amplifiers associated with the other memory group, regardless of the timing of the ACT commands. In an embodiment, electrical isolation between memory groups is achieved by positioning an interface between memory groups.
Various aspects of the subject-matter described herein are set out non-exhaustively in the following numbered clauses:
1. An integrated circuit memory device, comprising: an interface;
2. The integrated circuit memory device of clause 1, wherein the first and second plurality of storage cells are accessible during a column cycle time interval.
3. The integrated circuit memory device of clause 1, wherein a first plurality of data is output from the first plurality of storage cells onto the interface during a first time interval and a second plurality of data is output onto the interface from the second plurality of storage cells during a second time interval.
4. The integrated circuit memory device of clause 1, wherein a first and second plurality of data is output from the first and second plurality of storage cells, respectively, onto the interface during a first time interval.
5. An integrated circuit memory device, comprising:
6. The integrated circuit memory device of clause 5, wherein the first and second plurality of data is provided at the interface during a first time interval, and the third and fourth plurality of data is provided at the interface during a second time interval.
7. The integrated circuit memory device of clause 6, wherein the interface is coupled to a first interconnect to transfer the first plurality of data and a second interconnect to transfer the second plurality of data.
8. An integrated circuit memory device, comprising:
9. The integrated circuit memory device of clause 8, wherein the first and second plurality of data is provided at the interface during a first time interval, and the third and fourth plurality of data is provided at the interface during a second time interval.
10. The integrated circuit memory device of clause 8, wherein the interface is coupled to a first interconnect to transfer the first and third plurality of data and a second interconnect to transfer the second and fourth plurality of data
11. A memory system comprising:
12. The memory system of clause 11, wherein the second and third column addresses are transferred in a request packet by the master device.
13. The memory system of clause 11, wherein the first and second plurality of storage cells are accessible during a column cycle time interval.
14. The memory system of clause 11, wherein the master device is a graphics controller.
15. The memory system of clause 11, wherein the master device is a memory controller.
16. The memory system of clause 11, wherein the master device provides a fourth and fifth column address, and the integrated circuit memory device is operable in a third mode of operation, wherein:
17. The memory system of clause 16, wherein the second and third column addresses are transferred in a first request packet and the fourth and fifth column addresses are transferred in a second request packet by the master device.
18. The system of clause 16, wherein the master device is coupled to the integrated circuit memory device by a first and second external interconnect, wherein a first plurality of data is output from the first row in a first memory bank onto the first interconnect during a first time interval and a second plurality of data is output onto the second interconnect from the second row in a second memory bank during the first time interval.
19. A method comprising:
20. The method of clause 19, wherein the first time interval is a column cycle time interval.
21. The method of clause 19, further comprising:
22. The method of clause 21, wherein the first and second column addresses are in a request packet.
23. A method comprising:
receiving a first column address to access a first plurality of storage cells in a first row of storage cells during a first time interval;
24. The method of clause 23, wherein the first and second time intervals are column cycle time intervals.
25. The method of clause 23, wherein the first row of storage cells is in a first memory bank and the second row of storage cells is in a second memory bank.
26. An integrated circuit memory device, comprising:
The foregoing description of the preferred embodiments of the present application has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to understand the invention for various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.
This application is a continuation of U.S. patent application Ser. No. 13/410254, filed Mar. 1, 2012, which is a continuation of U.S. patent application Ser. No. 13/239846, filed Sep. 22, 2011 (now U.S. Pat. No. 8,154,947), which is a divisional of U.S. patent applicant Ser. No. 13/019,785, filed Feb. 2, 2011 (now U.S. Pat. No. 8,050,134), which is a continuation of U.S. patent application Ser. No. 12/391,873, filed Feb. 24, 2009 (now U.S. Pat. No. 7,907,470), which is a continuation of U.S. patent application Ser. No. 11/853,708 (now U.S. Pat. No. 7,505,356), which is a continuation of U.S. patent application Ser. No. 10/955,193 (now U.S. Pat. No. 7,280,428), each entitled “Multi-Column Addressing Mode Memory System Including an Integrated Circuit Memory Device.” Each of these earlier applications and patents are hereby incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
4377855 | Lavi | Mar 1983 | A |
4542483 | Procyk | Sep 1985 | A |
4569036 | Fujii | Feb 1986 | A |
4633434 | Scheuneman | Dec 1986 | A |
4636982 | Takemae et al. | Jan 1987 | A |
4646268 | Kuno | Feb 1987 | A |
4654781 | Schwartz et al. | Mar 1987 | A |
4670745 | O'Malley et al. | Jun 1987 | A |
4698788 | Flannagan | Oct 1987 | A |
4700328 | Burghard | Oct 1987 | A |
4710902 | Pelley, III | Dec 1987 | A |
4740921 | Lewandowski | Apr 1988 | A |
4758993 | Takemae | Jul 1988 | A |
4766538 | Miyoshi | Aug 1988 | A |
4768157 | Chauvel et al. | Aug 1988 | A |
4787858 | Killian, Jr. | Nov 1988 | A |
4796230 | Young | Jan 1989 | A |
4800525 | Shah | Jan 1989 | A |
4811302 | Koishi | Mar 1989 | A |
4825413 | Tran | Apr 1989 | A |
4837465 | Rubinstein | Jun 1989 | A |
4837743 | Chiu | Jun 1989 | A |
4843264 | Galbraith | Jun 1989 | A |
4862421 | Tran | Aug 1989 | A |
4888732 | Inoue | Dec 1989 | A |
4903344 | Inoue | Feb 1990 | A |
4961168 | Tran | Oct 1990 | A |
4982370 | Matsumoto | Jan 1991 | A |
4984196 | Tran | Jan 1991 | A |
4985867 | Ishii et al. | Jan 1991 | A |
4991141 | Tran | Feb 1991 | A |
5046050 | Kertis | Sep 1991 | A |
5093806 | Tran | Mar 1992 | A |
5111434 | Cho | May 1992 | A |
5119340 | Slemmer | Jun 1992 | A |
5121358 | Slemmer | Jun 1992 | A |
5124610 | Conley | Jun 1992 | A |
5124951 | Slemmer | Jun 1992 | A |
5128897 | McClure | Jul 1992 | A |
5132931 | Koker | Jul 1992 | A |
5146592 | Pfeiffer et al. | Sep 1992 | A |
5150330 | Hag | Sep 1992 | A |
5181205 | Kertis | Jan 1993 | A |
5193072 | Frenkil | Mar 1993 | A |
5193074 | Anami | Mar 1993 | A |
5214610 | Houston | May 1993 | A |
5222047 | Matsuda et al. | Jun 1993 | A |
5241503 | Cheng | Aug 1993 | A |
5249165 | Toda | Sep 1993 | A |
5251178 | Childers | Oct 1993 | A |
5263002 | Suzuki | Nov 1993 | A |
5267215 | Tsujimoto | Nov 1993 | A |
5274596 | Watanabe | Dec 1993 | A |
5291444 | Scott | Mar 1994 | A |
5301162 | Shimizu | Apr 1994 | A |
5305280 | Hayano | Apr 1994 | A |
5321646 | Tomishima | Jun 1994 | A |
5337283 | Ishikawa | Aug 1994 | A |
5343438 | Choi | Aug 1994 | A |
5383159 | Kubota | Jan 1995 | A |
5390308 | Ware et al. | Feb 1995 | A |
5394528 | Kobayashi et al. | Feb 1995 | A |
5406526 | Sugibayashi | Apr 1995 | A |
5414662 | Foss | May 1995 | A |
5418737 | Tran | May 1995 | A |
5428389 | Ito | Jun 1995 | A |
5432743 | Kusakari | Jul 1995 | A |
5455802 | McClure | Oct 1995 | A |
5471425 | Yumitori | Nov 1995 | A |
5485430 | McClure | Jan 1996 | A |
5517456 | Chishiki | May 1996 | A |
5530814 | Wong et al. | Jun 1996 | A |
5546346 | Agata et al. | Aug 1996 | A |
5559970 | Sharma | Sep 1996 | A |
5587960 | Ferris | Dec 1996 | A |
5614855 | Lee et al. | Mar 1997 | A |
5652870 | Yamasaki et al. | Jul 1997 | A |
5655113 | Leung et al. | Aug 1997 | A |
5666322 | Conkle | Sep 1997 | A |
5675180 | Pedersen | Oct 1997 | A |
5689472 | Tanaka et al. | Nov 1997 | A |
5717871 | Hsieh et al. | Feb 1998 | A |
5717901 | Sung et al. | Feb 1998 | A |
5748561 | Hotta | May 1998 | A |
5751657 | Hotta | May 1998 | A |
5787267 | Leung et al. | Jul 1998 | A |
5793998 | Copeland et al. | Aug 1998 | A |
5801985 | Roohparvar et al. | Sep 1998 | A |
5852725 | Yen | Dec 1998 | A |
5864505 | Higuchi | Jan 1999 | A |
5875132 | Ozaki | Feb 1999 | A |
5881017 | Matsumoto et al. | Mar 1999 | A |
5892981 | Wiggers | Apr 1999 | A |
5893927 | Hovis | Apr 1999 | A |
5903509 | Ryan et al. | May 1999 | A |
5933387 | Worley | Aug 1999 | A |
5936885 | Morita | Aug 1999 | A |
5958033 | Schubert et al. | Sep 1999 | A |
5963488 | Inoue | Oct 1999 | A |
5996051 | Mergard | Nov 1999 | A |
6018478 | Higuchi | Jan 2000 | A |
6034878 | Osaka et al. | Mar 2000 | A |
6047347 | Hansen et al. | Apr 2000 | A |
6049855 | Jeddeloh | Apr 2000 | A |
6050983 | Moore et al. | Apr 2000 | A |
6075728 | Inoue | Jun 2000 | A |
6125157 | Donnelly et al. | Sep 2000 | A |
6138185 | Nelson et al. | Oct 2000 | A |
6141273 | Ku et al. | Oct 2000 | A |
6144220 | Young et al. | Nov 2000 | A |
6160750 | Shieh | Dec 2000 | A |
6163491 | Iwamoto et al. | Dec 2000 | A |
6185149 | Fujioka et al. | Feb 2001 | B1 |
6240039 | Lee et al. | May 2001 | B1 |
6240040 | Akaogi et al. | May 2001 | B1 |
6247084 | Apostol et al. | Jun 2001 | B1 |
RE37409 | Richardson et al. | Oct 2001 | E |
6311313 | Camporese et al. | Oct 2001 | B1 |
6356975 | Barth et al. | Mar 2002 | B1 |
6363454 | Lakhani et al. | Mar 2002 | B1 |
6366995 | Vilkov et al. | Apr 2002 | B1 |
6393543 | Vilkov et al. | May 2002 | B1 |
6396764 | Holland | May 2002 | B1 |
6434081 | Johnson et al. | Aug 2002 | B1 |
6446158 | Karabatsos | Sep 2002 | B1 |
6587917 | Simmons | Jul 2003 | B2 |
6625687 | Halbert et al. | Sep 2003 | B1 |
6680736 | Cho | Jan 2004 | B1 |
6687796 | Laine et al. | Feb 2004 | B1 |
6725316 | Gans | Apr 2004 | B1 |
6742098 | Halbert et al. | May 2004 | B1 |
6748556 | Storino et al. | Jun 2004 | B1 |
6754120 | Bellows et al. | Jun 2004 | B1 |
6813688 | Wu et al. | Nov 2004 | B2 |
6825841 | Hampel et al. | Nov 2004 | B2 |
6854042 | Karabatsos | Feb 2005 | B1 |
6877079 | Yoo et al. | Apr 2005 | B2 |
6885572 | Fujisawa | Apr 2005 | B2 |
6895474 | Ryan et al. | May 2005 | B2 |
6920540 | Hampel et al. | Jul 2005 | B2 |
7039782 | Garrett, Jr. et al. | May 2006 | B2 |
7187572 | Perego et al. | Mar 2007 | B2 |
7254075 | Woo et al. | Aug 2007 | B2 |
7266667 | Oh | Sep 2007 | B2 |
7280428 | Ware et al. | Oct 2007 | B2 |
7281079 | Bains et al. | Oct 2007 | B2 |
7363422 | Perego et al. | Apr 2008 | B2 |
7369444 | Perego et al. | May 2008 | B2 |
7505356 | Ware et al. | Mar 2009 | B2 |
7729151 | Tsern et al. | Jun 2010 | B2 |
7907470 | Ware et al. | Mar 2011 | B2 |
8028144 | Hampel et al. | Sep 2011 | B2 |
8050134 | Ware et al. | Nov 2011 | B2 |
20010037428 | Hsu | Nov 2001 | A1 |
20030009612 | Latta | Jan 2003 | A1 |
20030048616 | Ko et al. | Mar 2003 | A1 |
20030052885 | Hampel et al. | Mar 2003 | A1 |
20030174573 | Suzuki et al. | Sep 2003 | A1 |
20030197201 | Yanagawa | Oct 2003 | A1 |
20040019756 | Perego et al. | Jan 2004 | A1 |
20040037133 | Park et al. | Feb 2004 | A1 |
20040073772 | Hokenek et al. | Apr 2004 | A1 |
20040105292 | Matsui | Jun 2004 | A1 |
20040120197 | Kondo et al. | Jun 2004 | A1 |
20040120210 | Lee | Jun 2004 | A1 |
20040177210 | Choi | Sep 2004 | A1 |
20040221186 | Lee et al. | Nov 2004 | A1 |
20040225853 | Lee et al. | Nov 2004 | A1 |
20040256638 | Perego et al. | Dec 2004 | A1 |
20050083721 | Hampel et al. | Apr 2005 | A1 |
20050152210 | Park et al. | Jul 2005 | A1 |
20050182885 | Matsui et al. | Aug 2005 | A1 |
20060004976 | Rader | Jan 2006 | A1 |
20060039227 | Lai et al. | Feb 2006 | A1 |
20060047899 | Ilda et al. | Mar 2006 | A1 |
20060067146 | Woo et al. | Mar 2006 | A1 |
20060072366 | Ware et al. | Apr 2006 | A1 |
20070268765 | Woo et al. | Nov 2007 | A1 |
20080028135 | Rajan et al. | Jan 2008 | A1 |
20080062807 | Ware et al. | Mar 2008 | A1 |
20090157994 | Hampel et al. | Jun 2009 | A1 |
20100211748 | Perego et al. | Aug 2010 | A1 |
Number | Date | Country |
---|---|---|
10-2005-021894 | Jan 2006 | DE |
0339224 | Nov 1989 | EP |
0887737 | Dec 1998 | EP |
0887737 | Dec 1998 | EP |
0910091 | Apr 1999 | EP |
1248267 | Oct 2002 | EP |
2367400 | Apr 2002 | GB |
07-262767 | Oct 1995 | JP |
10-172283 | Jun 1998 | JP |
2000-082287 | Mar 2000 | JP |
2003-007052 | Jan 2003 | JP |
2003-223785 | Aug 2003 | JP |
2004-005856 | Jan 2004 | JP |
2004-139552 | May 2004 | JP |
WO-91-16680 | Oct 1991 | WO |
WO-2004-034401 | Apr 2004 | WO |
WO-2006-039106 | Apr 2006 | WO |
WO-2009-089301 | Jul 2009 | WO |
Entry |
---|
EP Extended European Search Report dated Mar. 28, 2012 re EP Application No. 11168736.4. 11 pages. |
EP Office Action dated Mar. 23, 2012 re EP Application No. 05852180.8. 5 pages. |
EP Response dated Feb. 3, 2011 to the Official Communication dated Jul. 30 2010 re EP Application No. 05852180.8. 33 pages. |
Fairchild Semiconductor, “Design Optimization Techniques for Double Data Rate SDRAM Modules,” Jul. 2000. 6 pages. |
First CN Office Action dated Jul. 27, 2009 in CN Application No. 200580045523.7. 5 pages. |
Fujisawa et al., “An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme,” Feb. 7, 2006, IEEE International Solid-State Circuits Conference, Session 8, DRAM and TCAM, 8.4. 10 pages. |
Fujitsu Limited, “Memory CMOS 8×256K×32 Bit Double Data Rate FCRAM, MB81N643289-50/-60,” pp. 1-56, Fujitsu Semiconductor Data Sheet, Advance Info., AEO.5E. 57 pages. |
Giacalone et al., “SP23.2: A 1MB, 100MHz Integrated L2 Cache Memory with 128b Interface and ECC Protection,” IEEE ISSCC, Feb. 1996, pp. 370-371/475. 3 pages. |
Hirose et al., “A 20-ns. 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture,” IEEE, Oct. 1990, pp. 1068-1072, vol. 25, No. 5. 8 pages. |
International Preliminary Report on Patentability (Chapter 1) dated Apr. 12, 2007, re International Application No. PCT/US2005/032770. 6 pages. |
Nitta et al., “SP23.5: A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block & Distributed Bank Architecture,” IEEE ISSCC Digest of Technical Papers, pp. 376-377, 477, Feb. 10, 1996. 3 pages. |
Nvidia Corporation, Technical Brief, “GeForce3: Lightspeed Memory Architecture,” pp. 1-9. 11 pages. |
Response to Office Action of May 5, 2009, dated Oct. 5, 2009, re U.S. Appl. No. 11/767,863, filed Jun. 25, 2007. 20 pages. |
Saeki et al., “SP 23.4: A 2.5 ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay,” IEEE ISSCC Digest of Technical Papers, pp. 374-375, 476, Feb. 10, 1996. 3 pages. |
Sakata et al., “Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAM's,” IEEE Journal of Solid State Circuits, vol. 29, No. 8, Aug. 1994, pp. 887-893. 9 pages. |
Samsung Electronics, “SDRAM Device Operations,” date unknown. 42 pages. |
Satoh et al., “A 209K-Transistor ECL Gate Array with RAM,” IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1275-1281. 7 pages. |
Standards Information Network, IEEE Press, “The Authoritative Dictionary of IEEE Standards Terms,” Copyright 2000, IEEE 100, Seventh Edition, p. 252. 2 pages. |
Sugibayashi et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE, Nov. 1993, pp. 1092-1098, vol. 28, No. 11. 8 pages. |
Sugibayashi et al., “WP3.5: A 30ns 256Mb DRAM with Multi-Divided Array Structure,” ISSCC Feb. 1993, pp. 50-51/262. 3 pages. |
JP Office Action dated Jun. 19, 2012 for JP Application No. 2009-510005. 3 pages. |
KR Response (Argument/Amendment) dated Jun. 18, 2012 in KR Application No. 10-2007-7014584. 123 pages. |
Malviya et al., “Module Threading Technique to Improve DRAM Power and Performance,” D&R Industry Articles, dated Mar. 11, 2011, Copyright 2009. 9 pages. |
Micron, “Designing for High-Density DDR2 Memory,” Technical Note, TN-47-16, Rev. B., Dec. 2009. 10 pages. |
Official Communication with Extended European Search Report for EP Application No. 09167223.8-1233, dated Oct. 6, 2009. 8 pages. |
Rambus Inc., “Micro-Threading,” dated Apr. 3, 2011, found online at rambus.com/in/.../microthreading.html. 4 pages. |
Response to the Official Communication dated Jan. 31, 2012 (Summons to Attend Oral Proceedings), dated Aug. 28, 2012 in EP Application No. 09167223.8. 55 pages. |
Schuette, Michael, “Rambus/Kingston Threaded DDR3 Modules,” dated Oct. 8, 2009, last updated Oct. 24, 2009. 8 pages. |
Ware et al., “Micro-threaded Row and Column Operations in a DRAM Core,” Rambus White Paper, Mar. 2005. 7 pages. |
Zheng et al., “Decoupled DIMM: Building High-Bandwidth Memory System Using Low-Speed DRAM Devices,” ISCA '09, dated Jun. 20-24, 2009. 12 pages. |
Communication Regarding the Expiry of the Time Limit Within Which Notice of Opposition May be Filed dated Sep. 15, 2010 in EP Application No. 05799571.4-2210. 1 page. |
Elpida Memory Inc., “User's Manual: New Features of DDR3 SDRAM,” Document E1503E10 (Ver.1.0), published Mar. 2009. 18 pages. |
EP Extended Search Report dated Dec. 30, 2011 re EP Application No. 11179126.5. 10 pages. |
EP Extended Search Report dated Dec. 30, 2011 re EP Application No. 11184623.4. 9 pages. |
EP Extended Search Report dated Jan. 2, 2012 re EP Application No. 11184627.5. 7 pages. |
EP Office Action dated Feb. 6, 2012 re EP Application No. 11179126.5. 2 pages. |
EP Office Communication dated Jan. 11, 2012 re EP Application No. 07782931.5. 7 pages. |
EP Office Communication dated Nov. 24, 2010 re EP Application No. 09167223.8. 6 pages. |
EP Response dated Apr. 15, 2010 to the Official Communication dated Oct. 5, 2009 re EP Application No. 07783931.5-1233. 25 pages. |
EP Response dated Apr. 4, 2011 to the Official Communication dated Nov. 24, 2010 re EP Application No. 09167223.8, Includes New Claims (Highlighted & Clear Copy) and Cross-Reference of New Claims. 41 pages. |
EP Response dated Aug. 29, 2012 to the Official Communication dated Mar. 27, 2012, Application No. 11168735.6. 21 pages. |
EP Response dated Jul. 20, 2012 to the Official Communication dated Jan. 11, 2012 in EP Application No. 07782931.5-1233, Includes New Claims (Clear and Highlighted Copies). 23 pages. |
EP Response dated Jul. 30, 2012 in response to the Official Communication dated Feb. 6, 2012 and to the Extended European Search Report dated Dec. 30, 2012, in EP Application No. 11 184 623.4, Includes New Claims (Clear and Highlighted Copies). 29 pages. |
EP Response dated Jul. 30, 2012 in Response to the Official Communication dated Feb. 6, 2012 and to the Extended European Search Report dated Dec. 30, 2012, in EP Application No. 11 184 627.5, Includes New Description pp. 2, 2a, and 22. 13 pages. |
EP Response dated Jul. 30, 2012 to the Official Communication dated Feb. 6, 2011 and the extended European Search Report dated Dec. 30, 2011, in EP Application No. 11 179 126.5, Includes New Claims (Clear and Highlighted Copies). 26 pages. |
EP Response dated Sep. 6, 2012 to the Official Communication dated May 2, 2012, Application No. 11168734.9. 22 pages. |
EP Response dated Sep. 6, 2012 to the Official Communication dated May 2, 2012, Application No. 11168736.4. 27 pages. |
EP Response dated Sep. 6, 2012 to the Official Communication dated Mar. 23, 2012, Application No. 05852180.8. 19 pages. |
EP Response to Official Communication dated Aug. 29, 2012, in EP Application No. 11168735.6, Includes New Claims (Clear and Highlighted Copies). 19 pages. |
EP Submission dated Feb. 3, 2012 in Response to the Official Communication dated Jan. 31, 2012 re EP Application No. 09167223.8. 4 pages. |
EP Submission dated Jul. 31, 2012 in EP Application No. 11179126.5. 1 page. |
EP Submission dated Jul. 31, 2012 in EP Application No. 11184627.5. 1 page. |
EP Summons to Attend Oral Proceedings dated Apr. 27, 2012 re EP Application No. 09167223.8. 1 page. |
EP Summons to Attend Oral Proceedings re EP Application No. 09167223.8 dated Jan. 31, 2012. 8 pages. |
First EP Examination Report with mail date of Oct. 5, 2009, re EP Application No. 07 782 931.5-1233. 5 pages. |
“The Authoritative Dictionary of IEEE Standards Terms”, Seventh Edition. (p. 252)., IEEE Press Copyright 2000. |
International Preliminary Report on Patentability (Chapter II) with mailing date of Apr. 9, 2010 re Int'l. Application No. PCT/US07/67814. 7 pages. |
International Search Report and the Written Opinion for International Application No. PCT/US2007/067814, dated Feb. 29, 2008. 18 pages. |
Invitation to Pay Additional Fees from the International Searching Authority in International Application PCT/US2007/067814, dated Dec. 17, 2007. 8 pages. |
JP Office Action dated Dec. 7, 2012 in JP Application No. 2007-543517, Includes English Translation. 19 pages. |
Aimoto et al., “SP23.3 A 7168GIPS 3.84GB/s 1W Parallel Image-Processing RAM Integrating a 16Mb DRAM and 128 Processors,” ISSCC, Feb. 1996, pp. 372-373/476. 3 pages. |
Application as filed on Apr. 17, 2007, U.S. Appl. No. 09/837,307 re RA203.P.US. 54 pages. |
Chang, Kun-Yung, “Design of a CMOS Asymmetric Serial Link,” A Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University, Aug. 1999. 133 pages. |
CN Board Opinion dated Dec. 1, 2011 re CN Application No. 200580045523.7. 8 pages. |
CN Office Action dated Dec. 22, 2010 re Rejection Decision for CN Application No. 200580045523.7. 14 pages. |
CN Office Action dated Mar. 24, 2010 re CN Application No. 200580045523.7, Includes Text of the Second Office Action and Translation. 14 pages. |
CN Response dated Jun. 3, 2010 re CN Patent Application No. 200580045523.7. 11 pages. |
EP Communication pursuant to Article 94(3) EPC, dated Jul. 30, 2010 in EP Application No. 05852108.8-2210. 6 pages. |
EP Extended European Search Report dated Mar. 27, 2012 re EP Application No. 11168734.9. 9 pages. |
EP Extended European Search Report dated Mar. 27, 2012 re EP Application No. 11168735.6. 9 pages. |
International Preliminary Report on Patentability (Chapter I) dated Jun. 7, 2007, re International Application No. PCT/US2005/042722. 10 pages. |
International Search Report and Written Opinion dated Jan. 26, 2006 in International Application No. PCT/US2005/032770. 9 pages. |
International Search Report and Written Opinion dated Jan. 4, 2006 in International Application No. PCT/US2005/028728. 5 pages. |
International Search Report and Written Opinion dated May 10, 2006 in International Application No. PCT/US2005/042722. 15 pages. |
International Search Report and Written Opinion in International Application No. PCT/US/2005/032770, dated Jan. 26, 2006. 12 pages. |
JEDEC, “Minutes of Meeting No. 71, JC-42.3 Committee on RAM Memories,” including Proposal to Add Number of Banks Option to the Mode Register for 64M SDRAM, Joint Electron Device Engineering Council (JEDEC), May 25, 1994, New York, pp. 1-14 plus Attachment T. 8 pages. |
JP Office Action dated Oct. 27, 2011 re JP Application No. 2007-543517. 18 pages. |
JP Response dated Apr. 26, 2012, re Argument and Amendment to the Office Action dated Oct. 27, 2011 in JP Application No. 2007-543517. 21 pages. |
Kirihata et al., “A 390-mm2, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline Architecture,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999, pp. 1580-1588. 10 pages. |
Koike et al., “SP23.1: A 60ns 1Mb Nonvolatile Ferroelectric Memory with Non-Driven Cell Plate Line Write/Read Scheme,” ISSCC, Feb. 10, 1996, pp. 368-379/475. 3 pages. |
Konishi et al., “Session XVIII: Static RAMs, FAM 18.6: A 64Kb CMOS RAM,” IEEE International Solid State Circuits Conference, Feb. 12, 1982, pp. 258-259. 3 pages. |
KR Office Action dated May 9, 2012 re KR Application No. 2007-7014584. 4 pages. |
Masumoto, Rodney T., “Configurable On-Chip RAM Incorporated Into High Speed Logic Array,” Proceedings of the IEEE 1985 Custom Integrated Circuits Conference, May 20-23, 1985, pp. 240-243. 6 pages. |
Micron Technology Inc., “Micron Synchronous DRAM 128Mb: ×32 SDRAM,” pp. 1-52, Rev. 9/00. 52 pages. |
Micron Technology, Inc., “256Mb: x32 GDDR3 DRAM, MT44H8M32—2 Meg×32×4 Banks,” GDDR3—1.fm—Rev A, Jun. 2003. 68 pages. |
Micron Technology, Inc., “DRAM Data Book,” Preliminary 1997. 71 pages. |
Micron Technology, Inc., “Synchronous DRAM,” Rev. Apr. 1996. 43 pages. |
Micron, “Graphics DDR3 DRAM,” Advance, “256 Mb×32 GDDR3 DRAM,” © 2003 Micron Technology, Inc., pp. 1-67. 67 pages. |
Minutes of Meeting No. 70, JC-42.3 Committee on RAM Memories, Mar. 9, 1994, Orlando, Florida. 41 pages. |
Nakamura et al., “FA14.2: A 29ns 64Mb DRAM with Hierarchical Array Architecture,” ISSCC, Feb. 1995, pp. 246-247/373. 3 pages. |
Takase et al., “A 1.6-Gbyte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999, pp. 1600-1606. 7 pages. |
Takase et al., “WP 24.1 A 1.6GB/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme,” ISSCC99/Session 24/Paper, Toshiba Corp., WP 24.1, Feb. 17, 1999. 2 pages. |
Takase et al., “WP 24.1: a 1.6GB/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme,” IEEE International Solid-State Circuits Conference, 1999. 8 pages. |
Ware et al., U.S. Appl. No. 12/391,873, filed Feb. 24, 2009, re Notice of Allowance and Fee(s) Due mailed Aug. 31, 2010. 10 pages. |
Ware et al., U.S. Appl. No. 12/391,873, filed Feb. 24, 2009, re Notice of Allowance and Fee(s) Due mailed Nov. 3, 2010. 11 pages. |
Ware et al., U.S. Appl. No. 13/019,785, filed Feb. 2, 2011, re Notice of Allowance and Fee(s) Due mailed Jun. 29, 2011. 14 pages. |
Ware, Frederick A., “Direct RDRAM 256/288-Mbit (512K×16/18×32s) Data Sheet,” Preliminary Information, Rambus Inc., Document DL0060 Version 0.90, 1999, pp. 1-66. 66 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Amendment mailed Jan. 11, 2011. 10 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Amendment/Response to Office Action submitted Aug. 4, 2011. 12 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Appeal Brief mailed Apr. 6, 2010. 28 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Corrected Response submitted Feb. 22, 2012 to the Office Action of Nov. 23, 2011. 17 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Final Office Action mailed Nov. 23, 2011. 33 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Notice of Appeal mailed Oct. 11, 2010. 1 page. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Office Action mailed Feb. 8, 2011. 3 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Office Action mailed Jul. 9, 2010. 17 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Office Action mailed Mar. 11, 2011. 37 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Office Action mailed Mar. 21, 2012. 36 pages. |
Ware, Frederick, U.S. Appl. No. 10/998,402, filed Nov. 29, 2004, re Response submitted Feb. 22, 2012 to the Office Action of Nov. 23, 2011, Includes Request for Continued Examination. 21 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Final Office Action mailed Mar. 1, 2010. 17 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Final Office Action mailed Nov. 25, 2011. 30 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Notice of Appeal from the Examiner to The Board of Patent Appeals and Interferences dated Jul. 30, 2010. 1 page. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Office Action mailed Apr. 7, 2010. 3 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Office Action mailed Mar. 10, 2011. 23 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Office Action mailed Mar. 22, 2012. 34 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Response to Notice of Appeal submitted Dec. 24, 2010. 18 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Response to Office Action mailed Mar. 10, 2011. 15 pages. |
Ware, Frederick, U.S. Appl. No. 11/767,863, filed Jun. 25, 2007, re Response After Final Office Action mailed Mar. 24, 2010. 15 pages. |
Ware, Frederick, U.S. Appl. No. 13/019,785, filed Feb. 2, 2011, re Response dated Mar. 12, 2011 to the Office Action dated Feb. 16, 2011, Includes Replacement Figures. 5 pages. |
Ware, Frederick, U.S. Appl. No. 13/239,846, filed Nov. 15, 2011, re Preliminary Amendment submitted Nov. 16, 2011, Includes Terminal Disclaimer(s). 19 pages. |
Ware, Frederick, U.S. Appl. No. 13/239,846, filed Sep. 22, 2011, re Corrected Notice of Allowability mailed Jan. 17, 2012. 5 pages. |
Ware, Frederick, U.S. Appl. No. 13/239,846, filed Sep. 22, 2011, re Notice of Allowance and Fee(s) Due mailed Dec. 6, 2011. 47 pages. |
Yamashita et al., “FA 15.2: A 3.84 GIPS Integrated Memory Array Processor LSI with 64 Processing Elements and 2-Mb SRAM,” IEEE International Solid-State Circuit Conference, pp. 260-261, Feb. 1994. 3 pages. |
Yoo et al., “17.7: A 1.8V 700Mb/s/pin 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration”, ISSCC, Feb. 2003, pp. 312-313, 495, 250-251, 535. 6 pages. |
Yoo et al., “A 150 MHZ 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods,” IEEE ISSCC, Digest of Technical Papers, pp. 250-251, 374, Feb. 17, 1995. 3 pages. |
Yoo et al., “SP23.6 A 32-Bank 1Gb DRAM with 1GB/s Bandwidth,” ISSCC, Feb. 1996, pp. 378-379/477. 3 pages. |
Yoon et al., “A 2.5V 333Mb/pin 1Gb Double Data Rate SDRAM,” ISSCC Digest of Technical Papers, Feb. 17, 1999. 11 pages. |
Zhao et al., “TA 11.6: An 18Mb, 12.3GB/s CMOS Pipeline-Burst Cache SRAM with 1.54Gb/pin,” IEEE International Solid-State Circuits Conference, 1999. 10 pages. |
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