MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING DATA TRANSMISSION MODE BETWEEN PORTS

Abstract

A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features will become readily apparent from the description that follows, with reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional multi processor system for use in a portable communication device;

FIG. 2 is a block diagram illustrating an example of a conventional multi processor system capable of using a memory according to an embodiment;

FIG. 3 is a block diagram illustrating an internal structure of a conventional memory cell array of a DRAM;

FIG. 4 is a block diagram illustrating memory array portions of a conventional multi processor system;

FIG. 5 is a block diagram of multi processor system having a multi path accessible DRAM according to an embodiment;

FIG. 6 is a block diagram illustrating a layout of memory regions and ports in a multi path accessible DRAM shown in FIG. 5;

FIG. 7 is a timing diagram for write and read operations of FIG. 6;

FIG. 8 is a block diagram illustrating in detail a data transmission controller of FIG. 6;

FIG. 9 is a circuit diagram of the data transmission controller shown in FIG. 8;

FIG. 10 is a circuit diagram schematically illustrating command generators employed in processors according to an embodiment;

FIGS. 11 to 13 illustrate timings of signals shown in FIG. 10; and

FIG. 14 illustrates in detail an address comparator used in processors according to an embodiment.

Claims

1. A semiconductor memory device, comprising: a plurality of ports;at least one shared memory region of a memory cell array accessible through the ports; anda data transmission controller coupled to the shared memory region and the ports, wherein the data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.

2. The semiconductor memory device of claim 1, wherein the data transmission controller is further configured to apply the read command after applying the write command without applying a precharge command and an active command.

3. The semiconductor memory device of claim 1, wherein the portion of the write address and the portion of the read address that are substantially equivalent each include a common row address.

4. The semiconductor memory device of claim 1, further comprising: an address comparator coupled to the ports and configured to compare the at least the portion of the write address and the at least the portion of the read address to generate a transfer signal;wherein the data transmission controller is further configured to apply the read command after the write command without applying the precharge command and the active command in response to the transfer signal.

5. The semiconductor memory device of claim 1, wherein the data transmission controller is further configured to apply the read command after the write command before applying any other commands when at least one command associated with the write operation is received before any commands associated with the read operation.

6. The semiconductor memory device of claim 5, wherein the data transmission controller is further configured to apply the read command after the write command before applying any other commands when at least one command associated with the read operation is received before a final command associated with the write operation is applied.

7. The semiconductor memory device of claim 1, wherein: a first access through a first port includes the write operation; anda second access through a second port includes the read operation.

8. The device of claim 1, wherein the data transmission controller comprises: a command decoder coupled to the ports and configured to combine signals received through the ports associated with the read operation and the write operation and configured to generate a port decoding signal; anda port permission signal generator coupled to the command decoder and configured to generate a port permission signal in response to the port decoding signal;wherein the data transmission controller is further configured to apply the read command after the write command before applying any other commands to the shared memory region in response to the port permission signal.

9. A system for a semiconductor memory device, comprising: a shared memory region of the semiconductor memory device accessible through a plurality of ports;a data transmission controller coupled to the shared memory region and configured to generate a transfer signal by comparing a first address associated with a first access to the shared memory region through a first one of the ports with a second address associated with a second access to the shared memory region through a second one of the ports;a first processor coupled to the data transmission controller, and including a first command generator configured to generate a first set of commands in response to the transfer signal; anda second processor coupled to the data transmission controller, and including a second command generator configured to generate a second set of commands in response to the transfer signal.

10. The system of claim 9, wherein if the transfer signal indicates that the first access and the second access are associated with the same address: the first command generator is further configured to generate the first set of commands including an active command and a write command without a following precharge command; andthe second command generator is further configured to generate the second set of commands including a read command and a precharge command without a preceding active command.

11. A method of operating a semiconductor memory device, comprising: receiving write operation commands through a first port;receiving read operation commands through a second port;applying a write command of the write operation commands to a portion of a shared memory region; andapplying a read command of the read operation commands to the portion of the shared memory region after applying the write command and before applying any other commands to the portion of the shared memory region.

12. The method of claim 11, wherein receiving the read operation commands further comprises receiving the read operation commands substantially during or after receiving the write operation commands.

13. The method of claim 11, further comprising: comparing a write address associated with the write operation commands and a read address associated with the read operation commands to generate a transfer signal;wherein applying the read command further comprises applying the read command in response to the transfer signal.

14. The method of claim 11, wherein the portion of the shared memory cell array further comprises a portion having a common row address.

15. The method of claim 11, further comprising: comparing a write address associated with the write operation commands and a read address associated with the read operation commands to generate a transfer signal;generating the write operation commands in response to the transfer signal; andgenerating the read operation commands in response to the transfer signal.

16. A method of operating a semiconductor memory device, comprising: receiving write operation commands associated with a write operation through a first port;receiving read operation commands associated with a read operation through a second port; andperforming the write operation and the read operation on a shared memory region of the semiconductor memory device using a subset of the write operation commands and the read operation commands.

17. The method of claim 16, wherein performing the write operation and the read operation on the shared memory region further comprises sequentially performing the write operation and the read operation on the shared memory region.

18. The method of claim 16, wherein performing the write operation and the read operation on the shared memory region using the subset of the write operation commands and the read operation commands further comprises: applying an active command of the write operation commands to the shared memory region;applying a write command of the write operation commands to the shared memory region;applying a read command of the read operation commands to the shared memory region; andapplying a precharge command of the read operation commands to the shared memory region.

19. The method of claim 18, wherein applying the read command occurs after applying the write command and before any other commands are applied to the shared memory region.

20. The method of claim 16, wherein at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.