Test Point Placement to Simplify Fault Detection; Hayes et al.; IEEE Transactions on Computers, vol. C-23, No. 7, pp. 727-735 (Jul., 1974). |
On Testability Analysis of Combinational Networks; Franc Brglez; ISCAS '84; pp. 221-225 (1984). |
Statistical Fault Analysis; Jain et al.; IEEE Design & Test; pp. 38-44 (Feb. 1985). |
Predict--Probabilistic Estimation of Digital Circuit Testability; Seth et al.; IEEE, pp. 220-225 (1985). |
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation; Waicukauski et al; 1985 International Test Conference; Paper No. 21.3; pp. 779-784 (1985). |
Protest: A Tool For Probabilistic Testability Analysis; Wunderlich; 22nd Design Automation Conference; Paper 14.3; pp. 204-211; (1985). |
Random Pattern Testability by Fast Fault Simulation Briers et al.; IEEE 1986 International Test Conference; paper 9.5 pp. 274-281 (1986). |
A Dynamic Programming Approach to the Test Point Insertion Problem; Krishnamurthy; 24th ACM/IEEE Design Automation Conference; Paper 36.3, pp. 695-705 (1987). |
Synthesis of Pseudo-Random Pattern Testable Designs; Iyengar et al.; 1989 International Test Conference; Paper No. 22.2, pp. 501-508 (1989). |
An Observability Enhancement Approach for Improved Testability and At-Speed Test; Rudnick et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 13, No. 8, pp. 1051-1056 (Aug. 1994). |
DFTGEN User's Guide, Digital Equipment Corp., Jul. 1995. |
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST; Kwang-Ting (Tim) Cheng et al.; International Test Conference; Paper 23.1: 506-514 (1995). |
Test Point Insertion for Scan-Based BIST, Bernhard H. Seiss, Pieter M. Trouborst, Michael H. Schulz, Published before Jul. 1, 1996. |