Patent Application
20140065881
Embodiments of the present invention relate generally to the technical field of data processing, and more particularly, to multi-socket connectors for coupling memory modules to printed circuit boards.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
As modern computer software increasingly requires more computing resources, there is a push to include more memory in computing platforms. As smaller and/or thinner computing platforms such as mobile phones and computing tablets become more prevalent, memory modules of relatively small physical size, such as small outline dual inline memory modules (“SODIMM”), are becoming more popular.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
As used herein, the terms “module” and/or “logic” may refer to, be part of, or include an Application Specific Integrated Circuit (“ASIC”), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
Multiple memory modules may be coupled to a printed circuit board (“PCB”) such as a motherboard of a computing platform in a variety of ways. In a two-memory-module-per-channel implementation, a memory module may be coupled on each side of the PCB, or both may be coupled to the same side of the PCB, e.g., in a “daisy chain” fashion. Disposing both memory modules on the same side of the PCB may enable easier access by a user than disposing the memory modules on opposite sides of the PCB.
In addition to the offset between first connector 102 and second connector 106, first connector 102 may be sized so that when first memory module 110 is inserted into first socket 104, first memory module is offset from PCB 114 by a distance Z. Second connector 106 may be sized so that when second memory module 112 is inserted into second socket 108, second memory module 112 is offset from PCB 114 by a distance Z1. As the distance Z increases, system 100 may become less suitable for use in thin computing platforms such as smart phones and tablet computers. Likewise, decreasing the distance Z may enable computing platforms that incorporate system 100 to be made thinner. However, mechanical limitations of memory modules and the configuration of first connector 102 and second connector 106 may limit how much the distance Z can be reduced. For example, the distance Z between first memory module 110 and PCB 114 may be approximately 9.2 mm. The distance Z1 between second memory module 112 and PCB 114 may be approximately 5.2 mm.
First socket 704 and second socket 708 may be oriented so that first memory module 710 may be inserted into first socket 704 from a first direction 718 and second memory module 712 may be inserted into second socket 708 from a second, opposite direction 720. This way, when first memory module 710 and second memory module 712 are inserted into first socket 704 and second socket 708, respectively, and the assembly is viewed from the side, it may resemble a “T.” Accordingly, it may be referred to as a “T-connector.” In various embodiments, once inserted into first socket 704 and second socket 708, respectively, first memory module 710 and second memory module 712 may be equidistant from PCB 714, e.g., by a distance Z1 in a direction that is orthogonal to the first and second directions. In various embodiments, the distance Z1 may be less than 5.8 mm, e.g., approximately 5.2 mm. In various embodiments, on insertion, first memory module 710 and second memory module 712 may be coplanar with each other. In other embodiments, the memory modules on insertion may not be precisely coplanar and/or may not be precisely equidistant from PCB 714, though in general the memory module with the higher distance Z may still be closer to PCB 714 than with the aforementioned prior art connectors. Due to the single multi-socket connector 702, the distance S may be reduced or eliminated altogether. For example, in various embodiments, on insertion, first memory module 710 and second memory module 712 may be separated from each other on a plane by less than 100 mils.
In addition to decreasing S and Z, the manner in which multi-socket connector 702 receives memory modules may permit more air flow on both sides of the memory modules than other configurations, such as the prior art stacked configurations shown in
In various embodiments, multi-socket connector 702 may facilitate improved power decoupling over other types of connectors when power supplied to memory modules changes abruptly. For instance, it may be possible to dispose a decoupling element such as a capacitor closer to memory modules inserted into sockets of multi-socket connector 702 than to memory modules inserted into other types of connectors. In various embodiments, the decoupling element may be embedded inside of multi-socket connector 702. This may simplify layout of components on PCB 714, and may provide a power delivery path for high frequency switching noise.
In various embodiments, multi-socket connector 702 may be configured to respectively relay, to first memory module 710 and second memory module 712, from PCB 714, first and second separate, dedicated control signals and/or dedicated clock signals. However, in various embodiments, other signals, such as data signals and/or command signals, may be shared. For example, in various embodiments, multi-socket connector 702 may be configured to provide first memory module 710 and second memory module 712 with a shared data pathway to and from PCB 714 and/or a shared command signal pathway from PCB 714.
Connectors described herein may be configured to receive various types of memory modules. For example, in the examples shown in the drawings, the connectors may be configured to removably receive small outline dual inline memory modules (“SODIMMs”). However, this is not meant to be limiting, and other embodiments of connectors described herein may removably receive any type of dynamic or static memory modules, such as other types of DIMMs, double data rate synchronous dynamic random access memory (“DDR SDRAM”) of any vintage (e.g., DDR3, DDR4, etc.), Zero-Capacitor RAM (“Z-RAM”), twin transistor RAM (“TTRAM”), and any past, present or future memory technologies. Additionally, in various embodiments, memory modules may include various other types of memory, such as non-volatile random access memory (“NVRAM,” e.g., flash memory), ferroelectric random-access memory (“FeTRAM”), nanowire-based NVM, phase change memory (“PCM”), and so forth.
In
In various embodiments, providing dedicated control and clock signals to each memory module may increase the number of overall pins. For instance, in embodiments where the connector is configured to receive two SODIMMs, dedicated control and clock signals may increase the total number of pins by 21, e.g., from 204 pins to 225 pins.
Multi-socket connectors (e.g., 702, 1002, 1102) may be used in various types of computing platforms, including but not limited to a laptop, a netbook, a notebook, an ultrabook, a smart phone, a computing tablet, a personal digital assistant (“PDA”), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit (e.g., a gaming console), a digital camera, a portable music player, a digital video recorder, an so forth. In various implementations, multi-socket connectors may be used in any other electronic device that processes data.
At block 1206, first and second separate, dedicated control signals may be relayed from the PCB (e.g., 714) to the first and second memory modules, respectively. At block 1208, first and second separate, dedicated clock signals may be relayed from the PCB (e.g., 714) to the first and second memory modules, respectively. At block 1210, data may be exchanged between the PCB (e.g., 714) and the first and second memory modules along a shared data pathway. At block 1212, commands may be provided from the PCB (e.g., 714) to the memory modules along a shared command signal pathway.
Embodiments of apparatus, methods, systems, devices, and connectors are described herein for a connector having a longitudinal body configured to mount the connector to a PCB. In various embodiments, a first and a second socket may be respectively disposed at a first side and a second side of the longitudinal body. In various embodiments, the first and second sockets may removably receive a first memory module from a first direction and a second memory module from a second direction opposite to the first direction. In various embodiments, the second side may be opposite to the first side. In various embodiments, on insertion into the first and second sockets, the first and second memory modules may be coplanar and/or equidistant from the PCB along a third direction orthogonal to the first and second directions.
In various embodiments, on insertion into the first and second sockets, each of the first and second memory modules may be less than 5.8 mm from the PCB. For instance, in various embodiments, after insertion into the first and second sockets, each of the first and second memory modules may be approximately 5.2 mm from the PCB.
In various embodiments, the body may be further configured to respectively relay to the first and second memory modules, from the PCB, first and second separate, dedicated control signals. In various embodiments, the body may be further configured to respectively relay to the first and second memory modules, from the PCB, first and second separate, dedicated clock signals.
In various embodiments, the body may be further configured to provide the first and second memory modules with a shared data pathway to and from the PCB. In various embodiments, the body may be further configured to provide the first and second memory modules with a shared command signal pathway from the PCB.
In various embodiments, the first and second sockets may be configured to removably receive first and second memory modules that are SODIMMs. In various embodiments, the body further may include a top end and a bottom end, the first and second sockets being disposed at the top end, and the top end may be wider than the bottom end. In various embodiments, the first and second sockets may be coplanar and separated from each other on a plane by less than 100 mils. In various embodiments, the first and second sockets may be offset from each other in a direction parallel to the longitudinal body.
Although certain embodiments have been illustrated and described herein for purposes of description, this application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims.
Where the disclosure recites “a” or “a first” element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.
