Claims
- 1. A method for increasing processor throughput, the processor having a multi-threaded pipeline comprising the steps of:
concurrently processing a plurality of contexts; and dynamically assigning the plurality of contexts to pipeline flows according to a context issue rule.
- 2. The method of claim 1 wherein the number of contexts is at least two.
- 3. The method of claim 2 wherein the number of contexts is 4.
- 4. The method of claim 1 wherein the context issue rule prevents a context which issues in a pipeline flow from issuing in a successive pipeline flow.
- 5. The method of claim 4 wherein the context issue rule prevents a context which issues in pipeline Flow N from issuing in pipeline Flow N+1.
- 6. The method of claim 5 wherein a result of an execution stage in the pipeline flow for the context is available at least one cycle before a successive pipeline flow for the context enters the execution stage.
- 7. The method of claim 1 where the context issue rule prevents a context which issues in pipeline Flow N from issuing in pipeline Flow N+P, where P depends upon a configuration of stages of the pipeline.
- 8. The method of claim 7 where P is dependent on a number of stages between at least two predetermined pipeline stages.
- 9. The method of claim 8 wherein the predetermined stages are an execution stage and a memory stage.
- 10. The method of claim 9 wherein P=2 plus the number of stages between the execution stage and a memory stage.
- 11. The method of claim 7 wherein P=3.
- 12. The method of claim 6 wherein data retrieved from a memory stage in a pipeline flow for the context is available prior to a successive pipeline flow for the context entering an execution stage.
- 13. The method of claim 1 wherein a result of a branch instruction is available for a successive instruction in a same context to select a next address without prediction.
- 14. The method of claim 13 wherein the result is available after a delay slot instruction.
- 15. The method of claim 1 wherein a jump destination resulting from a data dependent jump instruction is available for a successive instruction in the same context.
- 16. The method of claim 15 where the jump destination is available after a delay slot instruction.
- 17. The method of claim 1 wherein the multi-threaded pipeline is filled by two contexts issuing in alternate cycles.
- 18. The method of claim 1 wherein upon determining no context issued in pipeline Flows N+1 and N+3, and determining that a different context issued in pipeline Flow N+2, the context which issued in pipeline Flow N is prevented from issuing in pipeline Flow N+4.
- 19. The method of claim 1 wherein pipeline stalls due to delayed results are less frequent.
- 20. A processor comprising:
a multi-threaded pipeline which concurrently processes a plurality of contexts; and a scheduler which dynamically assigns the plurality of contexts to pipeline Flows according to a context issue rule.
- 21. The processor of claim 20 wherein the number of contexts is at least two.
- 22. The processor of claim 21 wherein the number of contexts is 4.
- 23. The processor of claim 20 wherein the context issue rule prevents a context which issues in a pipeline Flow from issuing in a successive pipeline Flow.
- 24. The processor of claim 23 wherein the context issue rule prevents a context which issues in pipeline Flow N from issuing in pipeline Flow N+1.
- 25. The processor of claim 24 wherein a result of an execution stage in a pipeline Flow for a context is available at least one cycle before a successive pipeline Flow for the context enters the execution stage.
- 26. The processor of claim 20 where the context issue rule prevents a context which issues in pipeline Flow N from issuing in pipeline Flow N+P, where P depends upon a configuration of stages of the pipeline.
- 27. The processor of claim 26 where P is dependent on a number of stages between at least two predetermined pipeline stages.
- 28. The processor of claim 27 wherein the predetermined stages are an execution stage and a memory stage.
- 29. The processor of claim 28 wherein P=2 plus the number of stages between the execution stage and a memory stage.
- 30. The processor of claim 26 wherein P=3.
- 31. The processor of claim 27 wherein data retrieved from a memory stage in a pipeline Flow for the context is available prior to a successive pipeline Flow for the context entering an execution stage.
- 32. The processor of claim 20 wherein a result of a branch instruction is available for a successive instruction in a same context to select a next address without prediction.
- 33. The processor of claim 32 wherein the result is available after a delay slot instruction.
- 34. The processor of claim 20 wherein a jump destination resulting from a data dependent jump instruction is available for a successive instruction in the same context.
- 35. The processor of claim 34 wherein the jump destination is available after a delay slot instruction.
- 36. The processor of claim 20 wherein the multi-threaded pipeline is filled by two contexts issuing in alternate cycles.
- 37. The processor of claim 20 wherein upon determining no context issued in pipeline Flows N+1 and N+3, and a different context issued in pipeline Flow N+2, the context which issued in pipeline Flow N is prevented from issuing in pipeline Flow N+4.
- 38. The processor of claim 20 wherein pipeline stalls due to delayed results are less frequent.
RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Application No. 60/404,346, filed Aug. 16, 2002. The entire teachings of the above application are incorporated herein by reference.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60404346 |
Aug 2002 |
US |