Patent Application
20110215395
The invention relates to a multi-transistor, e.g. two transistor memory cell and to a method for manufacturing a multi-transistor, e.g. two-transistor memory cell as well as to arrays of such cells in memory devices.
Two-transistor memory cells relate to non-volatile memory cells which comprise at least one access transistor and at least one memory transistor. Non-volatile memory cells are used in a wide variety of commercial and military electronic devices and equipment, such as RFID/NFC, smart cards, automotive applications, mobile phones, radios or digital cameras. The market for these electronic devices continually demands devices with a lower voltage, lower power consumption and decreased chip size.
The access transistor typically comprises diffusion implants, which can act as source or drain, an access channel region and an access gate. The access channel region is often arranged intermediate the diffusion regions of the access transistor. The memory transistor typically comprises diffusion implants, which can act as a source or a drain, a memory channel region, a memory gate stack and a memory gate. The memory channel region is often arranged intermediate the diffusion implants. The memory gate stack is typically located above the memory channel region and is arranged for storing electronic charge. Typically, the memory gate stack comprises a stack of layers comprising a first insulating layer, a charge storage layer and a second insulating layer, wherein the first insulating layer is arranged intermediate the memory channel region and the charge storage layer, and the second insulating layer is arranged intermediate the charge storage layer and the memory gate. Under control of a gate voltage of the memory transistor, i.e. the memory gate voltage, the memory gate stack can be programmed and erased.
In SONOS (Semiconductor Oxide-Nitride-Oxide Semiconductor) memory cell devices, the memory gate stack comprises at least a stack of a bottom silicon dioxide layer, a charge trapping silicon nitride layer and a top silicon dioxide layer, also known as an ONO stack. SONOS memory cell devices are used in view of scaling, as reduced program and erase voltages can be obtained. However, as such low power SONOS memory cells, operated by direct tunnelling, suffer from retention problems, high-K dielectrics in combination with metal gates are used to replace the silicon oxide layers. Such non-volatile memory cells, wherein the silicon oxide layers are replaced by HfSiOx are usually referred to as SHINOS memory transistors. However, while such SHINOS memory transistors have the desired properties in terms of program and erase characteristics, endurance and retention, such memory transistors with a high-K gate dielectric provided as HfSiOx suffer from inherent reliability problems.
Accordingly, it is the object of the invention to provide a multi-transistor, e.g. two-transistor memory cell and a method for manufacturing a multi-transistor, e.g. two-transistor memory cell that provides a good reliability as well as to arrays of such cells in memory devices.
An advantage of the present invention can be the provision of reduced program and erase voltages for a multi-transistor, e.g. two-transistor memory cell.
This object is addressed by a multi-transistor, e.g. two-transistor memory cell arranged on a semiconductor substrate comprising an access transistor and a memory transistor, the access transistor comprising an access channel region, a first implant and a second implant, a first diffusion implant and a second diffusion implant, and an access gate, wherein the access channel region is arranged intermediate the first implant and the second implant, the first implant and the second implant is arranged intermediate the first diffusion implant and the second diffusion implant, the access gate is arranged above the access channel region, the memory transistor comprises a memory channel region, a third implant and a fourth implant, a third diffusion implant and a fourth diffusion implant, a memory gate stack, and a memory gate, the memory channel region is arranged intermediate the third implant and the fourth implant, the third implant and the fourth implant is arranged intermediate the third diffusion implant and the fourth diffusion implant, the memory gate stack is arranged above the memory channel region, and the memory gate is arranged above the memory gate stack.
Accordingly, it is an essential idea of the invention to provide a multi-transistor, e.g. two-transistor memory cell that is characterized by a high reliability while preferably realized with a metal gate-SHINOS memory transistor while avoiding the use of an access transistor with a high-K dielectric. It is a further advantage that the multi-transistor, e.g. two-transistor memory cell according to the invention does not put any constrains on the memory cell size compared to an NMOS transistor as the access gate known from the prior art. It is preferred that the second diffusion implant is in common with the third diffusion region. It is further preferred that the width of the memory gate stack exceeds the width of the memory channel region and/or that the width of the access gate exceeds the width of the access channel region.
According to another preferred embodiment of the invention, the memory gate stack comprises a bottom dielectric layer, a charge trapping layer such as a nitride charge trapping layer, a top dielectric layer, a metal layer and a poly silicon layer, wherein the charge trapping layer, e.g. the nitride charge trapping layer is arranged above the bottom dielectric layer, the top dielectric layer is arranged above the charge trapping layer, e.g. the nitride charge trapping layer, the metal layer is arranged above the top dielectric layer, and the poly silicon layer is arranged above the metal layer. Preferably, the charge trapping layer is provided as Si3N4 and the poly silicon layer preferably comprises a thickness of 10-20 nm.
According to another preferred embodiment of the invention, the access transistor is an enhancement junction field effect transistor (JFET). It is further preferred that the junction field effect transistor is provided as a self-aligned JFET.
According to another preferred embodiment of the invention, the access channel region and/or the memory channel region are/is a shallow n-type conductivity implant. In other words, the access channel region and/or the memory channel region are/is preferably provided as a depletion layer, i.e. by phosphorus injection.
According to another preferred embodiment of the invention, the access gate and/or the memory gate are/is a p+-type conductivity epitaxial silicon layer or a p+-type conductivity poly silicon layer. In other words, the access gate of the JFET can be provided as a p+-doped epitaxial silicon layer or as a p+-doped poly silicon layer, however, the latter embodiment assumes that the leakage of the JFET access transistor with the p+-doped poly silicon gate can be tolerated.
According to another preferred embodiment of the invention, the semiconductor substrate comprises a flash p-well type conductivity silicon layer and an n-well type conductivity silicon layer, wherein the flash p-well type conductivity silicon layer is arranged above the n-well type conductivity silicon layer.
According to another preferred embodiment of the invention, the first implant and/or the second implant and/or the third implant and/or the fourth implant are/is a lowly or a moderately doped drain implant and/or the first diffusion implant and/or the second diffusion implant and/or the third diffusion implant and/or the fourth diffusion implant are/is a highly doped drain or source implant. In other words, such a lowly or moderately doped drain implant allows for creating a reduced doping gradient between a drain/source to be formed and the access channel region and/or the memory channel region, which lowers a maximum electric field in the access channel region and/or the memory channel region in the vicinity of the drain/source. Preferably, the lowly or moderately doped drain implant is provided as an impurity implantation with a dose of an order of 1013-1014 atoms per cm2. It is further preferred that the highly doped drain or source implant is provided with an impurity concentration with an order of 1015 atoms per cm2.
According to another preferred embodiment of the invention, the access gate and/or the memory gate stack and the memory gate have two opposite sides each extending substantially vertically with respect to the semiconductor substrate, wherein a spacer is associated with each opposite side of the access gate and/or the memory gate stack and the memory gate, respectively. The spacer can be provided for example as a nitride spacer. It is preferred that the width of the access gate and both spacers associated to each one side of the access gate equals the width of the first implant, the access channel region and the second implant. It is further preferred that the width of the memory gate and both spacers associated to each one side of the memory gate and the memory gate stack equals the width of the third implant, the memory channel region and the fourth implant.
The object of the invention is further addressed by a method for manufacturing a multi-transistor, e.g. two-transistor memory cell arranged on a semiconductor substrate, comprising the steps of opening an area of the semiconductor substrate in which an access transistor and a memory transistor are to be formed while leaving a silicon active area free, depositing a memory gate stack in the area in which the access transistor and the memory transistor are to be formed, applying a mask above the memory gate stack in the area in which the memory transistor is to be formed, removing part of the memory gate stack in the area in which the access transistor is to be formed and stripping the mask above the memory gate stack in the area in which the memory transistor is to be formed, growing a first silicon layer above the memory gate stack and growing a second silicon layer above the area in which the memory transistor is to be formed, applying a first mask above the first silicon layer and applying a second mask above the second silicon layer, removing a part of the first silicon layer outside of the first mask and removing a part of the second silicon layer outside of the second mask for forming an access gate, and stripping the first mask and the second mask, applying four implants into the silicon active area, wherein each one implant is positioned close to each one end of the memory gate stack and the access gate, respectively, and applying four diffusion implants in the silicon active area, wherein the each two implants positioned close to the memory gate stack and to the access gate, respectively, are arranged intermediate each of two diffusion implants.
Such a multi-transistor, e.g. two-transistor memory cell according to the invention is advantageous over the prior art as it provides an increase reliability, while not putting any constraints on the memory cell size compared to manufacturing methods with an NMOS transistor as the access transistor known from the prior art. It should be noted that the method for manufacturing a multi-transistor, e.g. two-transistor memory cell according to the invention utilizes techniques known for semiconductor manufacturing from the prior art, such as for example dry etching, hydrofluoric acid (HF)-clean or wet etching.
According to another preferred embodiment of the invention the memory gate stack comprises a bottom dielectric layer, a charge trapping layer, e.g. a nitride charge trapping layer, a top dielectric layer, a metal layer and a poly silicon layer, wherein the charge trapping layer, e.g. the nitride charge trapping layer is arranged above the bottom dielectric layer, the top dielectric layer is arranged above the charge trapping layer, e.g. the nitride charge trapping layer, the metal layer is arranged above the top dielectric layer, and the poly silicon layer is arranged above the metal layer. It is further preferred that the charge trapping layer comprises Si3N4. The poly silicon layer is preferably 10-20 nm thick.
According to another preferred embodiment of the invention, the access transistor is provided as an enhancement junction field effect transistor (JFET). It is further preferred that the JFET is provided as a self-aligned JFET. Accordingly, and advantageous over the prior art, the invention allows for a method for manufacturing a multi-transistor, e.g. two-transistor memory cell comprising a JFET as the access transistor without adding any additional masks and/or processing steps.
According to another preferred embodiment of the invention, the method for manufacturing a multi-transistor, e.g. two-transistor memory cell further comprises the step of creating a shallow n-type conductivity implantation in the silicon active area. Such a shallow n-type conductivity implantation is, in other words, carried out to create a depletion memory gate of the memory transistor, and preferably carried out during an initial flash-well implantation with a dedicated mask.
According to another preferred embodiment of the invention, the first silicon layer and/or the second silicon layer are/is a p+-type conductivity epitaxial silicon layer or a p+-type conductivity poly silicon layer. It is further preferred that the semiconductor substrate comprises a flash p-well type conductivity silicon layer and a n-well type conductivity silicon layer, wherein the flash p-well type conductivity silicon layer is arranged above the n-well type conductivity silicon layer. According to another preferred embodiment of the invention, the four implants are each a lowly or a moderately doped drain implant and/or the four diffusion implants are each a highly doped drain or source implant.
Memory cells as described above are preferably used in an array. Accordingly the present invention provides a memory array comprising at least one multi-transistor memory cell arranged on a semiconductor substrate comprising:
an access transistor and a memory transistor,
the access transistor comprising an access channel region, a first implant and a second implant, a first diffusion implant and a second diffusion implant, and an access gate, wherein
the access channel region is arranged intermediate the first implant and the second implant,
the first implant and the second implant is arranged intermediate the first diffusion implant and the second diffusion implant,
the access gate is arranged above the access channel region,
the memory transistor comprises a memory channel region, a third implant and a fourth implant, a third diffusion implant and a fourth diffusion implant, a memory gate stack, and a memory gate,
the memory channel region is arranged intermediate the third implant and the fourth implant,
the third implant and the fourth implant is arranged intermediate the third diffusion implant and the fourth diffusion implant,
the memory gate stack is arranged above the memory channel region, and
the memory gate is arranged above the memory gate stack.
The array of memory cells may be provided with row/column addressing devices which allow each memory cell to be read and written independently, i.e. each memory cell in the array is individually addressable.
Such a memory array can be a NAND, NOR, 2T, AND or virtual ground type or is a FLASH or E2PROM memory.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
In the drawings:
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part hereof, and within which are shown by way of illustration specific embodiments by which the invention may be practiced. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Those skilled in the art will recognize that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.
Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
In embodiments of the present invention, the term “substrate” 1 may include any underlying material or materials that may be used, or upon which a device, a circuit or an epitaxial layer may be formed. In other alternative embodiments, this “substrate” 1 may include a semiconductor substrate 1 such as e.g. doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphate (GaAsP), a germanium (Ge) or a silicon germanium (SiGe) substrate 1. The “substrate” 1 may include, for example, an insulating layer such as a SiO2 or a Si3N4 layer in addition to a semiconductor substrate 1 portion. Thus, the term “substrate” 1 also includes silicon-on-glass, silicon-on sapphire substrates 1. The term “substrate” 1 is thus used to define generally the elements for layers that underlie a layer or portions of interest. Also, the “substrate” 1 may be any other base on which a layer is formed, for example a glass or metal layer. The following processing steps are mainly described with reference to silicon processing but the skilled person will appreciate that the present invention may be implemented based on other semiconductor material systems and that the skilled person can select suitable materials as equivalence of the dielectric and conductive materials described below.
In the following a multi-transistor memory cell according to the present invention will be exemplified in detail as a two-transistor memory cell.
In a first manufacturing step for manufacturing a two-transistor memory cell according to a preferred embodiment of the invention, and as depicted in
As can be seen further from
As can be seen from
During the initial flash well implantation with a dedicated mask, shallow n-type implantations are carried out for creating the depletion memory channel region 23 of the memory transistor 6. The same implants are utilized for creating an access channel region 14, depicted in
Upon and hydrofluoric acid (HF)-clean of the silicon surface, and as depicted in
Hereafter, and as depicted in
The role of the access gate of the access transistor 5 provided as a JFET is played by the p+-doped epitaxial silicon layer 15 grown upon the mask 13 is applied. In this way, it is feasible to realize a JFET transistor in a self-aligned fashion and keep the memory cell size comparable to the standard MOS based memory cells. It is to be noted that the n-type channel implants providing the memory channel region 14 of the access transistor 5 provided as JFET are such, that this layer is fully depleted without any biased applied to the memory cell. In addition, the lowly or moderately doped drain implants 18 and/or highly doped drain and source implants 20 of the access transistor 5 provided as JFET can be optimized with respect to desired read current and a breakdown of drain to gate and source to gate junctions, respectively.
The multi-transistor memory cell according to any embodiment of the present invention may be implemented in memory array configurations. The array of memory cells may be provided with row/column addressing devices which allow each memory cell to be read and written independently, i.e. each memory cell in the array is individually addressable. The memory cells according to embodiments of the present invention may be used in devices such as NAND, NOR, AND, 2T and virtual ground type memory arrays as well as in FLASH and EPROM memories.
The multi-transistor memory cell according to embodiments of the present invention may find useful application in a variety of semiconductor electronic devices. In particular, a memory array according to embodiments of the present invention may find useful application in a variety of electronic devices such as PDA's, mobile telephones, memory sticks, smart phones, etc.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.
Other variations to be disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 08167453.3 | Oct 2008 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/IB2009/054675 | 10/22/2009 | WO | 00 | 4/19/2011 |
