Claims
- 1. A monolithic capacitor, comprising:a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes; wherein said first and second connection portions are distributed substantially uniformly over the entire area of said first and second internal electrodes.
- 2. A monolithic capacitor, comprising:a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes; wherein said first and second connection portions are distributed substantially in a line, only at the periphery of the first and second internal electrodes.
- 3. A microprocessor circuit, comprising:a microprocessor; and a monolithic capacitor, comprising: a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes; wherein the monolithic capacitor is connected as a decoupling capacitor for said microprocessor.
- 4. A high frequency circuit comprising:an active element comprising a plurality of terminals, a monolithic capacitor connected to at least one of said terminals comprising: a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes.
- 5. A high frequency circuit as claimed in claim 4, wherein said monolithic capacitor is further connected to ground.
- 6. A high frequency circuit as claimed in claim 4, wherein said monolithic capacitor is further connected to a second one of said terminals.
- 7. A high frequency circuit comprising:an active element comprising a plurality of terminals and a monolithic capacitor connected to at least one of said terminals comprising: a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes; wherein said monolithic capacitor is connected for bypassing high-frequency signals from said at least one terminal to ground.
- 8. A high frequency circuit as claimed in claim 7, wherein said monolithic capacitor is further connected to a second one of said terminals for bypassing high-frequency signals from said second terminal to ground.
- 9. A wiring substrate having a plurality of conductors, and a monolithic capacitor mounted on said wiring substrate and connected to at least one of said conductors, said monolithic capacitor comprising:a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes.
- 10. A wiring substrate comprising a plurality of conductors, and a monolithic capacitor mounted on said wiring substrate and connected to at least one of said conductors, said monolithic capacitor comprising:a capacitor body having first and second opposed, generally parallel, planar surfaces; m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one; n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1; p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1; n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes; p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes; said monolithic capacitor being mounted to said substrate and connected to said conductors by bump-connection between said conductors and said external terminal electrodes.
- 11. A microprocessor circuit as claimed in claim 3, wherein said monolithic capacitor is connected for bypassing high-frequency signals from said microprocessor to ground.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-313206 |
Nov 1997 |
JP |
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CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation-in-part of Ser. No. 09/040,891 filed Mar. 18, 1998 now U.S. Pat. No. 6,034,864, allowed, the disclosures of which are incorporated by reference.
US Referenced Citations (23)
Foreign Referenced Citations (6)
Number |
Date |
Country |
0 191 668 |
Aug 1986 |
EP |
60-158612 |
Aug 1985 |
JP |
5-205966 |
Aug 1993 |
JP |
6-260364 |
Sep 1994 |
JP |
7-326536 |
Dec 1995 |
JP |
11-204372 |
Jul 1999 |
JP |
Non-Patent Literature Citations (3)
Entry |
1991 Symposium on VLSI Technology, Digest of Technical Papers entitled Mutilayer Vertical Stacked Capacitors (MVDTC) for 64 Mbit and 256 Mbit DRAMs by D. Temmler, Institute of Semiconductor Physics, Germany. |
IBM Technical Disclosure Bulletin (vol. 31 No. 3 Aug. 1988). |
IBM Technical Dislcosure Bulletin (vol. 32 No. 6B Nov. 1989). |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09/040891 |
Mar 1998 |
US |
Child |
09/483403 |
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US |