This disclosure relates to coupling interfaces for silicon-on-insulator (SOI) devices.
Silicon-on-insulator (SOI) technologies are used for developing optical components, including photonic integrated circuits, which can be used in optical networking and other systems.
SOI devices require Input/Output (I/O) interfaces for allowing optical signals to enter and/or exit the SOI device. Current coupling methods include low-volume telecommunication device packaging, which does not provide a sufficiently low-cost, high-volume solution. Vertical grating couplers suffer from drawbacks of a diffractive nature. Their bandwidth is small and polarization-independent operation comes at a significant cost in transmission efficiency. In order to increase density, some grating couplers connect to the SOI device from a direction outside of the plane of the SOI device, adding complications to manufacture, space design and possible heat dissipation. Further, typical I/O edge interfaces require the precise alignment of a lensed fiber which abuts a waveguide within the SOI device. This requires high precision alignment systems as the alignment is critical due to the small spot size, which adds to the cost of such systems.
Ribbons having a single layer of waveguides have been proposed, for example in T. Barwicz, et al., Assembly of Mechanically Compliant Interfaces between Optical Fibers and Nanophotonic Chips, ECTC 2014; T. Barwicz, et al., Low-Cost Interfacing of Fibers to Nanophotonic Waveguides: Design for Fabrication and Assembly Tolerances, IEEE Photonis Journal, 2014; and Y. Taira, et al., Precision Assembly of Polymer Waveguide Components for Silicon Photonic Packaging, CPMT Symposium Japan (ICSJ), 2014 IEEE, all of which are hereby incorporated by reference in their entirety. Each of these coupling interfaces has different issues related to complexity of manufacturing, difficulty of alignment and the number of waveguides supported.
There is a need for improved I/O interfaces that allow optical signals to enter and/or exit SOI components. In particular, there is a need for such I/O interfaces to have good alignment tolerance, low loss, and low crosstalk while providing high volume.
An aspect of the disclosure provides a coupling interface for Silicon-on-Insulator (SOI) platforms. In some embodiments, evanescent field coupling (hereafter referred to as evanescent coupling) is utilized to decrease alignment requirements as compared to butting connections, while multiple layers of waveguides are used to achieve a high density optical Input/Output (I/O) interface.
A first aspect of the disclosure provides an optical coupling I/O interface which includes a plurality of layers of waveguides. The I/O interface further includes a coupling interface section, which is staggered to allow for coupling of the waveguides of each layer with a corresponding layer of waveguides in an optical device. Such an optical coupling I/O interface can form part of a Silicon Photonic processor, an SOI device or an optical coupler.
Another aspect of the disclosure provides an optical coupler which includes a plurality of layers of waveguides and a coupling interface section. The coupling interface section is staggered to allow for coupling of the plurality of layers of waveguides with a corresponding layer of waveguides in a photonic device.
Another aspect of the disclosure provides an optical device having a coupling section. A first layer of the coupling section includes a plurality of waveguides disposed within the first layer for evanescent coupling. A second layer of the coupling section includes a plurality of waveguides disposed within the second layer for optical coupling. A terminal edge of the second layer is staggered in alignment from a terminal edge of the first layer. The optical device can be a photonic device, such as Silicon Photonic processor or an SOI device, or an optical coupler.
Another aspect of the disclosure provides an SOI device. Such a device includes a plurality of layers of waveguides and a coupling interface section in which the plurality of layers of waveguides are staggered at an edge of the SOI device. This staggering allows for evanescent coupling of waveguides of each layer with a corresponding layer of waveguides in an optical coupler having a corresponding number of layers of waveguides. In some embodiments the coupling interface section is etched from an edge of SOI device. The staggering of layers in the coupling interface section provides a sufficient coupling length between the waveguides of the layers of the optical coupler and the corresponding waveguides of the SOI device to allow for evanescent coupling.
Another aspect of the disclosure provides an optical coupler which includes first and second layers, each of the layers having at least one waveguide. The coupler also includes a coupling interface section in which the first and second layers are staggered to allow for coupling of at least one waveguide in each of the first and second layers to corresponding waveguides in a photonic device. In some embodiments, at least one waveguide is positioned for evanescent coupling with a corresponding waveguide of the photonic device. In some embodiments, at least one waveguide is positioned for edge coupling with at least one waveguide in a corresponding layer of the photonic device. In some embodiments the waveguides with the layers are offset from each other. In some embodiments additional layers are included, and waveguides within may utilize evanescent coupling or another form of coupling. In some embodiments the
Another aspect of the disclosure provides a coupling interface having staggered first and second layers of waveguides to allow for coupling with corresponding layers of waveguides in a photonic device. At least one of the waveguides in the first layer of waveguides is arranged for evanescent coupling with the corresponding waveguides in the photonic device.
In embodiments of the above aspects, at least one of the plurality of layers has waveguides near a surface of the coupling interface section to allow for evanescent coupling with waveguides of a corresponding layer of the photonic device. The plurality of layers may be a part of a compliant ribbon which has the coupling interface section at at least one end. The waveguides may be arranged in layers and disposed within the ribbon to allow for evanescent coupling with the corresponding waveguides of the photonic device. One set of waveguides can be disposed within a layer to allow for evanescent coupling and waveguides in a different subset of the plurality of layers can be disposed to allow for a different coupling with the corresponding waveguides of the photonic device. The different coupling arrangements can include grating couplers and edge couplers. The ribbon can be further configured to connect to a concentrator located at the opposite end of the ribbon from the coupling interface section. The concentrator may include an interface to transform the pitch of the input media to the pitch of the waveguides of the ribbon. Located at a distal end of the ribbon may from the coupling interface may be a second coupling interface section, similar to the above described coupling interface section for coupling to a second photonic device.
The photonic device can be a Silicon-on-Insulator (SOI) device. Each of the plurality of layers in the coupling interface section can be separated by a gap corresponding to a gap between layers in the SOI device. The waveguides in a single layer may be laterally offset from the waveguides of another layer by a sufficient distance to allow for a reduction in crosstalk between waveguides of adjacent layers. The waveguides of one layer can be laterally offset from the waveguides of another layer by a distance corresponding to lateral offsets between waveguides in the SOI device. The edges of layers in the coupling section can be staggered to provide a sufficient coupling length between the waveguides of the layers of the ribbon and the corresponding wavelengths of the SOI device to allow for evanescent coupling. The ribbon can be composed of a polymer based material or a silicon based material. The coupling section of both the ribbon and the SOI device may have self-alignment assemblies to allow for mating of the ribbon to the SOI device. The self-alignment assembly may be a set of ribs to be inserted into a corresponding set of grooves.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings which description is by way of example only.
For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.
As can be seen in the embodiment of
The ribbon 100 has a coupling interface section 140 in which the edges of the ribbon are staggered to allow the waveguides of the multilayer ribbon to correspondingly overlap the silicon or silicon nitride waveguides of the SiP Die 200 when attached. The edges are said to be staggered as their terminal ends are offset from each other, with edge 132 extending beyond edge 122 by coupling length CL3. Edge 122 further extends beyond edge 112 by coupling length CL2. The waveguides in the ribbon 100 are aligned to overlap with the waveguides in die 200 to allow for evanescent field coupling, which realizes good alignment tolerance and low-loss coupling between waveguides of the ribbon and those of the photonic device (i.e. the SiP Die). Coupling length CL1 is the length in which the waveguides in layer 111 of the ribbon overlap the corresponding waveguides in layer 211 of the SiP Die 200. The coupling lengths (CL1, CL2, CL3) used allow for sufficient coupling efficiency for the desired application. The coupling lengths depend on the waveguide material, dimensions, light wavelength and gap.
It should be noted that although illustrated as being separated into layers, ribbon 100 may be monolithic in construction so that no layers are discernible. In a monolithic construction, ribbon 100 may have all lightpaths in a single layer, or there could be a variety of stacking arrangements. The lightpaths (also referred to as waveguides) then separate in advance of the edge of the coupling region so that each of the waveguides is in the correct position for coupling into the die 200.
Further, in some embodiments the entire SiP Die need not be staggered at the left edge 240 as shown. Rather, the SiP Die may be continuous at the edge, in which case etchings are made to accommodate the staggered edges of the ribbon to allow for the waveguide overlapping.
The layers of the ribbon 100 are separated by gaps (G1, G2) corresponding to gaps (G1, G2) between layers in the SOI device 200. The waveguides of one layer are laterally offset from waveguides of another layer by inter-layer waveguide offsets (L1, L2). The waveguides of one layer of the ribbon 100 are laterally offset from waveguides of another layer of the ribbon 100 to align with corresponding lateral offsets between waveguides of layers in the SOI device 200. The gaps (G1, G2) and inter-layer waveguide offsets (L1, L2) between the different waveguide layers can be selected to reduce crosstalk of channels and insertion loss. The size (i.e. width and thickness) of the ribbon waveguides can be a function of the size of the waveguides on the chip to achieve minimum insertion loss.
It is noted that the Pitch and MFD concentrator 10 illustrated in
In some embodiments, the ribbon or the SiP Die are fabricated (deposited) layer by layer. For example, a bottom layer is fabricated first, and then the upper layers are sequentially deposited overtop. Accordingly, in some embodiments the ribbon and the photonics device can be considered to include layers. Possible ways to form multilayer waveguide ribbons have been discussed in S. Garner et al, Three-Dimensional Integrated Optics Using Polymers, IEEE Journal of Quantum Electronics, Vol. 35, No. 8, August 1999; J Ryu et. al., Simple Fabrication of Double-layer Multi-channel Optical Waveguide Using Passive Alignment, Vol 19, No. 2, Optics Express 1183, January 2011; T. Korhonen et. al., Multilayer Single-mode Polymeric Waveguides by Imprint Patterning for Optical Interconnects, SPIE Proceedings Vol. 8991, Optical Interconnects XIV, March 2014; and K. Chen et al., Realization of Polymer-Based Polarization-Insensitive Interleaver Using Multilayer Waveguide Structure, IEEE Photonics Technology Letters, Vol. 23, No. 16, Aug. 15, 2011, all of which are hereby incorporated by reference in their entirety.
Accordingly, embodiments provide a multilayer ribbon interface which acts as a high density optical I/O for an SOI device that includes integrated multilayer silicon and silicon nitride waveguides. Such a multilayer waveguide ribbon can include multiple layers of silicon/silicon nitride waveguides as the optical I/O for silicon dies. The multilayer waveguide ribbon can comprise polymer or silicon based material. The multilayer ribbon can include a vertical and horizontal waveguide layout to minimize loss and crosstalk. Further, such a multilayer ribbon can provide a tolerant and compliant interface due to the evanescent coupling between waveguides, with a passive self-alignment assembly for coupling with SOI devices.
Throughout the above description, the terms optical and photonic have been used in a manner that will be understood by those skilled in the art to be generally interchangeable. A SiP Die, is typically referred to as a photonic device, while a ribbon is referred to as an optical device. These terms can be interchanged without introducing error, and the consistent use in this manner should not be considered to be limiting.
Although the present invention has been described with reference to specific features and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the invention. The specification and drawings are, accordingly, to be regarded simply as an illustration of the invention as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present invention.
This application claims the benefit of priority to U.S. patent application Ser. No. 62/168,273 entitled “MULTILAYER EVANESCENT COUPLING INTERFACE” filed May 29, 2015, which is hereby incorporated by reference in its entirety.
Number | Date | Country | |
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62168273 | May 2015 | US |