Patent Application
20130235630
High voltage power supplies are needed for many types of electronic devices. A low voltage may be converted to the appropriate high voltage by a transformer and associated signal conditioning components to obtain the desired voltage and current level. Often multiple electronic components and systems are powered by a single power supply. However, some types of loads may need individual current control. Typical power supplies provide global voltage or current control, but not individual voltage or current control for each of a number of outputs. A common solution is to provide a separate regulated power supply for each load or a subset of loads but not the entire set of loads, increasing the size and cost by including a transformer and filtering and control circuitry for each load or subset of loads.
An exemplary power supply includes a power source having at least one power source output, and a plurality of drivers connected to the at least one power source output. At least one of the plurality of drivers includes a bridge network having a first switch, a second switch and a bridge network output. The first switch is connected between the at least one power source output and the bridge network output. The second switch is connected between the bridge network output and a ground. The bridge network further includes at least one control input connected to the second switch. The bridge network is adapted to change a state of the first switch based on a state of the second switch.
An exemplary operation for driving current to an output includes generating an envelope waveform, increasing a voltage of the envelope waveform to generate a high voltage envelope, and switching a control input to either drive the high voltage envelope through a bridge network to the output or turnoff the output. The control input is operated by a lower voltage than the high voltage envelope.
Illustrative embodiments are shown in the accompanying drawings as described below.
The drawings and description, in general, disclose a method and apparatus for providing multiple drivers with a single transformer or other power source in a high voltage power supply. The multiple drivers are individually controllable by low voltage analog and/or digital control signals. Referring now to
The drivers may each comprise a half-bridge or full-bridge network, as illustrated in
Referring now to
Although the exemplary driver 29 with a full-bridge network is more complex than the driver 22 with a half-bridge network, it can be advantageous for certain types of loads.
The method and apparatus for supplying power may be envelope-driven with any desired waveform to meet the requirements of the load. For example, the high voltage power supply may generate any desired output such as a sine wave or variation thereof, a square wave, triangle wave, sawtooth, etc. The waveform of the current through the load tracks the waveform from the power supply, making the circuit envelope-driven. The method and apparatus for supplying power may alternatively be operated in a typical digital switching mode rather than being envelope-driven by using a direct current (DC) high voltage power supply if desired. Referring now to
Additional examples of envelope waveforms are illustrated in
Note that the method and apparatus for supplying power is not limited to use with any particular envelope or combination of multiple envelopes, and may be adapted as needed to create the desired envelope across the load. The envelope may also ramp gradually up and down if desired. For example, the DC-biased sine wave of
Referring now to
In one exemplary embodiment using discrete components, the transistors 88 and 92 may each comprise suitable discrete 1000 volt NMOS transistors, available from a number of vendors. The Zener diode 90 may comprise any suitable Zener with a reverse breakdown voltage (voltage rating) larger than the threshold of the NMOS transistor. Any suitable range Zener diode may be used. The high-side resistor 100, depending on the application and use, may comprise a high value resistor such as a 1 Megohm or 10 Megohm watt resistor. The low-side resistor 94 may comprise a low value resistor, again depending on the application, such as a 10 ohm to few hundred ohm resistor. These values are to be understood to be possible values for certain applications; higher and lower values may be used as dictated and required for a particular application including both low and high voltage, low and high power applications.
In another exemplary embodiment, the driver 80 may be fabricated as an integrated circuit. In order for the transistors to handle the high voltages in this and other exemplary embodiments, whether using discrete components or as part of an integrated circuit, the transistors may be stacked to divide the voltage across multiple transistors, as will be discussed with reference to other exemplary embodiments below. One suitable method of stacking transistors to divide the high voltages is described in a U.S. patent application entitled “Processes and Packaging for High Voltage Integrated Circuits, Electronic Devices, and Circuits” of Laurence P. Sadwick et al., filed Sep. 29, 2006, which is incorporated herein by reference for all that it discloses.
During operation, the driver 80 sources current to the load 104 when the low-side transistor 92 is turned off by the control input 102. During this phase of operation, no current flows through the low-side transistor 92. The high-side transistor 88 is turned on by the gate resistor network to a Vgs voltage value greater than the threshold voltage of the transistor and is limited and supported by the Zener diode 90, allowing current to flow from the power source 82, through the high-side transistor 88 and through the load 104. The current through the relatively high impedance load 104 is limited primarily by the resistance of the load 104 and the voltage and current sourcing capacity of the power source 82. If a low impedance load is being driven, an appropriate means of current limitation may be added as desired.
During the second phase of operation, the low-side transistor 92 is turned on by the control input 102. As current flows through the Zener diode 90 and the low-side transistor 92, the Zener diode 90 is forward biased and Vgs of the high-side transistor 88 is about −0.7 volts, turning off the high-side transistor 88 for an enhancement transistor for the particular embodiment shown in the figure. It should be understood that appropriate modifications can be made to the particular embodiment presented for this invention to use, for example, n channel depletion MOSFETs and p channel depletion and/or enhancement MOSFETs. These MOSFETs can be made from any suitable semiconductor based materials system including but not limited to silicon, silicon on insulator (SOI), silicon carbide, III-V semiconductors, etc. In this particular embodiment, a small current flows from the power source 82, through the high-side resistor 100, the low-side transistor 92 and the low-side resistor 94. The current through the driver 80 during this phase of operation is limited primarily by the resistance of the high-side resistor 100, keeping the Zener diode 90 forward biased so that the high-side transistor 88 remains off. During this phase of operation, no significant current flows through the load 104.
Current may be directed continuously through the load 104 by keeping the low-side transistor 92 turned off by the control input 102 and thus turning on the high side transistor in the present embodiment. Alternatively, the duty cycle of the current through the load 104 may be varied by alternately turning the low-side transistor 92 on and off with the control input 102, turning current through the load 104 off and on. In one exemplary embodiment, a pulse width or pulse code modulated signal is applied to the control input 102 to vary the duty cycle through the load 104. For example, if the power source 82 is providing a sine wave at 50 kHz and a pulse width modulated (PWM) signal of typically a few Hz to around 1 kHz is applied to the control input 102, 50 sine waves will cycle on the input power source 82 during each period of the PWM signal. To fully drive the load 104, the duty cycle of the PWM signal is set to 0% so that the low-side transistor 92 is always turned off, allowing the current to flow through the load 104 rather than being pulled down to ground 96. To turn off the current through the load 104, the duty cycle of the PWM signal is set to 100% to always turn on the low-side transistor 92. (Note that the power source 82 could also be turned off, but assuming that the same power source 82 is supplying other drivers and loads, that would turn off the current to all loads. In contrast, the control input 102 may be used to independently control just one driver.) Generally speaking, to set the duty cycle through the load 104 to 90% of peak, the width of the pulse is set to 10% of the PWM period so that the pulse turns on the low-side transistor 92 during 5 of each 50 sine waves from the power source 82.
Note that the frequencies of the current from the power source 82 and the signal applied to the control input 102 may be set to any desired frequency. Similarly, the PWM control signals may have any desired period and frequency. For example, the frequency may be set at about 100 Hz to be just above the 50 or 60 Hz frequencies of many power grids.
The low-side resistor 94 is included to monitor current through the load 104 for certain applications and uses. Alternatively a resistor of suitable value for the particular application may be attached to the load (typically on the low side of the load) to monitor the current through individual loads, a subset of the loads, or the total load.
Referring now to
On the right side 172 of the driver 140, a high-side transistor 174 is connected drain first to the power source 142, followed in series by a Zener diode 176 (anode first), a low-side transistor 178 (drain first), and a low-side resistor 180, before connecting to ground 162. A high-side resistor 184 is connected at one end to the power source 142 and at the other end to the gate of the high-side transistor 174 and to the node between the Zener diode 176 and the low-side transistor 178. A control input 186 is connected to the gate of the low-side transistor 178, and the load 168 is connected at another end to the output node 188 between the high-side transistor 174 and the Zener diode 176. The load 168 is thus connected between the output nodes 170 and 188 of the two sides 152 and 172 of the full-bridge driver 140. In this exemplary embodiment, the transistors 154, 158, 174 and 178 comprise NMOS transistors. Again, it is understood that PMOS or CMOS transistors could be used in these novel inventive circuits. The circuit may be modified as desired to utilize other types of transistors or switches. As with other embodiments described herein, the method and apparatus for supplying power may be fabricated using discrete parts, as an integrated circuit, or a combination thereof.
The driver 140 operates in two phases to drive current through the load 168 alternately from either direction. In the first phase, the left high-side portion 144 of the driver 140 sources current to the load 168 and the right low-side portion 150 sinks current from the load 168 to ground 162. In the second phase, the right high-side portion 148 of the driver 140 sources current to the load 168 and the left low-side portion 146 sinks current from the load 168 to ground 162. To enter the first phase, the left control input 166 turns off the left low-side transistor 158 and the right control input 186 turns on the right low-side transistor 178. On the left side 152, when the low-side transistor 158 is turned off, the high-side transistor 154 is turned on as described above with respect to
During the second phase, the right control input 186 turns off the right low-side transistor 178, thereby turning on the right high-side transistor 174. The left control input 166 turns on the left low-side transistor 158, turning off the left high-side transistor 154. Current flows from the power source 142, through the right high-side transistor 174, the load 168, the left Zener diode 156, the left low-side transistor 158 and the left low-side resistor 160 to ground 162.
To provide a 1000 volt full-bridge driver, the same exemplary parts used in the circuit of
As with the exemplary half-bridge driver 80 of
Current through the load 168 may be monitored by the low-side resistors 160 and 180. Current monitors (not shown) may be connected to current monitor nodes 190 and 192 to measure the voltage across the low-side resistors 160 and 180. Current monitors may comprise any device or technique to measure voltage across the low-side resistors 160 and 180, whether now known or developed in the future. The current may also be monitored at other locations in the driver 80, such as the high-side of the driver or in series with the load. Current may alternatively be monitored using external monitors, such as, for example, inductively coupled coils.
Referring now to
A high-side resistor 218 is connected at one end to the power source 202 and at the other end to the gate of the bottom high-side transistor 206 and to the node between the Zener diode 208 and the top low-side transistor 210. A load 220 is connected at one end to the output node 222 between the bottom high-side transistor 206 and the Zener diode 208 and at the other end to ground 216. A voltage divider chain made up of four resistors 224, 226, 228, and 230 balances the voltages applied to the gates of the transistors 204, 206, 210 and 212. In one exemplary embodiment, the resistors 224-230 of the voltage divider chain are of equal resistance. A high resistance, such as 10 Megohms, will limit the current through the voltage divider chain. Alternatively, various resistances may be selected to match the breakdown voltages of the transistors, applying the desired voltage levels to the gates of the transistors.
The first resistor 224 is connected between the power source 202 and the gate of the top high-side transistor 204. The second resistor 226 is connected between the gate of the top high-side transistor 204 and the output node 222. The third resistor 228 is connected between the output node 222 and the gate of the top low-side transistor 210. The fourth resistor 230 is connected between the gate of the top low-side transistor 210 and ground 216.
During one phase of operation, the bottom low-side transistor 212 is turned off so that current flows through the load 220 and the output node 222 is at about the same voltage level as that of the power source 202, or, in this particular example, 2000 volts. The third and fourth resistors 228 and 230 will divide the voltage at the output node 222 in half, applying about 1000 volt to the gate of the top low-side transistor 210. Because the bottom low-side transistor 212 is turned off, the top low-side transistor 210 will not be carrying any appreciable current and the source of the top low-side transistor 210 will be about 1000 volts, the same voltage as at the gate, also turning off the top low-side transistor 210. Thus, the voltage across each of the low-side transistors 210 and 212 is about 1000 volts, splitting the 2000 volt potential equally. Again, with different resistances in the voltage divider chain, different voltages can be applied across the transistors 204, 206, 210 and 212 in the driver 200. When the bottom low-side transistor 212 is turned off and the voltage at the output node 222 is about 2000 volts, the voltages on the top gates will be such that the two top transistors 204 and 206 are turned on resulting in an output voltage that is only a few volts less than the voltage of the power source. Thus the output voltage will be nearly 2000 volts. Typically a threshold turn on voltage is dropped across each of the gates of 204 and 206 under this condition resulting in an output voltage that is not exactly equal to but close to the voltage of the power minus 2 times the threshold voltage or, for this particular example, 2000 volts minus approximately 2 times the threshold voltage.
During another phase of operation, the bottom low-side transistor 212 is turned on and the bottom high-side transistor 206 will be turned off as described above. The output node 222 will be close to 0v, being raised slightly above 0 volts primarily by the voltage potential across the Zener diode 208, the low-side transistors 210 and 212 and the low-side resistor 214. Under this condition, the voltage at the bottom of resistor 226 is only a few volts above ground (basically equal to the threshold turn on voltage) and the gate of transistor 206 is below the threshold turn on voltage resulting in equal voltage drops across transistors 204 and 206 with both transistors 204 and 206 being turned off and supporting, for this particular example, approximately 1000 volts across each transistor (i.e., 204 and 206).
As with previous exemplary embodiments, the driver 200 may be individually controlled by a signal applied to the gate of the bottom low-side transistor 212. All drivers connected to the power source 202 may also be simultaneously controlled by adjusting the voltage and/or current from the power source 202. In this exemplary embodiment, the driver 200 provides both digital duty cycle control by applying a PWM control signal 234 and analog current control by adjusting a reference current from a current supply 236. The PWM control signal 234 may be applied to the gate of the bottom low-side transistor 212. It is to be understood that either the PWM or the analog control could be used, designed, and/or implemented separately depending on a particular application. Again, the exemplary embodiments herein comprise NMOS transistors, but the drivers could alternatively use other types of switches or transistors, including PMOS transistors, junction field effect transistors (JFETs), bipolar junction transistors (BJTs), etc. The PWM control signal 234 operates as described in the exemplary embodiment of
Analog current control is provided using a reference current from a current supply 236 that may be connected at any desired location in the path through the load 220, such as between the load 220 and ground 216. A transistor 244 and resistor 246 are placed, for example, between the load 220 and ground 216. The drain of a current mirror transistor 240 is connected to the current supply 236. The gate of the current mirror transistor 240 is connected to the drain of the current mirror transistor 240 and the gate of the transistor 244. A current limiting resistor 242 is connected between the source of the current mirror transistor 240 and ground 216. The current through the transistor 244 is proportionally limited to that flowing through the current mirror transistor 240 from the current supply 236. The current supply 236 may be provided and adjusted using any means now known or that may be developed in the future. Current through the load may alternatively be proportionally limited by a current mirror (not shown) connected between the load 220 and ground 216. Note, in this example, that additional transistors may be stacked to support larger voltages than 2000 volts or to support the same voltage if the transistors are rated at lower voltages than 1000 volts each.
Referring now to
On the left side 263, a top high-side transistor 264 is connected to the power source 254, followed in series by a bottom high-side transistor 266, Zener diode 268 (anode first), a top low-side transistor 270, a bottom low-side transistor 272 (all transistors drain first) and a current monitor resistor 274 before connecting to ground 276. The top high-side transistor 264 and top low-side transistor 270 are added to the stack to divide the higher voltage across the transistors as described above with reference to
A high-side resistor 278 is connected at one end to the power source 254 and at the other end to the gate of the bottom high-side transistor 266 and to the node between the Zener diode 268 and the top low-side transistor 270. The load 252 is connected at one end to the output node 280 between the bottom high-side transistor 266 and the Zener diode 268. A voltage divider chain made up of four resistors 282, 284, 286, and 288 balances the voltages applied to the gates of the transistors 264 and 270. In one exemplary embodiment, the resistors 282-288 of the voltage divider chain are of equal resistance. A high resistance, such as 10 Megohms, will limit the current through the voltage divider chain. Alternatively, various resistances may be selected to match the particulars including the voltages of the transistors, applying the desired voltage levels to the gates of the transistors.
The first resistor 282 is connected between the power source 254 and the gate of the top high-side transistor 264. The second resistor 284 is connected between the gate of the top high-side transistor 264 and the output node 280. The third resistor 286 is connected between the output node 280 and the gate of the top low-side transistor 270. The fourth resistor 288 is connected between the gate of the top low-side transistor 270 and ground 276. The voltages at the power source 254 and the output node 280 are divided by the resistors 282-288 of the voltage divider chain as described above with reference to the driver 200 of
The right side 290 of the exemplary driver 250 is a mirror image of the left side 263, although the method and apparatus for supplying power is not limited to this configuration. Special objectives such as asymmetrical envelopes may be met by asymmetry in the full-bridge driver 250 if desired. A top high-side transistor 294 is connected to the power source 254, followed in series by a bottom high-side transistor 296, Zener diode 298 (anode first), a top low-side transistor 300, a bottom low-side transistor 302 (all transistors drain first) and a current monitor resistor 304, before connecting to ground 276. A high-side resistor 308 is connected at one end to the power source 254 and at the other end to the gate of the bottom high-side transistor 296 and to the node between the Zener diode 298 and the top low-side transistor 300. As described above, the load 252 is connected at one end to the left side output node 280 and is connected at the other end to the right side output node 310 between the bottom high-side transistor 296 and the Zener diode 298. A voltage divider chain made up of four resistors 312, 314, 316, and 320 generates the voltages for the gates of the stacked transistors 294 and 300 as on the left side 263 of the driver 250. The first resistor 312 is connected between the power source 254 and the gate of the top high-side transistor 294. The second resistor 314 is connected between the gate of the top high-side transistor 294 and the output node 310. The third resistor 316 is connected between the output node 310 and the gate of the top low-side transistor 300. The fourth resistor 320 is connected between the gate of the top low-side transistor 300 and ground 276.
As with various other exemplary embodiments described herein, the driver 250 may be individually controlled by signals applied to the gates of the bottom low-side transistors 272 and 302, and all drivers connected to the power source 254 may be controlled simultaneously by adjusting the voltage and/or current from the power source 254. In this exemplary embodiment, the driver 250 provides both digital duty cycle control by applying PWM control signals 330 and 332 and analog current control by adjusting reference currents from current supplies 334 and 336. On the left side 263 of the driver 250 a stealer transistor 340 is connected between the gate of the bottom low-side transistor 272 and ground 276 with the source at ground 276. The PWM control signal 330 is applied to the gate of the stealer transistor 340. When the stealer transistor 340 is turned on by the PWM control signal 330, it pulls the gate of the bottom low-side transistor 272 down to ground, turning it off. On the right side 290 of the driver 250 another stealer transistor 342 is connected between the gate of the bottom low-side transistor 302 and ground 276 with the source at ground 276. The PWM control signal 332 is applied to the gate of the stealer transistor 342. When the stealer transistor 342 is turned on by the PWM control signal 332, it pulls the gate of the bottom low-side transistor 302 down to ground, turning it off.
Analog current control is provided using reference currents from current supplies 334 and 336. On the left side 263 of the driver 250, the drain of a current mirror transistor 344 is connected to the current supply 334. The gate of the current mirror transistor 344 is connected to the drain of the current mirror transistor 344, the drain of the stealer transistor 340 and the gate of the bottom low-side transistor 272. A current limiting resistor 346 is connected between the source of the current mirror transistor 344 and ground 276. The current through the bottom low-side transistor 272 is proportionally limited to that flowing through the current mirror transistor 344 from the current supply 334. On the right side 290 of the driver 250, the drain of a current mirror transistor 350 is connected to the current supply 336. The gate of the current mirror transistor 350 is connected to the drain of the current mirror transistor 350, the drain of the stealer transistor 342 and the gate of the bottom low-side transistor 302. A current limiting resistor 352 is connected between the source of the current mirror transistor 350 and ground 276. The current through the bottom low-side transistor 302 is proportionally limited to that flowing through the current mirror transistor 350 from the current supply 336. Note that the bottom low-side transistors 272 and 302 are turned on by the current mirrors 344 and 350 and current limiting resistors 346 and 352, respectively, unless the stealer transistors 340 and 342 pull their respective gates down to ground 276.
During operation, the full-bridge driver 250 with stacked transistors operates much the same as the full-bridge driver 140 of
In addition to the digital duty cycle control in the driver 250 provided by the PWM control signals 330 and 332 and the stealer transistors 340 and 342, this exemplary embodiment of a full-bridge driver 250 provides analog current control at the driver level. The current through the bottom low-side transistors 272 and 302 is proportionally limited by the current through the current mirror transistors 344 and 350, respectively. Thus, by adjusting the reference currents from the current supplies 334 and 336, the current through the load 252 may be controlled, providing independent current control through the load on a driver-by-driver basis. During one phase of operation, with the left PWM control signal 330 on, the stealer transistor 340 will be turned on, turning off the left bottom low-side transistor 272. With the right PWM control signal 332 off, the stealer transistor 342 will be turned off, turning on the right bottom low-side transistor 302. Current will therefore flow from the power source 254, through the left high-side portion 256 of the driver 250, through the load 252, through the right low-side portion 262 of the driver 250 to ground 276. The current through the load 252 during this phase of operation will be proportionally limited by the reference current flowing through the right current mirror transistor 350. During the other phase of operation, with the left PWM control signal 330 off, the stealer transistor 340 will be turned off, turning on the left bottom low-side transistor 272. With the right PWM control signal 332 on, the stealer transistor 342 will be turned on, turning off the right bottom low-side transistor 302. Current will therefore flow from the power source 254, through the right high-side portion 260 of the driver 250, through the load 252, through the left low-side portion 258 of the driver 250 to ground 276. The current through the load 252 during this phase of operation will be proportionally limited by the reference current flowing through the left current mirror transistor 344.
The actual current levels needed in the current mirror transistors 344 and 350 for full current flow through the load is dependent on the waveform from the power source 254 and on the transistor characteristics. If the power source 254 and the current supplies 334 and 336 all generate a DC current, and the temperature and other characteristics of the current mirror transistors 344 and 350 and bottom low-side transistors 272 and 302 are identical, the currents in each side of the current mirrors would be equal. However, with an alternating waveform from the power source 254 and other potential variations in the transistor characteristics, the currents may be proportional rather than equal. Furthermore, the currents through the current mirror transistors 334 and 336 can be scaled as needed for example for a particular application to the current through the bridge. The current needed from the current supplies 334 and 336 may be calculated based on the waveforms and transistor characteristics, may be determined experimentally at design-time, may be actively adjusted by a control system, or may be manually adjusted during manufacture, operation, maintenance, or repair, etc.
The current supplies 334 and 336 may comprise any current source now known or that may be developed in the future, and may be adjustable by any means. For ease in describing the driver 250, DC current supplies 334 and 336 are shown. ADC reference current may be used even when the power source 254 is providing a sine wave or some variation thereof. If the current waveforms are not matched and/or, for example, synchronized, the currents though either side of each current mirror will be proportional rather than equal as discussed above. Alternatively, AC reference currents may be used with an AC power source 254 to generate various waveforms through the load 252 as desired, with the AC reference currents synchronized or not with the AC power source 254 as desired. Again, note that to match currents exactly, the characteristics and temperature of the current mirror transistors 344 and 350 should match those of the bottom low-side transistors 272 and 302. However, as noted above, proportional current control provides excellent control of the currents through each load (e.g., 252) using any type of control system to control the reference currents, whether currently known or developed in the future.
The reference currents through each current mirror 344 and 350 may be set to equal levels to balance the current levels flowing in each direction through the load 252, or may be unequal. For example, the current flowing into the load 252 from the left side 263 of the driver 250 may be set to a higher level than the current flowing into the load 252 from the right side 290 of the driver 250, causing the load 252 to be higher on one end than the other.
Current monitoring through the load 252 is provided by the current monitor resistors 274 and 304. Current monitors (not shown) may be connected to current monitor nodes 354 and 356 to measure the voltage across the current monitor resistors 274 and 304. Current monitors may comprise any device or technique to measure voltage, whether currently known or developed in the future. The exemplary current monitor resistors 274 and 304 may alternatively be replaced by any means for identifying the variation in voltage and/or current in the driver 250, such as one or more current mirror transistors. Again, the current may be monitored using any desired technique at any suitable location in the power supply.
The full-bridge driver 250 provides a number of substantial benefits. A power supply having a single power source 254, for example having a single transformer, may power multiple drivers (e.g., 250), each driving its own corresponding load 252. High voltages may be handled by the drivers by stacking transistors, whether discrete or integrated. Digital duty cycle control is provided by PWM control inputs, and analog current control is provided by reference currents, each on the driver level so that loads powered by a single power source may be independently controlled. The driver level digital and analog control is low voltage, despite the high voltage nature of the power supply, greatly simplifying control circuitry. The PWM control signals may comprise standard 3.3 volt or 5 volt digital signals, or any other voltage level as desired. Similarly, the analog current control may be provided by low voltage current supplies. Because the current mirrors are at the bottom end of the driver 250 near ground 276, a low power current mirror having a relatively low voltage may be used to control the higher power of the high voltage driver 250. The driver 250 also provides current monitoring through the load 252.
Various elements of the exemplary embodiments disclosed herein may be combined piecemeal as desired based on the requirements of the power supply and the loads. For example, current monitoring may or may not be omitted if desired. Transistors may be stacked as deeply as desired based on the breakdown voltages of the transistors and the voltage requirements of the load. Any number of half bridges or full bridges may be put in parallel provided the power source can support this number of parallel bridges.
Referring now to
On the left side 364 of the driver 360, a primary high-side transistor 366 and low-side transistor 368 are used to switch the top 370 and bottom 372 halves of the driver on and off, as with previous embodiments. The bottom low-side transistor 368 is turned on and off by a PWM control signal 373 and is current limited by a reference current from a current supply 374 through a current mirror transistor 376. Additionally, the bottom high-side transistor 366 could be turned on and off by a diode-connected NMOS transistor 378 using the drain of transistor 378 to accomplish this in the same manner as the Zener diode (e.g., 268) of previous embodiments. Alternatively, any form or type of Zener diode or similar functioning device, circuit element or component could be used to achieve the same performance and effect. The higher 3000 volt input from the power source 362 is divided in the top half 370 across the bottom high-side transistor 366 and two additional stacked transistors 380 and 382. The 3000 volts is divided in the bottom half 372 across the bottom low-side transistor 368 and two additional stacked transistors 384 and 386. As described above, the 3000 volt potential is placed primarily across the top half 370 of the driver 360 during one phase of operation and primarily across the bottom half 372 of the driver 360 during the other phase of operation. A voltage divider chain made up of six resistors 384, 386, 388, 390, 392 and 394 generates the voltages used to bias the gates of the stacked transistors 380, 382, 384 and 386. Given equal resistances such as 10 Megohms, the 3000 volt input potential is evenly divided by the top three resistors 384, 386 and 388 during one phase of operation, and by the bottom three resistors 390, 392 and 394 during the other phase of operation.
During the first phase when current is flowing through the top half 370 of the driver 360 and the bottom half 372 of the driver 360 is switched off, very little voltage is placed across the top three resistors 384, 386 and 388 of the voltage divider chain and across the transistors 380, 382 and 366 of the top half 370 of the left side 364. Most of the 3000 volts from the power source 362 is placed across the bottom three resistors 390, 392 and 394 of the voltage divider chain and across the transistors 384, 386 and 368 of the bottom half 372 of the left side 364. Thus, the voltage at the upper end of the transistor 378 at the output node 396 will be at about 3000 volts, the voltage at the gate and source of the top low-side stacked transistor 384 will be at about 2000 volts, and the voltage at the gate and source of the bottom low-side stacked transistor 386 will be at about 1000 volts. Each transistor 384, 386 and 368 in the bottom half 372 of the driver 360 will thus each have a potential of about 1000 volts from drain to source.
During the second phase when current is flowing through the bottom half 372 of the driver 360 and the top half 370 of the driver 360 is switched off, much of the 3000 volts is placed across the top three resistors 384, 386 and 388 of the voltage divider chain and across the transistors 380, 382 and 366 of the top half 370 of the left side 364. Very little voltage is placed across the bottom three resistors 390, 392 and 394 of the voltage divider chain and across the transistors 384, 386 and 368 of the bottom half 372 of the left side 364. The voltage at the top of the voltage divider chain above resistor 384 will be about 3000 volts, the voltage at the gate and source of the top high-side stacked transistor 380 will be about 2000 volts, the voltage at the gate and source of the bottom high-side stacked transistor 382 will be about 1000 volts, and the voltage at the output node 396 will be near 0 volts plus whatever small voltage drops across the diode-connected transistor 378 (or, for example a Zener diode), the transistors 384, 386 and 368 of the bottom half 372, and the current monitor resistor 398. Each transistor 380, 382 and 366 in the top half 370 of the driver 360 will thus have a potential of about 1000 volts from drain to source across each of them. The transistor stacking and biasing operates in the same manner in the right side 400 of the driver 360.
Short circuits, for example, may be detected in the driver 360 by monitoring the voltage at the output nodes 396 and 410 to indicate when the output voltage is pulled down before reaching the load 420. On the left side 364, a voltage divider made up of two resistors 402 and 404 is connected in series between the output node 396 and ground 406. A short detector (not shown) may be connected to the short detection output 408 between the two resistors 402 and 404 to measure the voltage of the output node 396. Any means for measuring the voltage at the short detection output 408 may be used as a short detector. The resistance of the two resistors 402 and 404 may be selected to provide an easily measurable voltage at the short detection output 408, given the voltage of the power source 362. For example, the resistance may be selected to scale the 3000 volts of the power source 362 down to 5 volts or 3.3 volts. On the right side 400, another voltage divider made up of two resistors 412 and 414 is connected between the right output node 410 and ground 406, with a short detection output 416 connected between the two resistors 412 and 414. During one phase of operation, one output node 396 should be at about 3000 volts (minus the voltage drop across the transistors 380, 382 and 366 in the top half 370 of the left side 364) and the opposite output node 410 should be at about 0 volts (plus the voltage drop across the various transistors and the resistor in the bottom half 422 of the right side 400). If the resistors 402, 404, 412 and 414 were selected to divide the 3000 volts down to 5 volts at the short detection outputs, the left short detection output 408 should be at about 5 volts and the right short detection output 416 should be at about 0 volts during normal operation. If both short detection outputs 408 and 416 drop to about 0 volts during normal operation with the power source 362 active and the PWM controls (e.g., 373) and reference currents set at the proper levels, the driver 360 may have a fault such as a short to ground and this can be detected and properly handled. The above is just one example of how to accomplish the short detection; it should be clear to anyone skilled in the art that there are numerous ways to accomplish the above. All of these are within the scope of the present invention.
Referring now to
The exemplary driver 450 of
An exemplary synchronous embodiment in which the PWM control signals 470 and 472 are switched at the frequency of the power sources 462 and 464 will now be described, with the waveform of
Note again that the use of dual power sources 462 and 464 enables the current through the load 460 to be shaped with various desired envelopes by setting the amplitudes or frequencies at different levels on each side.
In one exemplary embodiment, negative voltage protection diodes 456 and 458 are added anode-up between the Zener diodes 484 and 486 and the top stacked transistors 488 and 490, respectively, in the low-side portions 474 and 478 of the driver 450. If the power sources 462 and 464 go to negative voltages as illustrated in
Referring now to
As described above with respect to
In this exemplary embodiment 610, distributed negative voltage protection diodes 670, 672 and 674 are included, allowing negative voltages from the power source 642 to reach the output 682 and protecting the transistors 612-616 and 622-626 from damage that might otherwise be caused by the effects of the negative voltages due to the parasitic diodes in those transistors. The negative voltage protection diodes 670, 672 and 674 prevent current from flowing up through the low-side portion 628 of the driver 610 from ground 644 when the power source 642 is at negative potentials. The anode of diode 670 is connected to the node between the cathode of Zener 650, the control input of the bottom high-side transistor 616 and the high-side resistor 652. The cathode of diode 670 is connected to the drain of the top low-side transistor 622. The anode of diode 672 is connected to the source of the top low-side transistor 622 and the cathode of diode 672 is connected to the drain of the middle low-side transistor 624. The anode of diode 674 is connected to the source of the middle low-side transistor 672 and the cathode of diode 674 is connected to the drain of the bottom low-side transistor 626. Additional negative voltage protection diodes may be added for additional stacked transistors, with one diode distributed in the driver 610 for each stacked transistor in this exemplary embodiment. Note that a single negative voltage diode may be included per side of the driver bridge as in
Referring now to
The power supplied by the power source may also be controlled globally for all outputs or drivers by pulse width modulating the power source using any suitable means in any suitable location. For example, a PWM control circuit 524 may be used to enable and disable the signal from the oscillator to the primary winding of the transformer. The PWM control circuit 524 may comprise any suitable circuit to apply pulse width modulation to the power signal, such as, for example, an AND gate at the output of the oscillator, or a PWM signal applied directly to a 555 timer to enable and disable the output, or a stealer transistor applied anywhere desired in the power source, or a transistor placed in series with the primary or secondary winding of the transformer under the control of a PWM control signal, etc. A PWM control circuit 524 may be applied in any embodiment of the power source as desired, such as in the embodiments illustrated in
Referring now to
Referring now to
Referring now to
Note that the exemplary embodiments in
Referring now to
Turning now to
For example, as disclosed in
As disclosed in
As disclosed in
As disclosed in
As disclosed in
As disclosed in
The example embodiments disclosed herein illustrate certain features of the present invention and not limiting in any way, form or function of present invention. The present invention is, likewise, not limited in materials choices including semiconductor materials such as, but not limited to, silicon (Si), silicon carbide (SiC), silicon on insulator (SOI), other silicon combination and alloys such as silicon germanium (SiGe), etc., diamond, graphene, gallium nitride (GaN) and GaN-based materials, gallium arsenide (GaAs) and GaAs-based materials, etc. The present invention can include any type of switching elements including, but not limited to, field effect transistors (FETs) of any type such as metal oxide semiconductor field effect transistors (MOSFETs) including either p-channel or n-channel MOSFETs of any type, junction field effect transistors (JFETs) of any type, metal emitter semiconductor field effect transistors, etc. again, either p-channel or n-channel or both, bipolar junction transistors (BJTs) again, either NPN or PNP or both, heterojunction bipolar transistors (HBTs) of any type, high electron mobility transistors (HEMTs) of any type, unijunction transistors of any type, modulation doped field effect transistors (MODFETs) of any type, etc., again, in general, n-channel or p-channel or both, vacuum tubes including diodes, triodes, tetrodes, pentodes, etc. and any other type of switch, etc.
The present invention can also include circuit breakers including solid state circuit breakers and other devices, circuits, systems, etc. that limit or trip in the event of an overload condition/situation. The present invention can also include one or more of the following: constant current control, constant power control, constant voltage control, overvoltage protection, over current protection, short circuit protection, undervoltage protection, over temperature protection, etc. The present invention can also include, for example analog or digital controls including but not limited to wired (i.e., 0 to 10 Volt, RS 232, RS485, RS422, universal serial bus (USB), general purpose interface bus (GPIB), IEEE standards, SPI, I2C, SPC, other serial and parallel standards and interfaces, etc.), wireless (including RF, microwave, and infrared (IR, etc.), powerline, etc. and can be implemented in any part of the circuit for the present invention. The present invention can be used with a buck, a buck-boost, a boost-buck and/or a boost, flyback, or forward-converter design, topology, implementation, etc. Time constants and other types of filters including, but not limited to, low pass, high pass, notch, bandpass, first order, second order, higher order, etc. may also be used with the present invention.
A voltage signal which represents a voltage from, for example but not limited to, a 0 to 10 Volt analog signal can be used with the present invention; when such a signal is connected, the output as a function time or phase angle will correspond to the inputted signal. Other voltage ranges (0 to 1 V, 0 to 2 V, 0 to 3 V, 0 to 5 V, etc.) can also be used with the present invention.
Other embodiments can use comparators, other op amp configurations and circuits, including but not limited to error amplifiers, summing amplifiers, log amplifiers, integrating amplifiers, averaging amplifiers, differentiators and differentiating amplifiers, etc. and/or other digital and analog circuits, timers, PWM controllers microcontrollers, microprocessors, complex logic devices, field programmable gate arrays (FPGAs), PWM microcontrollers, microprocessors, FPGAs, CLDs, analog to digital converters (ADCs), digital to analog converters (DACs), etc. firmware and software and associated interfaces, etc. may also be used with the present invention.
The present invention includes implementations that contain various other control circuits including, but not limited to, linear, square, square-root, power-law, sine, cosine, other trigonometric functions, logarithmic, exponential, cubic, cube root, hyperbolic, etc. in addition to error, difference, summing, integrating, differentiators, etc. type of op amps. In addition, logic, including digital and Boolean logic such as AND, NOT (inverter), OR, Exclusive OR gates, etc., complex logic devices (CLDs), field programmable gate arrays (FPGAs), microcontrollers, microprocessors, application specific integrated circuits (ASICs), etc. can also be used either alone or in combinations including analog and digital combinations for the present invention. The present invention can be incorporated into an integrated circuit, be an integrated circuit, etc.
Power may be supplied from any type of power supply including AC to DC, DC to DC, DC to AC, AC to AC using any type of topology including, but not limited to, discontinuous conduction mode (DCM), continuous conduction mode (CCM), critical conduction mode (CRM), resonant mode, isolated, non-isolated, flyback, forward converter, half-bridge, full-bridge, Cuk, SEPIC, etc. Certain embodiments of the present invention may be part of power supply including the aforementioned ones above such as AC to DC, DC to DC, DC to AC, AC to AC converters and inverters using any type of topology including, but not limited to, discontinuous conduction mode (DCM), continuous conduction mode (CCM), critical conduction mode (CRM), resonant mode, isolated, non-isolated, flyback, forward converter, half-bridge, full-bridge, Cuk, SEPIC, a buck, a buck-boost, a boost-buck and/or a boost, or forward-converter design, topology, implementation, etc.
The power supply multiple drivers disclosed herein provides substantial benefits over conventional power supplies. Multiple loads may be driven by the current from a single high voltage power source, and the current may be controlled individually using low voltage analog and/or digital control inputs including being PWM controlled. The drivers are envelope-driven, enabling various envelopes or waveforms to be supplied to a load. A low cost, compact power supply may thus be used to provide multiple easily controlled outputs.
While illustrative embodiments have been described in detail herein, it is to be understood that the concepts disclosed herein may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art.
This is a continuation-in part of U.S. patent application Ser. No. 13/190,261, filed Jul. 25, 2011, which was a continuation of U.S. patent application Ser. No. 12/717,350, filed Mar. 4, 2010, which was a continuation-in-part of U.S. patent application Ser. No. 11/681,767, filed Mar. 3, 2007, all of which are incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12717350 | Mar 2010 | US |
| Child | 13190261 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13190261 | Jul 2011 | US |
| Child | 13865984 | US | |
| Parent | 11681767 | Mar 2007 | US |
| Child | 12717350 | US |
