Claims
- 1. A computational random access memory comprising:
a memory comprising N columns, N being an integer; and an arithmetic logic unit, in communication with the N columns in the memory, the arithmetic logic unit comprising:
M multipliers, m being an integer divisible into N, each of the m multipliers being configured to multiply two N/M-bit numbers; and an adder stage, in communication with the M multipliers to receive outputs of the M multipliers, for forming and outputting calculation results in accordance with the outputs of the M multipliers.
- 2. The computational random access memory of claim 1, wherein M=2.
- 3. The computational random access memory of claim 1, wherein the arithmetic logic unit is configured to multiply two N-bit numbers by:
(a) multiplying, in the M multipliers, a plurality of combinations of N/M bits of the two N-bit numbers to form a plurality of partial products; and (b) accumulating, in the adder stage, the plurality of partial products to provide a product of the two N-bit numbers.
- 4. The computational random access memory of claim 3, wherein the arithmetic logic unit is configured to add two N-bit numbers by multiplication by one in the multipliers and forming a sum in the adder stage.
- 5. The computational random access memory of claim 1, wherein:
the memory comprises a plurality of groups of N columns; a plurality of said arithmetic logic units are provided, one for each of the plurality of groups of N columns; and the computational random access memory further comprises a secondary processing logic, in communication with the plurality of arithmetic logic units to receive outputs of the plurality of arithmetic logic units, the secondary processing logic comprising a plurality of adders for combining calculation results from the plurality of arithmetic logic units to permit calculations on numbers of more than N bits.
- 6. The computational random access memory of claim 5, wherein the plurality of groups of N columns of the memory are arranged in a plurality of rows, each of the plurality of rows comprising said arithmetic logic units and said secondary processing logic.
- 7. The computational random access memory of claim 6, wherein, in each of the rows, the groups of columns are interconnected by a diagonal connection.
- 8. The computational random access memory of claim 6, wherein, in each of the rows, the groups of columns are interconnected by an N-bit word connection.
- 9. The computational random access memory of claim 8, wherein, in each of the rows, the groups of columns are also interconnected to a diagonal connection.
- 10. The computational random access memory of claim 9, further comprising a plurality of two-way shift registers, each interconnecting two of the groups of N columns in two of the rows.
- 11. The computational random access memory of claim 1, wherein:
the arithmetic logic unit further comprises a repair multiplier in addition to the M multipliers; and each of the M multipliers comprises an input for receiving a repair signal which controls that multiplier to replace its output with an output received from the repair multiplier.
- 12. The computational random access memory of claim 11, wherein the arithmetic logic unit further comprises a repair-input muxing unit for selecting inputs to the repair multiplier.
- 13. A method for performing a calculation on two N-bit numbers, the method comprising:
(a) providing M multipliers, M being an integer divisible into N, each of the M multipliers being configured to multiply two N/M-bit numbers; (b) providing an adder stage, in communication with the M multipliers to receive outputs of the M multipliers; (c) dividing each of the N-bit numbers into M combinations of N/M bits; (d) performing multiplications involving the M combinations of N/M bits in the M multipliers to provide outputs; and (e) forming and outputting, in the adder stage, calculation results in accordance with the outputs of the M multipliers.
- 14. The method of claim 13, wherein M=2.
- 15. The method of claim 13, wherein, when the calculation is multiplication, the two N-bit numbers are multiplied by:
(i) multiplying, in the M multipliers, the plurality of combinations of NIM bits of the two N-bit numbers to form a plurality of partial products; and (ii) accumulating, in the adder stage, the plurality of partial products to provide a product of the two N-bit numbers.
- 16. The method of claim 13, wherein, when the calculation is addition, the two N-bit numbers are added by multiplication by one in the multipliers and by forming a sum in the adder stage.
- 17. The method of claim 13, further comprising:
(f) further providing a repair multiplier in addition to the M multipliers; (g) determining which, if any, of the M multipliers is not operating properly and generating a repair signal identifying said one of the M multipliers is not operating properly; (h) controlling the multiplier which is not operating properly to replace its output with an output received from the repair multiplier.
REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims the benefit of U.S. Provisional Application Nos. 60/370,722 and 60/370,723, both filed Apr. 9, 2002, whose disclosures are hereby incorporated by reference in their entireties into the present disclosure.
STATEMENT OF GOVERNMENT INTEREST
[0002] The work leading to the present application was supported, in part, by National Science Foundation grant CCR-0073469 and by New York State Office of Science, Academic & Research (MDC) grant NYSTAR 02332105. The government has certain rights in the present invention.
Provisional Applications (2)
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Number |
Date |
Country |
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60370723 |
Apr 2002 |
US |
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60370722 |
Apr 2002 |
US |