Patent Application
20050276106
1. Field of Invention
This invention pertains generally to semiconductor memory devices and, more particularly, to a NAND flash memory and fabrication process.
2. Related Art
Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's), cellular phones, and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture.
The traditional NOR-type stack-gate flash memory cell usually has a bit line contact, a source region, a floating gate, and a control gate, with the control gate being positioned directly above the floating gate. Its relatively large cell size prevents it from being used in very high density data storage applications.
Cell size is smaller in a NAND flash memory array having a series of stack-gate flash memory cells connected in series between a bit-line and a source line, with only one bit-line contact, as illustrated in
Two select gates 29, 31 are included in the array, one near the bit line contact 32 and one near source diffusion 23. Diffusions 33 are formed in the substrate between the stacked gates and between the stacked gates and the select gates to serve as source and drain regions for the transistors in the memory cells. The bit line diffusion, source diffusion, and the diffusions 33 are doped with N-type dopants.
To erase the memory cell, a positive voltage of about 20 volts is applied between the P-well and the control gates, which causes the electrons to tunnel from the floating gates to the channel regions beneath them. The floating gates thus become positively charged, and the threshold voltage of the stack-gate cells becomes negative.
To program the memory cells, the control gates are biased to a level of about 20 volts positive relative to the P-well. As electrons tunnel from the channel region to the floating gates, the floating gates are negatively charged; and the threshold voltage of the stack-gate cells becomes positive. By changing the threshold voltage of a stack-gate cell, the channel beneath it can be in either a non-conduction state (logic “0”) or a conduction state (logic “1”) when a zero voltage is applied to the control gate during a read operation.
However, as the fabrication process advances to very small geometries, e.g., tens of nanometer, it is difficult to form a high-voltage coupling ratio which is sufficient for program and erase operations while maintaining a small cell size.
It is in general an object of the invention to provide a new and improved semiconductor device and process of fabricating the same.
Another object of the invention is to provide a semiconductor device and process of the above character which overcome the limitations and disadvantages of the prior art.
These and other objects are achieved in accordance with the invention by providing a NAND flash memory cell array in which control gates and charge storage gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide.
In the disclosed embodiments, programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates.
As illustrated in
In this embodiment, the charge storage gates extend beneath and along the lower portions of the side walls of the control gates. They are fabricated of nitride or the combination of nitride and oxide, with a preferred thickness on the order of 60 Å to 200 Å. Dielectric films 42 are formed between the charge storage gates and control gates, and gate insulators 40 are formed beneath and along the sides of the charge storage gates. The dielectric films can be a pure oxide or a nitrided oxide. The control gates are fabricated of a conductive material such as a doped polysilicon or polycide.
Cell select gates 43 are positioned between stack-gate cells 36, and row select gates 44, 45 are positioned between the cells at the ends of the row and bit line contact 46 and source diffusion 51. The select gates are fabricated of a conductive material such as a doped polysilicon or polycide. They are parallel to the control gates and the charge storage gates. The select gates are separated from the substrate by gate oxide layers 53, which can be either a pure oxide or a combination of oxide and nitrided oxide. They are insulated from the charge storage gates by gate insulators 40.
Select gates 44 and 45 partially overlap bit line diffusion 50 and common source diffusion 51, with edge portions of the two gates being positioned above edge portions of the diffusions. The common source diffusions extend continuously in a direction perpendicular to the rows in which the cells are grouped, and are shared by groups of cells on both sides of the diffusions.
As best seen in
The memory cell array of
A conductive layer 59 of polysilicon (poly-1) is deposited on the thermal oxide to a thickness on the order of 300 Å to 1500 Å, and a dielectric layer 61 is formed on the silicon. This silicon is preferably doped with phosphorus, arsenic or boron to a level on the order of 1018 to 1020 per cm3. The doping can be done in-situ during deposition of the silicon or by ion implantation directly into the silicon or through the dielectric 61 above it.
A photolithographic mask 64 is applied to dielectric layer 61 to define the select gates. The unmasked portions of the dielectric and silicon layers are etched away anisotropically to form select gates 43, 44, 45, as illustrated in
As illustrated in
Thereafter, a glass material 60 such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) is deposited across the entire wafer, then etched to form openings for bit line contacts 46, as shown in
Operation and use of the memory cell array can be described with reference to
Erasing can be done using two different bias conditions. In erase mode 1 (ERS1), the control gate is biased at 0 volts, the select gates are biased at 0 to 4 volts, the bit line and common source are floating, and P-well is biased at 7 to 12 volts. With this bias condition, a uniform channel tunneling occurs. As the charge storage gate becomes more positively charged, the threshold voltage of the memory cell, which is preferably on the order of −1 to 1 volt in this embodiment, becomes lower. This results in an inversion layer in the channel beneath the charge storage gate when the control gate is biased at about 1.5 volts. Therefore, the memory cell goes into the conductive state (logic “1”) after the erase operation.
In erase mode 2 (ERS2), the control gate of the selected cell is biased at 0 volts, the control gates of unselected cells are biased at 3 to 8 volts, the select gates are biased at 3 to 6 volts, the bit lines are biased at 2 to 4 volts, and the common source is biased at 5 to 9 volts. With this bias condition, a hot hole injection happens between the silicon substrate and the charge storage gate of the selected cell. As the charge storage gate becomes more positively charged, the threshold voltage of the memory cell, which is preferably on the order of −1 to 1 volt in this embodiment, becomes lower. This results in an inversion layer in the channel beneath the charge storage gate when the control gate is biased at about 1.5 volts. Therefore, the memory cell goes into the conductive state (logic “1”) after the erase operation.
During a program operation, the control gate of the selected memory cell C1n is biased to a level of 8-12 volts, 5-10 volts is applied to select gates SG0 and SG2-SG16, 5-10 volts is applied to the control gates of the other memory cells in the same bit line direction as the selected cell (e.g. C0n and C2n), 0-1 volts is applied to the bit line, 0 volts is applied to P-well, and 3-8 volts is applied to the common source. The cells and the select transistors are turned on by applying 5-10 volts to the control gates and the select gates. The voltage applied to the select gate just before the selected cell (SG1 and C1n in this example) can be on the low side, preferably on the order of 1-2 volts.
With this bias condition, most of the voltage between the common source and the bit line appears across the mid-channel region between select gate SG1 and the charge storage gate of the selected cell C1n, resulting in a high electric field in that region. In addition, since the charge storage gate is coupled to a high voltage from the common source node (i.e., control gate CG1 and select gate SG2), a strong vertical electric field is established across the oxide between the mid-channel region and the charge storage gate. When electrons flow from the bit line to the common source during the program operation, they are accelerated by the electric field across the mid-channel region, and some of them become heated. Some of the hot electrons get accelerated by the vertical field, which causes them to overcome the energy barrier of the oxide (about 3.1 eV) and inject into the charge storage gate.
At the end of the program operation, the charge storage gate is negatively charged, and the threshold voltage of the memory cell, which preferably is on the order of 2-4 volts, becomes higher. Thus, the memory cell is turned off when the control gate is biased at about 1.5 volts during a read operation. Following a program operation, the memory cell goes into a non-conductive state (logic “0”).
In the unselected memory cells C1(n−1), and C1(n+1) which share the same control gate with the selected cell C1n, the bit line is biased at 3 volts, the select gate SG1 is at 1-2 volts, and the control gate is at 8-12 volts. Thus, select transistors S1(n−1) and S1(n+1) are turned off, and there is no mid-channel hot carrier injection taking place in cells C1(n−1) and C1(n+1). The other unselected memory cells C0n and C2n are biased with 0-1 volts to the bit line, 5-10 volts to the control gates, and 5-10 volts to the select gates just before them, which minimizes the mid-channel hot carrier injection, and the charge storage gate charges are unchanged.
In the read mode, the control gate of the selected memory cell C1n is biased at about 1.5 volts, the common source is biased to 0 volt, 1-3 volts is applied to the bit line, and Vcc is applied to the select gates. The unselected memory cells in the bit line direction, e.g. C0n and C2n, are turned on by applying 5-9 volts to their control gates. When the memory cell is erased, the read shows a conductive state because the channel of selected cell is turned on, and the other cells and the select transistors in the same bit line direction also turned on. Thus, a logic “1” is returned by the sense amplifier. When the memory cell is programmed, the read shows a non-conductive state because the channel of the selected cell is turned off, and hence the sense amplifier returns a logic “0”. In the unselected memory cells C1(n−1) and C1(n+1), both the bit line and common source nodes are biased at 0 volts, and there is no current flow between the bit line and the common source nodes.
The embodiment of
As in the embodiment of
A preferred process of fabricating the embodiment of
A charge storage layer 62 of a nitride or the combination of nitride and oxide is formed on the thermal oxide to a thickness on the order of 60 Å to 200 Å. Then, another dielectric layer 42 is formed on the charge storage layer. This dielectric can be a pure oxide layer or a nitrided oxide layer.
A conductive layer 63 of polysilicon (poly-1) is deposited on dielectric film 42. This layer has a thickness on the order of 1500 Å-3500 Å, and is doped with phosphorus, arsenic or boron to a level on the order of 1020 to 1021 per cm3. A CVD oxide or nitride layer 66 having a thickness on the order of 300 Å-1000 Å is deposited on the poly-1 layer, and is used as a mask to prevent the poly-1 material from etching away during subsequent dry etching steps.
A photolithographic mask 67 is formed over layer 66 to define the control gates, and the unmasked portions of that layer and poly-1 layer 63 are etched away anisotropically, leaving only the portions of the poly-1 which form the control gates 38. The exposed portions of the dielectric 42 and the underlying portions of the charge storage layer 62 are then etched away anisotropically to form the charge storage gates 37, as illustrated in
Then, a dielectric 47 is formed on the sidewalls of control and charge storage gates, and a conductive (poly-2) layer 59 is deposited over the entire wafer, as shown in
The poly-2 layer is then etched anisotropically to form select gates 43, 44, 45, as illustrated in
Thereafter, a glass material 60 such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) is deposited across the entire wafer, then etched to form openings for bit line contacts 46, as shown in
Operation of the embodiment of
The invention has a number of important features and advantages. It provides a NAND flash memory cell array with significantly smaller cell size and greater cell density than memory structures heretofore provided. The array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
It is apparent from the foregoing that a new and improved NAND flash memory and process of fabrication have been provided. While only certain presently preferred embodiments have been described in detail, as will be apparent to those familiar with the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
