Patent Application
20100283570
In the manufacture of integrated circuit devices, voltage regulators are generally located separate from the integrated circuit die. On die voltage regulators, known as integrated silicon voltage regulators (ISVR), are highly desired. However, issues such as eddy currents tend to appear in conventional metal magnetic films used for ISVR, thereby causing reliability issues.
Conventional off-die voltage regulators tend to be relatively large and consume considerable power. Off-die voltage regulators are also slow relative to ISVR devices due to impedance caused by the length of the connection to the integrated circuit transistors. This slowness causes a bottleneck as integrated circuit devices are made smaller and faster. Accordingly, improved ISVR devices are needed to reduce eddy currents and eliminate the need for off-die voltage regulators.
Described herein are systems and methods of forming an integrated silicon voltage regulator (ISVR) using a nano-encapsulated magnetic particle suspension. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Implementations of the invention provide structures and fabrication methods for an ISVR device formed using nano-encapsulated magnetic particles dispersed within a dielectric material. For ease of reference, this mixture of magnetic particles within a dielectric material will be referred to herein as a “nano-encapsulated magnetic particle suspension,” or simply as the “suspension”. The magnetic particles may be formed using metals such as cobalt, nickel, and iron that are encased within a protective nano-encapsulation shell. The nano-encapsulation shell may be formed using materials that include, but are not limited to, aluminum oxide, silicon dioxide, silicon nitride, tantalum nitride, titanium nitride, fluorinated silicon dioxide, carbon doped oxide, tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), low-k materials, high-k materials, organic polymers such as perfluorocyclobutane and polytetrafluoroethylene, inorganic polymers, and organosilicates such as silsesquioxane, siloxane, and organosilicate glass. The nano-encapsulation shell protects the magnetic particles from oxidation and loss of magnetic moment.
For reference,
The method 100 of
Components such as transistors, inductors, and diodes may be formed on the surface of the substrate or within layers formed on the substrate. The semiconductor substrate generally includes one or more layers of material on its surface, such as semiconductive layers, dielectric layers, and conductive layers that have been photolithographically patterned and etched to form semiconductor device features over, on, or within the substrate. The semiconductive layers may include one or more of epitaxial silicon, polysilicon, amorphous silicon, doped polysilicon, or the like.
The dielectric layers may be formed using materials known for the applicability in dielectric layers for integrated circuit structures, such as one or more of silicon dioxide (SiO2), fluorinated SiO2, carbon doped oxide (CDO), silicon nitride (SiN), tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin on glass (SOG), low-k materials, high-k materials, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, inorganic polymers, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The dielectric layer may include pores or other voids to further reduce its dielectric constant.
The conductive layers include metal interconnects and metal vias. These structures are generally formed of one or more of refractory silicides, refractory metals, aluminum, copper, tungsten, alloys of these materials, conductive nitrides, conductive oxides, or the like. Each conductive layer also includes interlayer dielectric (ILD) material surrounding and insulating the metal interconnects and the vias.
A passivation layer is formed over the above described layers of the IC device to seal and protect these layers. The passivation layer is generally formed of silicon nitride and may contain vias that electrically couple components within the IC device to components outside of the IC device.
On the final metallization layer 206-n are a number of bond pads 208. One or more interconnects of the metallization layers 206 terminate at the bond pads 208, which are generally formed of copper, aluminum, or alloys thereof. A passivation layer 210 is formed above the metallization layers 206 to seal and protect the IC device 200 and the metallization layers 206 from damage and contamination. The passivation layer 210 may be formed from many different materials, including but not limited to silicon nitride (SiN), oxynitride, polyimide, and certain polymers. As is known in the art, openings may be formed in the passivation layer 210 to expose the bond pads 208.
Returning to
The weight fraction of nano-encapsulated magnetic particles to dielectric material may range from 30% to 70%, depending on the variables such as the desired magnetic properties of the material, the specific metals used for the magnetic particles, and the specific dielectric material that is chosen. Other factors may be taken into consideration as well.
As noted above, in accordance with implementations of the invention, the NEMP suspension may be used to form the MCM layers of the ISVR. Therefore, the method 100 continues by using a spin-coating deposition process to deposit a first layer of the NEMP suspension onto the IC device (106). The NEMP suspension is typically formed on the passivation layer of the IC device, although in alternate implementations it may be deposited on a layer other than the passivation layer.
In implementations of the invention, the spin-coating deposition process may be adjusted to address issues that may arise, such as the NEMP suspension developing thixotropic properties at relatively high magnetic particle loadings. The adjustments that may be made include dilution of the NEMP suspension with MSSQ or common organic solvents including PGMEA, methyl isobutyl ketone (MIBK), chloroform, chlorobenzene, common alcohols (e.g., isopropanol, ethanol, and methanol), and toluene. Reflow agents may also be used to dilute the NEMP suspension. Further, the NEMP suspension may be adjusted using additional processing such as planarization, chemical mechanical polishing, annealing, spinning, laser ablation, or chemical etching. These processes may be used to improve film thickness uniformity across the surface of the wafer.
Next, the NEMP suspension that has been deposited on the IC device is cured using ultraviolet (UV) radiation (108). In some implementations, a thermal anneal may be used in lieu of UV curing. In one implementation, the thermal anneal may occur at around 150° C. in an ambient atmosphere. The UV or thermal cure promotes polymerization of the MSSQ into a glassy, amorphous, and low-k dielectric material, thereby forming a composite layer consisting of the glassy dielectric layer having the nano-encapsulated magnetic particles dispersed throughout its matrix. The composite layer therefore provides both insulating functionality and magnetic functionality. The nano-encapsulation shells continue to protect the magnetic particles from oxidation and loss of magnetic moment. For ease of reference, this composite layer will be referred to herein as a “NEMP composite layer”.
In some implementations of the invention, the thickness and uniformity of the NEMP composite layer may be increased by spin-depositing and curing one or more additional layers of the NEMP suspension.
The NEMP composite layer is used as an MCM layer for the ISVR device being fabricated by the method 100 of
In an alternate implementation, prior to the spin-coating deposition of the NEMP suspension in process 106, a patterned photoresist mask may formed that defines areas of the IC device where the first MCM layer is to be formed. For instance, conventional methods for depositing and patterning a photoresist material may be used to form a photoresist mask with at least one opening that exposes the underlying IC device. This opening defines where the first MCM layer is to be formed, and the spin-coating deposition process will fill this opening with the NEMP suspension. A planarization process may be used to remove excess material from the field of the photoresist mask.
One or more inductor wires may be formed atop the NEMP composite layer (110). Conventional metal deposition processes may be used to form the inductor wires, such as dual damascene processes that are well known in the art. The inductor wires may be formed using conventional metals used in semiconductor applications, including but not limited to copper and aluminum. An insulating material, such as an interlayer dielectric material, may then be formed over the inductor wires (112). This dielectric material may be any known dielectric material suitable for use here, such as any of the dielectric materials described herein.
The fabrication of the ISVR continues by using a spin-coating deposition process to deposit a second layer of the NEMP suspension on the IC device (114). Here, the NEMP suspension is deposited on the interlayer dielectric that surrounds the inductor wires. As with the previous spin-coating deposition, adjustments may be made to address any thixotropic issues that have arisen, such as dilution of the NEMP suspension, addition of a reflow agent, or the addition of a planarization step to the process flow. The NEMP suspension is then cured using ultraviolet radiation or thermal anneal, thereby forming a second NEMP composite layer over the inductor wires (116). Again, the thickness of this NEMP composite layer may be increased by spin-depositing and curing one or more additional layers of the NEMP suspension.
This second NEMP composite layer that that has been formed over the inductor wires may be used as the second MCM layer 312 of the ISVR 300 in
Accordingly, a novel NEMP composite layer has been described that may be applied using spin-coat deposition and curing processes and provides both magnetic and insulating functionality. The NEMP composite layer provides improved device response time, an increased number of power states, and low impedance access to the transistors. The use of a nano-encapsulation shell on the magnetic particles prevents oxidation and loss of magnetic moment. Finally, the NEMP suspension provides in-situ conversion of magnetic material to insulator.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
