The present application claims priority to European Patent Application No. 21306536.0, filed Nov. 2, 2021, the entire contents of which are incorporated herein by reference.
The present invention relates to the field of integration and, more particularly, to nanowire structures for integration, electronic products and related semiconductor products including such nanowire structures, and their methods of manufacture.
Nowadays, semiconductor manufacturing techniques include technologies for integrating passive components. For example, the PICS technology developed by Murata Integrated Passive Solutions allows high density capacitive components to be integrated into a silicon substrate. According to this technology, tens or even hundreds of passive components can be efficiently integrated into a silicon die.
In their work titled “Nanotubular metal-insulator-metal capacitor arrays for energy storage” (published in Natural technology, May 2009), P. Banerjee et al. describe a metal-insulator-metal (MIM) structure formed in a porous anodic material, such as porous anodic alumina (PAA) for example. The successive layers of metal, insulator, and then metal follow the contours of the porous material resulting in the MIM structure being embedded inside the pores of the porous material and, thus, increase the specific area of the capacitor electrodes. Banerjee's PAA embedded structure however suffers from high Equivalent Series Resistance (ESR) and limited capacitance density due to the PAA thickness that can be deposited by Atomic Layer Deposition (ALD).
Generally, embedded structures as described above result from embedding a structure (e.g., a MIM capacitive stack) inside a porous region above a substrate, such as a silicon wafer. Typically, the porous region results from anodizing a thin layer of metal, such as aluminum, deposited above the substrate. The anodization process converts the metal layer into a porous anodic oxide (e.g. an aluminum layer is converted into porous anodic alumina). The anodization process may be implemented in a known manner to form a self-organized array of elongated pores that are substantially parallel to one another and substantially perpendicular to the substrate surface, at least in the central zone of the porous region. Typically, the boundary of the porous region may be formed with any desired shape (as viewed from the top) by use of a suitable hard mask.
A structure by F. Voiron et al. that improves Banerjee's ESR and capacitance is described in international application publication WO 2015/063420. Voiron's structure results in highly integrated capacitance that may be used in a variety of applications. In this structure the bottoms of the pores are opened and the lower metal layer of the MIM structure contacts a conductive layer that underlies the porous region, providing electrical contact and reducing ESR.
This latter technology provides highly-integrated capacitance which can be used for different applications. For some applications, Equivalent Series Resistance (ESR) is a key parameter of the device. This is for example the case for capacitive elements used for decoupling processors. In this context, capacitors are used as a local energy tank (and thus are placed very nearby to the processor), to compensate for voltage drop induced by power supply line impedance in the case of large current swings.
Those current swings can be as large as 100 A for recent processors. In that case, the capacitor can provide the charges (i.e. current) required by the processor for a short period. As the current provided by the capacitor is fed through the internal capacitor resistance (Equivalent Series Resistance), it is desirable that the ESR is kept as low as possible to prevent voltage drop at the capacitor terminal. Similar reasoning applies for the inductive parasitics (i.e. Equivalent Series Inductance) that also should be minimized. Finally, the larger the capacitance (i.e. specific capacitance density) the larger the event that can be filtered by the capacitor: for example, a supply interruption lasting about a picosecond for a capacitor having capacitance of approximately 1 nF, and a nanosecond supply interruption for a μF capacitor.
As described in the Applicants' earlier patent application EP 3656734, an even lower ESR can be achieved, together with 15% increase in capacitance density, by using a different approach for increasing the specific area of the capacitor electrodes, namely forming the MIM capacitive stack conformally over a group of aligned nanopillars projecting from the substrate (instead of embedding the MIM stack in pores of porous anodic oxide).
In the case described in EP 3656734 the nanopillars are metallic nanowires and they are formed by first creating a porous anodic oxide matrix, then forming metallic columns within the pores, then removing the porous anodic oxide matrix to release the nanowires.
Other techniques are known for forming aligned arrays of nanopillars projecting from a substrate. For example, WO 2008/060665 describes techniques for forming an array of aligned carbon nanotubes by chemical vapor deposition (CVD) using a patterned catalyst.
It should be noted that other electronic structures, besides capacitive structures, can be formed using such arrays of aligned nanopillars.
Despites the advantages that derive from using arrays of aligned nanopillars to form electronic components for integration into integrated circuits, the vertical extension of the wires above the substrate surface intrinsically generates relief features (high topologies) that can be difficult to manage. More particularly, integrated circuit manufacture generally involves formation of various active and/or passive components in a plurality of superposed layers. In the case where significant relief features are produced in a particular layer of the circuit, it may be difficult (or, even, impossible) to form the layer(s) that should be superposed on that particular layer and/or difficult to create contacts to the components formed in that particular layer.
This problem will be discussed in greater depth with reference to
In this example, as illustrated in
It may be desirable for some applications to form a circumscribed porous region within the original metal layer 8. For example, it may be desirable to control the size of the resulting porous region in order to control the size and electrical value (e.g., capacitance, resistance, etc.) of the electronic component that will be formed there. Typically, this is done by applying, on top of metal layer 8, a hard mask layer 10 with openings 12 therein to define regions where porous AAO is to be formed. Hard mask layer 10 masks the part of metal layer 8 that is not intended to be anodized. The masking shields this area from contact with the anodization electrolyte, and the porous region is thus formed in the area(s) of metal layer 8 where hard mask layer 10 is open.
Typically, a silicon dioxide masking layer is used for the hard mask 10. This choice is driven by several factors, including the availability of a silicon dioxide deposition process at medium/low temperature that is compatible with deposition above an aluminum-based stack, the availability of silicon dioxide patterning techniques with good selectivity on an underlying aluminum layer, the resistance of silicon dioxide to the anodization step, and the relatively low stress induced by an oxide layer.
However, while this choice is beneficial for the reasons mentioned above, it has an undesirable effect on pore formation in the region of the metal layer 8 adjacent to the hard mask. In effect, the use of silicon dioxide for the hard mask layer 10 weakens the anodization electrical field through the underlying metal layer 8 in the vicinity of the hard mask edge. This weakening of the anodization electrical field results in pores being not fully open and/or malformed at the periphery of the porous region. This issue is discussed below with reference to
Using known process steps and process conditions, regions in the metal layer 8 are anodized, converting aluminum in these regions to porous AAO 14 containing pores 16 extending all the way down to the anodization-stop layer 6, the pores being in a self-organized array, as illustrated in
The desired array of nanowires 18 is created by depositing metal into the pores 16 of the porous AAO matrix 14, as illustrated by
The removal of the porous AAO template 14 used to form the nanowires gives rise to significant topology (relief features), because a cavity is formed around the periphery of the nanowire structure. Considering
Furthermore, an over-etching may occur below the hard mask 10 that is used to delimit the region where the porous AAO region 14 is formed, creating a void V under the edge part of the hard mask 10 as can be seen in
The nanopillar structure may be produced with a view to integrating an electronic component into an integrated circuit. In such a case, the presence of the cavity in region Z2 is detrimental to the subsequent step of the manufacturing process, because it may prevent the next photolithographic step (even coating with photo-resist may become impossible). Also it is detrimental to continuity of superposed layers: i.e., it may result in discontinuity of metallic or insulating layers that are used superposed over the nanowire structure and which are used for forming the interconnections to the electronic component embedded using the nanowire structure. Accordingly, up to now it has been difficult to integrate, into integrated circuits or semiconductor products, electronic components that are embedded over an array of nanowires.
The present invention has been made in the light of the above problems.
The present invention provides a nanopillar array structure, a semiconductor product, a method of fabricating the nanowire array structure and a method of fabricating the semiconductor product which employ a level-sustaining hard mask to avoid formation of significant topological features that would hinder integration of a nanopillar array.
More particularly, the present invention provides a nanopillar array structure, comprising: a material layer comprising a well: the well having a sidewall, a well floor and a well mouth facing said well floor; an array of nanopillars located in said well and extending in the direction from the well floor towards the well mouth; and a hard mask overlying a peripheral region of said array and extending outwards to cover the remainder of the well mouth, wherein an aperture in said hard mask exposes the nanopillars disposed inwardly of said peripheral region.
The notion of overlaying, with regard to the hard mask, refers here to an at least partial superposition of the hard mask with direct contact on the nanopillars of said peripheral region, so as to close off the well mouth in this area.
Hence, in the nanowire array structure according to the present invention, the hard mask closes off the well mouth around the periphery of the array of nanopillars, so that only small topological features remain and the nanowire array structure is well-adapted for integration into an integrated circuit or electronic component. The hard mask may be considered to sustain the level of the topography.
The above-mentioned nanopillar array structure may comprise porous anodic oxide material at the periphery of the array of nanopillars and the nanopillars may be conductive nanowires. In such a case, the peripheral region may comprise peripheral nanowires disposed in pores of the porous anodic oxide material and the hard mask may overlie said peripheral nanowires disposed in the pores of the porous anodic oxide material. In some cases the porous anodic oxide material at the periphery of the array of nanopillars may comprise a first region, R2, where the pores contain nanowires and a second region, R3, outward of the first region and closer to the well sidewall, where the pores do not contain nanowires. The level-sustaining hard mask may overlie both of these regions of the porous anodic oxide material.
In the case where the level-sustaining hard mask overlies nanowires located in pores of a porous anodic oxide material there is increased support for the hard mask at the edge of the aperture(s) therein, reducing strain and reducing the risk of cracking.
The level-sustaining hard mask may be removed from the latter configuration, producing a nanowire array structure in which an array of released nanowires is surrounded by a first region containing porous anodic oxide with nanowires in the pores and the first region is surrounded by a second region consisting of porous anodic oxide having pores that do not contain nanowires.
In the above-mentioned nanopillar array structures the material layer may overlie a conductive layer and a surface of the conductive layer may (wholly or partially) define the well floor, and at least some of the nanopillars disposed inwardly of said peripheral region make contact with the conductive layer at the well floor. In this configuration, in the case where the nanopillars are made of electrically conductive material, electrical contact to the nanopillars may be made at the bottom of the well. This may allow an electronic component implemented using the nanopillar arrays structure to be connected to another component in an integrated circuit, resulting in a functional module.
The present invention further provides a semiconductor product comprising a nanopillar array structure as described above, and an electronic component constituted by one or more layers embedded in the array of nanopillars. The electronic component may be a capacitive component constituted, for example, by a metal-insulator-metal (MIM) stack embedded in the nanopillar array structure.
In the case where an electronic component is implemented by embedding layers in a nanopillar array of such a nanopillar array structure, the surface area of the layers embedded over the nanopillars is large and so high values of properties, such as capacitance, can be attained.
The above-mentioned semiconductor products may further comprise an interconnect structure comprising a plurality of nanowires located in respective pores of a region of porous anodic oxide material. Said region may be located in a well aside of the well in which is located the nanopillar array structure embedding the electric component, and said interconnect structure being further configured to provide electronic connection with a conductive layer underlying the material layer. Such an interconnect structure may extend from the back side of the product to the front side and may allow electrical contact to be made to two terminals at the same side of the semiconductor product. Advantageously, in the case where the electronic component layers are embedded in an array of nanowires, common process steps may be used to make the nanowires in the interconnect structure and the nanowires of the array, reducing the overall number of steps in the method of fabrication.
The present invention yet further provides a method of fabricating a nanopillar array structure, comprising: forming an array of nanopillars located in a well comprised in a material layer, the well having a sidewall, a well floor and a well mouth facing said well floor, the nanowires of said array extending in the direction from the well floor towards the well mouth; and forming a hard mask overlying a peripheral region of said array and extending outwards to cover the remainder of the well mouth, wherein an aperture in said hard mask exposes the nanopillars disposed inwardly of said peripheral region.
By forming the mask covering the well mouth region peripheral to the center of the nanopillar array, the method according to the invention prevents formation at the periphery of the array of large topographical features (large steps/height differences) which, otherwise, would arise and would hinder integration of the nanopillar array structure in a semiconductor product.
In the method of fabricating the nanopillar array structure: the forming of the array of nanopillars may comprise forming an array of nanowires in pores of a porous anodic oxide material; the forming of the hard mask may comprise forming a hard mask overlying the peripheral region of the array and extending outwards to cover the remainder of the well mouth, wherein an aperture in the hard mask exposes the nanowires disposed inwardly of said peripheral region; and after the forming of the hard mask, there may be a step of releasing the exposed nanowires (i.e. those disposed inwardly of said peripheral region), by selectively removing the porous anodic oxide material from between the exposed nanowires, leaving under the hard mask nanowires located in pores of the porous anodic oxide material.
By leaving under the hard mask some porous anodic oxide material whose pores contain nanowire material, the latter method assures better support for the hard mask, reducing the risk of breakage thereof.
The present invention still further provides a method of fabricating a semiconductor product comprising: fabrication of a nanopillar array structure by a method as described above; and embedding, in the array of nanopillars, one or more layers to form an electronic component. In this method, the embedding of one or more layers in the array of nanopillars may comprise forming a metal-insulator-metal (MIM) stack over the array of nanopillars to form a capacitive component. According to such a method the surface area of layers in the electronic component is large and the values of electrical properties, such as capacitance, can be increased.
Further features and advantages of the present invention will become apparent from the following description of certain embodiments thereof, given by way of illustration only, not limitation, with reference to the accompanying drawings in which:
Embodiments of the present invention address the existing deficiencies of the prior art by using a “level-sustaining” hard mask to prevent the formation, at the periphery of a nanopillar array, of cavities which cause topological features that might otherwise inhibit subsequent process steps when integrating the nanopillar array structure into a semiconductor product or integrated circuit.
In accordance with this feature, a method 300 of fabricating a nanopillar array structure according to an embodiment of the present invention will now be described with reference to the flow diagram of
The example described below with reference to
As in the method described above in connection with
The substrate 22 may be made, without limitation, of silicon, glass, or a polymer, and may be a raw (i.e., unprocessed) substrate or it may already be processed to a certain extent such that other electronic components are already formed thereon.
Conductive layer 24 is included in the structure in view of providing electrical contact at the bottom of the structure (as in Voiron's structure described in WO 2015/063420) and may be omitted if electrical contact is not needed underneath the nanowire array. Conductive layer 24 may include one or more metal layers including aluminum (Al), copper (Cu), silver (Ag), or aluminum copper (AlCu) combined or not with barrier metals such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). In one implementation, the conductive layer 24 is formed of an AlCu layer sandwiched between two TiN or TiTiN layers.
Barrier layer 26 is optional and serves to protect the conductive layer 24 (when present) during subsequent formation of the porous region. The barrier layer 26 has sufficient electrical conductivity to allow conduction between the conductive layer 24 and conductive material provided (subsequently) in pores of porous anodic oxide. The barrier layer 26 may be selected to act as an anodization stop layer for stopping the progression of anodization from reaching the conductive layer 24. In an embodiment, during the anodization, the barrier layer 26 may oxidize to form oxide plugs (not shown) at the bottom of the pores reaching the conductive layer 24. The oxide plugs may be etched away during a subsequent process step to allow electrical contact between the structure deposited into the pores and the conductive layer 24.
In another embodiment, the barrier layer 26 may also be selected so that it performs the function of shielding the conductive layer 24 from exposure to a halogen-based precursor that may be used in a subsequent process step. As such, the barrier layer 26 may be made of a metal that is resistant to halogen corrosion, such as W or Ti, for example.
The metal layer 28 may be made of an anodizable metal, such as aluminum for example.
Typically, a silicon dioxide masking layer is used for the anodization hard mask 30, but the invention is not limited to use of this material for the anodization hard mask. Other materials that may be used for the hard mask include, without limitation, silicon nitride, composite materials combining silicon oxide or nitride with a polymer, or a combination of any of those materials with a metallic barrier layer (e.g. made of tungsten). It is preferable to keep the thickness of the hard mask relatively low, so as to avoid formation of topological features but, generally, a minimum thickness is required (whose value depends on the anodization voltage). Typically, the thickness of the hard mask ranges from 0.5 to 1.5 μm.
Using known process steps and process conditions, regions in the metal layer 28 that are exposed from the anodization hard mask 30 are anodized (S302), converting metal of the metal layer 18 in these regions to porous anodic metal oxide 34 containing a self-organized array of pores 36 extending all the way down to the barrier layer 26, as illustrated in
As part of this step S302, the bottom-ends of the pores 36 are opened (for example by using a selective etching process) to expose the metal that is underneath the pores. If desired, the anodization hard mask 30 may be selectively removed after this operation. In this embodiment of the invention, the pore bottom ends are opened in view of an intended application of the nanowire array structure for the formation of a high-density capacitive component having bottom contact as in WO 2015/063420. However, in other applications it may be appropriate to keep the pore bottoms closed and, if desired, the metal layer for anodization 28 may be formed on the substrate 22, omitting layers 24 and 26.
The porous matrix is made of an anodic oxide having a plurality of pores that extend from a top surface of the porous region toward the substrate 22. As used herein, the term “anodic oxide” is a generic term referring to a material including anodic oxide or hydroxide, and possibly carbon and hydrogen byproducts resulting from the anodization. Typically, the pores in the central part of the porous material extend perpendicularly or substantially perpendicularly to the substrate 22. Pores at the periphery of the porous region may have uneven depths and/or diameters.
An array of nanowires 38 is created by providing metal (S303) into the pores 36 of the porous anodic oxide matrix 34, as illustrated in
A second hard mask 40 is formed (S304) over the anodization hard mask 30 (if the anodization hard mask 30 remains) and extends over an outer part of the region where the pores 36 contain metal, as shown in
The level-sustaining hard mask 40 may be made of a single layer made of insulating material (for example, SiO2 deposited by PECVD) or conductive material (for example, TiN deposited by PVD), or any combination of such layers. In the case where a selective etching process is used to release the nanowires, the material(s) used to make the level-sustaining hard mask 40 should be selected for resistance to the etching chemistry. Selective etching of AAO may use chemistry that partially etches silicon oxide. To overcome this issue, the level-sustaining hard mask 40 may be formed as a composite mask like, for example, SiOx+SiNx or SiOx+TiN.
It is preferable to set the thickness of the level-sustaining hard mask 40 to a low value so as to avoid formation of topological features. Typically, the thickness of the level-sustaining hard mask 40 is on the same order as that of the anodization hard mask (i.e. typically ranging from about 0.5 μm to about 1.5 μm).
In preferred embodiments of the invention, the level-sustaining hard mask 40 overlaps a peripheral region of the nanopillar array by a sufficient distance to prevent etching materials used in subsequent process steps from reaching zones of anodic oxide where the pores do not contain nanopillar material. The relevant overlap distance, O, may be determined by experimentation but, for example, in the case where the porous anodic oxide is made of a 5 μm thick layer of AAO, it has been found to be sufficient for a level-sustaining hard mask 40 made of SiO2 to extend a distance of 20 μm (inward) beyond the boundary of the nanopillar array. In the case of setting the overlap distance O to a value of this kind of magnitude, the level-sustaining hard mask 40 tends to cover the peripheral nanowires that may have morphology that deviates from the desired shape/geometry (notably, peripheral nanowires that are formed at locations where residual metal juts out below the anodic oxide).
Optionally, the height of the anodic oxide matrix 34 and the height of the metal in the pores 36 in the region exposed by the openings 42 in the second hard mask 40 can be trimmed (S305) to planarize the surface and to allow a controlled contact to be obtained. As can be seen from
The nanowires 38 are released (S306) by removing the porous anodic oxide matrix 34 (e.g. by a selective etching process, for instance a wet etching process), to leave a nanowire array structure 50 as illustrated in
After the selective removal of the anodic oxide material, in a central region R1 of the nanowire array structure there is a group of released nanowires. Around the periphery of the central region R1, there is a first region R2 which comprises anodic oxide matrix material 14 containing (unreleased) metal nanowires 38, and the level-sustaining hard mask 40 overlies this first region R2. In a second region R3, located around the periphery of the first region R2, there is a volume of porous anodic oxide material 34 in which no metal is present, and the level-sustaining hard mask 40 overlies this second region R3 also. Region R3 may comprise pores that are misshapen and/or misaligned and certain of these pores may be underlain by a ledge of unanodized metal of the metal layer 28.
The regular nanopillar structure present in region R1 can be used to embed capacitive structures, or other electronic components.
It can be seen from
The level-sustaining hard mask 40 should be in place prior to the releasing of the nanowires. Thus, it should be deposited after the nanowire material is put into the pores. In preferred embodiments of the invention, the level-sustaining hard mask 40 overlies the outer part of the region where the porous anodic oxide contains nanopillar material. In the case where the release of the nanowires is performed by wet etching, over-etching below the level-sustaining hard mask 40 would cause problems comparable to those of the related art if nothing were present underneath it for support. Additional support to the level-sustaining hard mask 40 may be provided by filling the pores 36 to overflowing in step S303 (i.e. forming an overflow region 38o as illustrated in
It should be understood that methods embodying the present invention, using a level-sustaining hard mask, may be generalized to other configurations. For example, they can be used in cases where the whole of metal layer 28 is to be anodized, i.e., where there is no need to use an anodization hard mask 30 to define selected local regions where porous anodic oxide is to be formed. In such a case, none of the initial metal forming the layer 28 remains after anodization, but only porous structure that is subsequently filled with nanowires. In that case, the level-sustaining hard mask 40 has one or more apertures 42 defining the area(s) where the nanowires should be selectively released (e.g. etched).
Furthermore, the method of
The nanowire array structure 50a of
As well as providing methods for fabricating nanowire array structures as described above, the present invention provides nanowire array structures produced by such methods, for example, the nanowire array structure 50 of
More generally, the level-sustaining hard mask used in embodiments of the invention can be used to planarize substantially any nanopillar structure (nanotubular, nanowire structure) located in a well, notably in cases where this well is delimited by a porous anodic oxide structure, or a porous structure filled with nanowires or any other suitable material (such as, for example, silicon or glass).
Thus, for example, the invention may be implemented in a generic nanopillar array structure such as that illustrated in
In the above-described generic case, the level-sustaining hard mask 140 covers the cavity/gap that otherwise would form at the transition between the nanowires and the external material delimiting the well 160.
The present invention still further provides semiconductor products which include: a nanopillar array structure embodying the invention, and an electronic component constituted by one or more layers embedded in the array of nanopillars.
In the example illustrated in
More particularly, in the example illustrated in
A method 1100 of fabricating the semiconductor product 200 of
The initial stages of the method 1100 of fabricating the semiconductor product 200 may be implemented similarly to the above-described steps of the method 300 of
Using known process steps and process conditions, regions in the metal layer 228 that are exposed from the anodization hard mask 230 are anodized (S1102), producing regions of porous anodic oxide 234 as illustrated in
The arrays of nanowires are created by providing metal (S1103) into the pores 236 of the porous anodic oxide templates 234, as illustrated in
A level-sustaining hard mask 240 is formed (S1104) over the anodization hard mask 230 (if the anodization hard mask 230 remains) and extends over the outer parts of the regions where the pores 236 contain metal, as shown in
In this example method, in the selected region where the overflowed metal 238o is exposed through the aperture 242 in the level-sustaining hard mask 240, the height of the anodic oxide matrix 234 and the height of the metal in the pores 236 is trimmed (S1105), which removes the overflow metal in the regions OR as illustrated in
The nanowires 238 to form array 265 are released (S1106) by selectively removing the porous anodic oxide matrix 234, for example, by a selective etching process (for instance, a wet etching process) through the aperture 242 in the mask 240, to leave a nanowire array structure 270 as illustrated in
An electronic component (here, a capacitive structure) is now formed using the nanowire array 265. More particularly, a layered structure is formed (S1107) on top of the hard mask 240, the layered structure being embedded in-between the nanowires of the array 265 as can be seen in
In the present example, the lower electrode of the capacitive structure (first M layer of a simple MIM stack) is constituted by the nanowires 238 themselves. In the present example, a layer 252 of dielectric material is formed over the nanowires 238 to constitute the dielectric of the capacitive structure (I layer of the MIM stack), and a layer 254 of conductive material is formed over the layer 252 so as to constitute the top electrode of the capacitive structure (second M layer of the MIM stack). Preferably, the layers 252 and 254 conform to the shape of the nanowire surface as closely as possible.
In one implementation, one or more conductive layers of the layered structure, which may provide an electrode for the layered structure, may be deposited using an Atomic Layer Deposition (ALD) process with a gaseous halogen-based (e.g., chlorine) precursor. For example, the conductive layer may be made of titanium nitride (TiN). One or more insulator layers of the layered structure, which may provide a dielectric for the layered structure, may be deposited using a process such as CVD or, more preferably, ALD. For example, the insulator layer may correspond to a structure that includes dielectric material (such as an oxide of Si, an oxide of Al, an oxide of Hf or an oxide of Zr) as a single component or as a laminated structure including a plurality of layers, or as a mixture obtained by co-deposition. Alternatively, the insulator layer may be formed of a material which, although insulative from the point of view of conduction of electrons, is an ionic conductor (e.g. LiPON).
A contact 268 to the top electrode of the capacitive structure 260 is made (S1108), for example by depositing and patterning a metallic layer to produce the structure illustrated in
In the method 1100 described above, the array of nanopillars 265 in the capacitive structure is formed of conductive wires and these constitute the lower capacitor electrode. However, if desired, or in a case where a capacitive structure is formed over nanopillars that are not (sufficiently) conductive, before formation of the dielectric layer 252 a layer of conductive material can be deposited over the nanopillars to form the lower capacitor electrode.
The method 1100 results in a semiconductor product 200 in which contacts 268, 288 to the top and bottom electrodes of the capacitive structure 260 are both available on the same side of the product (e.g. the top of the product as illustrated in
Furthermore, even in a case where both contacts are provided on the same side of the product, the wiring/connection from the back side to the front side may be implemented by means other than the structure 280 used in the product 200. For example,
In the semiconductor product 300 illustrated in
Incidentally, in the semiconductor product 300 illustrated in
In
In
In both of the cases illustrated in
Although the present invention has been described above with reference to certain specific embodiments, it will be understood that the invention is not limited by the particularities of the specific embodiments. Numerous variations, modifications and developments may be made in the above-described embodiments within the scope of the appended claims.
Number | Date | Country | Kind |
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21 306 536.0 | Nov 2021 | WO | international |