Patent Application
20240203482
Embodiments of the present disclosure relate generally to memory devices. More specifically, embodiments of the present disclosure relate to monitoring operations of a memory device.
Generally, a computing system may include electronic devices that, in operation, communicate information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM) device, a ferroelectric random-access memory (FeRAM) device, another random-access memory (RAM) device, and/or a hybrid device that incorporates more than one type of RAM. In this manner, the processor may communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed, by the processor, and/or store data output from the processor.
The memory devices utilize sense amplifiers during read operations. Specifically, the read circuitry of the memory device uses the sense amplifiers to receive low voltage (e.g., low differential) signals and amplify relatively small voltage differences to enable the memory device to interpret the data properly. However, some sense amplifiers may consume excess resources (e.g., power and/or area). Furthermore, some sense amplifiers may insufficiently amplify or amplify the low voltages too slowly.
Embodiments of the present disclosure may be directed to one or more of the problems set forth above.
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
As previously discussed, a memory device uses sense amplifiers to receive low voltage (e.g., low differential) signals and to amplify relatively small voltage differences to enable the memory device to interpret the data properly. However, some sense amplifiers may suffer from output drive degradation as designs have been modified over time (e.g., reduced in size to meet array efficiency performance targets).
Indeed, as memories shrink, cell capacitance decreases due to an associated memory cell area decreasing and methods may have increasingly relied on both n-channel and p-channel compensation. A sense amplifier that uses a combined n-channel and p-channel compensation may experience several disadvantages. For example, digit line capacitance may increase and sense amplifier circuitry may decrease in footprint. As sense amplifiers decrease in size, differential voltages on the digit lines may reduce, where the differential voltages may be used to amplify inputs to the sense amplifier. Sense amplifier mis-match and/or the reduction of the differential voltages may reduce an overall read window used during a sensing operation. Furthermore, n-channel and p-channel compensation circuits may be more sensitive to overcompensation from unintentional timing variations and some generations of memory devices may be capped at how great of a high reference voltage may be used. Thus, it may be desired to increase a drive strength of a sense amplifier without also increasing footprint, which may be achievable through an n-channel-centric compensation scheme.
Keeping the foregoing in mind, negative source voltage pre-sense and negative voltage write back systems and methods are described herein that utilize n-channel compensation via the sense amplifier as opposed to a combination of n-channel and p-channel compensation. The p-channel cross-coupled circuitry of the sense amplifier may become a high reference voltage placeholder as opposed to an active portion of the compensation. Due to this, the n-channel-centric threshold voltage compensation (VtC) may result in a voltage closer to a threshold voltage of the sense amplifier, which decreases a gain of the sense amplifier used to amplify sensed signals. Thus, a low reference voltage may be lowered to increase the drive capacity of the sense amplifier to preserve a desired gain of the sense amplifier (e.g., increase the decreased gain).
To elaborate, during the associated negative source voltage pre-sense and negative voltage write back operations, a threshold voltage compensation (VtC) operation may involve reducing a digit line voltage level, which may increase the percentage of VtC compensation (e.g., increase a percent able to be compensated). However, the lower EQ digit line voltage may cause n-channel sense amplifier output drive degradation. To reduce this degradation, a negative source voltage may be pulsed during a presense operation to keep a gate-source terminal voltage (Vgs) of the sense amplifier suitably above a threshold level. At the start of the precharge cycle, the presense n-channel may turn on to bring a digit line or a reference digit line to an adjustable negative voltage level (e.g., from 0 volts (V)). In turn, this may provide a negative voltage level to the cell capacitance before the word lines turn off. Thus, by modifying sense amplifier systems and methods to enable pulsing the negative source voltage to keep the Vgs of the sense amplifier above a threshold level, the differential voltage used by the sense amplifier may be expanded to cause a suitable driving amplification. By doing so, a driver operation of the sense amplifier may increase without increasing a high reference voltage used to amplify signals.
Turning now to the figures,
The memory device 10 may include a number of memory banks 12. The memory banks 12 may be DDR5 SDRAM memory banks, for instance. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) that are arranged on dual inline memory modules (DIMMS). Each DIMM may include a number of SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form bank groups. For instance, for an 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged into 8 bank groups, each bank group including 2 memory banks. For a 16 Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12, arranged into 8 bank groups, each bank group including 4 memory banks, for instance. Various other configurations, organization and sizes of the memory banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system.
The memory banks 12 and/or bank control blocks 32 include sense amplifiers 14. As previously noted, sense amplifiers 14 are used by the memory device 10 during read operations. Specifically, read circuitry of the memory device 10 utilizes the sense amplifiers 14 to receive low voltage (e.g., low differential) signals from the memory cells of the memory banks 12 and amplifies the small voltage differences to enable the memory device 10 to interpret the data properly.
The memory device 10 may include a command interface 16 and an input/output (I/O) interface 18. The command interface 16 is configured to provide a number of signals (e.g., signals 8) from an external (e.g., host) device (not shown), such as a processor or controller. The processor or controller may provide various signals 8 to the memory device 10 to facilitate the transmission and receipt of data to be written to or read from the memory device 10.
As will be appreciated, the command interface 16 may include a number of circuits, such as a clock input circuit 20 and a command address input circuit 22, for instance, to ensure proper handling of the signals 8. The command interface 16 may receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, the true clock signal Clk_t and the complementary or bar clock signal Clk_c. The positive clock edge for DDR refers to the point where the rising true clock signal Clk_t crosses the falling bar clock signal Clk_c, while the negative clock edge indicates that transition of the falling true clock signal Clk_t and the rising of the bar clock signal Clk_c. Commands (e.g., read command, write command, etc.) are typically entered on the positive edges of the clock signal and data is transmitted or received on both the positive and negative clock edges.
The clock input circuit 20 receives the true clock signal Clk_t and the bar clock signal Clk_c and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 24. The DLL circuit 24 generates a phase controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase controlled internal clock signal LCLK is supplied to the I/O interface 18, for instance, and is used as a timing signal for determining an output timing of read data. In some embodiments, the clock input circuit 20 may include circuitry that splits the clock signal into multiple (e.g., 4) phases. The clock input circuit 20 may also include phase detection circuitry to detect which phase receives a first pulse when sets of pulses occur too frequently to enable the clock input circuit 20 to reset between sets of pulses.
The internal clock signal(s)/phases CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For instance, the internal clock signal CLK may be provided to a command decoder 26. The command decoder 26 may receive command signals from a command bus 28 and may decode the command signals to provide various internal commands. For instance, the command decoder 26 may provide command signals to the DLL circuit 24 to coordinate generation of the phase controlled internal clock signal LCLK. The phase controlled internal clock signal LCLK may be used to clock data through the I/O interface 18, for instance.
Further, the command decoder 26 may decode commands, such as read commands, write commands, mode-register set commands, activate commands, or the like, and provide access to a particular memory bank 12 corresponding to the command, via a bus path 30. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes the bank control block 32 which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks 12.
The memory device 10 executes operations, such as read commands and write commands, based on the command/address signals received from an external device, such as a processor. In one embodiment, the command/address bus may be a 14-bit bus to accommodate the command/address signals (CA<13:0>). The command/address signals are clocked to the command interface 16 using the clock signals (Clk_t and Clk_c). The command interface may include a command address input circuit 22, which is configured to receive and transmit the commands to provide access to the memory banks 12, through the command decoder 26, for instance. In addition, the command interface 16 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to specific memory banks 12 within the memory device 10 is encoded on the CA<13:0> bus with the commands.
In addition, the command interface 16 may be configured to receive a number of other command signals. For instance, a command/address on die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) may be used to reset the command interface 16, status registers, state machines and the like, during power-up for instance. The command interface 16 may also receive a command/address invert (CAI) signal which may be provided to invert the state of command/address signals CA<13:0> on the command/address bus, for instance, depending on the command/address routing for the particular memory device 10. A mirror (MIR) signal may also be provided to facilitate a mirror function. The MIR signal may be used to multiplex signals so that they can be swapped for enabling certain routing of signals to the memory device 10, based on the configuration of multiple memory devices in a particular application. Various signals to facilitate testing of the memory device 10, such as the test enable (TEN) signal, may be provided, as well. For instance, the TEN signal may be used to place the memory device 10 into a test mode for connectivity testing.
The command interface 16 may also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For instance, an alert signal (ALERT_n) may be transmitted from the memory device 10 if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. Further, the bus and pin for transmitting the alert signal (ALERT_n) from the memory device 10 may be used as an input pin during certain operations, such as the connectivity test mode executed using the TEN signal, as described above.
Data may be sent to and from the memory device 10, utilizing the command and clocking signals discussed above, by transmitting and receiving data signals 34 through the I/O interface 18. More specifically, the data may be sent to or retrieved from the memory banks 12 over datapath 36, which includes a plurality of bi-directional data buses. Data IO signals, generally referred to as DQ signals, are generally transmitted and received in one or more bi-directional data busses. For certain memory devices, such as a DDR5 SDRAM memory device, the IO signals may be divided into upper and lower bytes. For instance, for a x16 memory device, the IO signals may be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to upper and lower bytes of the data signals, for instance.
To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices may utilize data strobe signals, generally referred to as DQS signals. The DQS signals are driven by the external processor or controller sending the data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For read commands, the DQS signals are effectively additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. As with the clock signals (Clk_t and Clk_c), the DQS signals may be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For certain memory devices, such as a DDR5 SDRAM memory device, the differential pairs of DQS signals may be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to upper and lower bytes of data sent to and from the memory device 10, for instance.
An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the I/O interface 18. The ZQ calibration signal may be provided to a reference pin and used to tune output drivers and ODT values by adjusting pull-up and pull-down resistors of the memory device 10 across changes in process, voltage and temperature (PVT) values. Because PVT characteristics may impact the ZQ resistor values, the ZQ calibration signal may be provided to the ZQ reference pin to be used to adjust the resistance to calibrate the input impedance to known values. As will be appreciated, a precision resistor is generally coupled between the ZQ pin on the memory device 10 and GND/VSS external to the memory device 10. This resistor acts as a reference for adjusting internal ODT and drive strength of the IO pins.
In addition, a loopback data signal (LBDQ) and loopback strobe signal (LBDQS) may be provided to the memory device 10 through the I/O interface 18. The loopback data signal and the loopback strobe signal may be used during a test or debugging phase to set the memory device 10 into a mode wherein signals are looped back through the memory device 10 through the same pin. For instance, the loopback signal may be used to set the memory device 10 to test the data output (DQ) of the memory device 10. Loopback may include both LBDQ and LBDQS or possibly just a loopback data pin. This is generally intended to be used to monitor the data captured by the memory device 10 at the I/O interface 18. LBDQ may be indicative of a target memory device, such as memory device 10, data operation and, thus, may be analyzed to monitor (e.g., debug and/or perform diagnostics on) data operation of the target memory device. Additionally, LBDQS may be indicative of a target memory device, such as memory device 10, strobe operation (e.g., clocking of data operation) and, thus, may be analyzed to monitor (e.g., debug and/or perform diagnostics on) strobe operation of the target memory device.
As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operations and configurations), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing temperatures of the memory device 10), etc., may also be incorporated into the memory device 10. Accordingly, it should be understood that the block diagram of
As illustrated, the sense amplifier 50 receives an array voltage (VARY) 52. The sense amplifier 50 also includes transistor 54 that receives a control signal PSA1_F 56 at the respective gates of the transistor 54 to control generation of a p-channel activate signal PCS (ACT) 58 as a local voltage. The PCS (ACT) 58 activates the sense amplifier 50 by providing an operating voltage to the sense amplifier 50.
The sense amplifier 50 also receives an isolation signal (ISO) 60 via isolating transistors (transistor 62, transistor 64). The sense amplifier 50 includes transistors 62 and 64 that couple and/or decouple internal circuitry of the sense amplifier 50 from respective digit lines 66 and 68 based on the ISO 60. The digit line 66 may be indicative of the data in the memory cell as a “bit line true” signal (BLT) while the digit line 68 may be opposite as a complementary “bit line bar/false” signal (BLB). Thus, the digit lines 66 and 68 may be complementary pairs and there may be multiple pairs of digit lines associated with the memory device 10. Each digit line 66, 68, such as each digit line 66, 68 of each of the multiple pairs of digit lines associated with the memory device 10, may be coupled to respective memory cells of the memory device 10.
The sense amplifier 50 also includes a cross-coupled p-channel metal oxide semiconductor device (CCP) 70 (e.g., cross-coupled PMOS transistors coupled to a supply voltage). Gut nodes 72 and 74 are each coupled to a first terminal (e.g., gate) of a respective one of the P-channel MOSFETs of the CCP 70 and to a second terminal (e.g., drain) of the other respective P-channel MOSFET of the CCP 70.
The sense amplifier 50 further includes a transistor 76 that is used to equalize the voltages of the gut nodes 72 and 74 based on an equalization signal (EQ) 78 to an equalization transistor (e.g., transistor 76). Specifically, the gut node 72 may be discharged/charged to a bit line precharge voltage (VBLP) when the EQ 78 is asserted. The ISO 60 controls coupling of the gut node 72 to and decoupling of the gut node 72 from the digit line 66 via the transistor 62. Similarly, the ISO 60 controls coupling of the gut node 74 to and decoupling of the gut node 74 from the digit line 68 via the transistor 64.
The sense amplifier 50 further includes n-channel MOSFETs (NMOS) transistors 80, 82, 84, and 86. The n-channel transistors 86 and 82 both receive a local bit line compensation enable signal (LBLCP) 88 at their respective gates. Another terminal (e.g., source) of the NMOS transistor 86 is coupled to the digit line 68 while another terminal (e.g., source) of the NMOS transistor 82 is coupled to the digit line 66. The third terminal of the NMOS transistor 86 is coupled to a terminal (e.g., source) of the NMOS transistor 80, and the third terminal of the NMOS transistor 82 is coupled to a terminal (e.g., source) of the NMOS transistor 84. The gate of the NMOS transistor 80 is coupled to the digit line 68, and the gate of the NMOS transistor 84 is coupled to the digit line 66. The third terminals of the transistors 80 and 84 are coupled to an n-channel strobe (NCS) 90. The sense amplifier 50 receives an n-channel sense amplifier signal (NSA1) 92 to control a transistor 94 that selectively couples and decouples the NCS 90 from ground.
The illustrated embodiment of the sense amplifier 50 senses low voltage data and amplifies the low voltage data, but the sense amplifier 50 may have some drawbacks. Specifically, the local generation of the PCS (ACT) 58 from the VARY 52 may be problematic. Although VARY 52 may be a well-regulated voltage, there may be a voltage drop through the transistor 54 (and any other circuitry) during low voltage operation that may cause the PCS (ACT) 58 to improperly fluctuate. For example, VARY 52 may be regulated from VDD and may be as low as 0.8V for LPDRAM during an Activate cycle. This low voltage may correspond to a voltage drop through transistor 54 that could be as high as 0.1V, resulting in the PCS (ACT) 58 level being as low as 0.7V that may greatly degrade the activate cycle operation. By removing the local generation of the PCS (ACT) 58, such voltage drops during low voltage operation may be avoided. Furthermore, the limited amount of amplification in the sense amplifier 50 causes the length of the digit lines 66 and 68 to be limited and/or the amount of noise relatively significant.
To address the issues with the sense amplifier 50, an alternative embodiment of the sense amplifiers 14 may be used. For instance,
To exemplify the differences, the sense amplifier 50 may use a low voltage (VSS) or ground voltage of approximately 0 volts (V) (e.g., within a 2% tolerance, within a 1% tolerance, any suitable tolerance), a mid-voltage level of approximately 0.5 volts (V) (e.g., within a 2% tolerance, within a 1% tolerance, any suitable tolerance), and a high voltage (VARY) level of approximately 1.0 volts (V) (e.g., within a 2% tolerance, within a 1% tolerance, any suitable tolerance). The sense amplifier 110 is similar to the sense amplifier 50 except that the sense amplifier 110 is configured differently in that it does not connect the gut node 72 to VBLP via the transistor 76. The sense amplifier 110 continues to locally generate the PCS (ACT) 58 but does so based on a voltage (VCCL) 112 as opposed to the VARY 52. Moreover, the sense amplifier 110 includes an additional low voltage (VBBSA) 114 coupled to the transistor 118. The VBBSA 114 may be a negative voltage (e.g., negative voltage source). However, in certain systems, the VBBSA 114 may be an internally generated voltage used when a corresponding sensing amplifier row is enabled to allow sensing to occur. Thus, the VBBSA 114 may sometimes be reserved for use by transistors in the sense amplifier 110, as opposed to being a global negative voltage. The sense amplifier 110 also includes a transistor 122 that receives a control signal, PSA2_F 124. These changes enable the sense amplifier 110 to use a relatively lower voltage as a low reference voltage (e.g., VBBSA 114) of approximately −0.2V (e.g., within a 2% tolerance, within a 1% tolerance, any suitable tolerance), a mid-voltage level of approximately 0.5 volts (V) (e.g., within a 2% tolerance, within a 1% tolerance, any suitable tolerance), and a high voltage (VARY) level of approximately 1.0 volts (V) (e.g., within a 2% tolerance, within a 1% tolerance, any suitable tolerance). By using a lower low reference voltage, the drive strength of the sense amplifier 110 may be desirably increased without increasing a footprint size.
Indeed, as opposed to using a single low reference voltage throughout a sensing operation, the sense amplifier 110 uses a first low reference voltage (VBBSA) 114 and a second low reference voltage (VSS) 116 during the sensing operation. The sense amplifier 110 may be coupled to the VBBSA 114 via transistor 118 in response to a control signal, NSA2 120. The VBBSA 114 may be a negative voltage and may enable the sense amplifier 110 to have a suitably large gain relative. The improved driving characteristics of the sensing amplifier 100 may allow continued use of the reduced sense amplifier size due to the sense amplifier 110 producing reliable sensing outputs.
To help explain the operation of the sense amplifier 110 of
Referring now to
This first stage 154 may correspond to a low-voltage threshold voltage (Vt) compensation stage with a gut node equalization. To elaborate, this stage begins with the LBLCP 88 being asserted along with the NSA1 92. During this stage, the ISO 60 is off/de-asserted thereby causing the transistor 64 to act as an open switch disconnecting the digit line 68 and the gut node 74. The off state of the ISO 60 also causes the transistor 62 to act as an open switch to disconnect the digit line 66 from the gut node 72. The EQ 78 is also deasserted at the beginning of the first stage 154 causing the transistor 76 to function as an open switch, which decouples the gut nodes 72 and 74 from each other. The LBLCP 88 and the NSA1 92 may be on/asserted for most of the time period of this first stage causing transistors 94, 86, and 82 to act as a closed switch and may be deasserted by the end of the first stage 154 (which is shown in
The assertion of LBLCP 88 causes the gut node 72 to be coupled to two terminals (e.g., gate and source) of the NMOS transistor 80. This connection is made because the LBLCP 88 being asserted causes the NMOS transistor 86 to act as a closed switch between the two terminals of the NMOS transistor 80. Similarly, the assertion of the LBLCP 88 causes the gut node 74 to be coupled to two terminals (e.g., gate and source) of the NMOS transistor 84. This connection is made because the assertion of the LBLCP 88 causes the NMOS transistor 80 to act as a closed switch between the two terminals of the NMOS transistor 84. Moreover, the connection of the third terminals (e.g., drain) of the NMOS transistors 80 and 84 is made to ground through the transistor 94 acting as a closed switch due to the assertion of the NSA1 92. Due to these connections, the transistors 80 and 84 act as diodes to enable threshold voltage compensation using the charge on the gut nodes 72 and 74 from the previous cycle to set the charge at the gut nodes 72 and 74 to the threshold voltages of the respective transistors 80 and 84.
Referring back to
The second stage 156 of
Referring back to
Referring now to
Referring back to
The fourth stage 160 corresponds to
Referring back to
Referring now to
At block 182, the memory controller may receive an instruction to perform a sensing operation via a sense amplifier 110. The instruction may be generated by a host device communicatively coupled to the memory controller and/or the memory device. The instruction may correspond to a read operation associated with at least a portion of the memory bank 12.
At block 184, the memory controller may perform a precharge operation at least in part by sending NSA2 120 (e.g., a first control signal) to the transistor 118 (e.g., a first transistor) coupled between the sense amplifier 110 and VBBSA 114 (e.g., a first reference voltage) to turn on the transistor 118 (e.g., first transistor). The precharge operation may correspond to a precharging operation of a previous read operation (e.g., previous sense amplifier 110 operation). The VBBSA 114 may include a voltage level lower than VSS 116 (e.g., a second reference voltage). For example, VBBSA 114 may be a voltage between −0.25 volts (V) and −0.17V and/or a voltage less than 0V. As another example, VBBSA 114 may be a voltage between 1.1 volts (V) and 1.3V less than a high reference voltage of the sense amplifier 110.
At block 186, the memory controller may determine that an n-channel node (e.g., node 212 of
At block 190, the memory controller may perform a voltage threshold compensation operation by transmitting NSA1 92 (e.g., a third control signal) to turn on the transistor 94 (e.g., a second transistor) coupled between the sense amplifier 110 and VSS 116 (e.g., a second reference voltage without turning on the first transistor). Performing the voltage threshold compensation may involve the memory controller not sending a fourth control signal to turn on the transistor 118. Operations of block 190 may correspond to operations of the first stage 154 of
At block 192, the memory controller may perform a presense operation at least in part by pulsing a NSA2 120 (e.g., fourth control signal) to turn on the transistor 118 for a duration of time corresponding to a desired discharging of a gut node 72 coupled to digit line 68 associated with the sense amplifier 110. Operations of block 192 may correspond to the third stage 158 of
Technical effects caused by systems and methods of the present disclosure may include improving a differential voltage window at latch time of a sense amplifier. Indeed, relatively smaller memory cell capacitances, relatively high memory cell leakages, and an increased likelihood for increased noise budget in 3DDRAM technologies may reduce a sensing time window used by a sensing amplifier. By using n-channel centric threshold voltage compensation (VtC) operations, negative gut EQ presense operations may use digit noise budget to pre-amplify a gut node to improve a differential voltage window at the latch time of the sense amplifier. In addition, n-channel centric VtC operations with negative source presense may improve or alleviate n-channel amplifier drive degradation. These systems and methods may further improve threshold voltage (Vt) compensation percentages otherwise associated with relatively weak p-channel PCS (ACT) drive signal during the VtC compensation time. Additionally, negative digit line write back operations at the beginning of a precharge time may help to widen an operating voltage of a memory cell, which may help improve digit line differential signals with a relatively smaller cell capacitance.
While the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the following appended claims.
The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).
This application claims priority to U.S. Provisional Application No. 63/433,526, filed Dec. 19, 2022, entitled “NEGATIVE PULL-DOWN VOLTAGE IN A SENSE AMPLIFIER,” the disclosure of which is incorporated by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63433526 | Dec 2022 | US |
