Patent Application
20150166332
This application relates to the field of electromechanical systems and in particular that of MEMS (Micro-Electro-Mechanical Systems) or NEMS (Nano Electro-Mechanical Systems).
It provides a feedback device provided with (a) programmable delay module(s) enabling a MEMS or NEMS component to be oscillated and/or kept in oscillation.
The controlling device according to the invention is adapted to a wide range of NEMS or MEMS.
Among the existing NEMS devices, those called “Cross-Beam” are equipped with a movable element 15, which may for example be in the form of a nanoscale beam or a bar designed to vibrate or oscillate (
This movable element 15 is moved through electrostatic actuating means comprising a connection network on which an excitation signal is applied, the connection network terminating in one or more pads 21, 22 arranged in proximity of the movable element 15.
The excitation signal is generally a signal having a high frequency or a frequency higher than 100 kHz.
Detecting means, which can be for example piezoresistive sensing means comprising piezoresistive gauges enable a detection of the electrical signal generated by the movements of the movable element 15 to be carried out.
These detecting means may comprise a pad 28 connected to a conductive line for extracting a detection signal reflecting a movement of the movable element.
The device may also comprise bias means provided with pads 24, 25, on which a bias signal, generally in the form of a DC voltage, is applied.
The document “A High Gain-Bandwidth Product Transimpedance Amplifier for MEMS-Based Oscillators” Nabki et al., IEEE 2008, for example, discloses a MEMS resonator provided with a movable element in the form of a beam and arranged in a feedback loop provided with a transimpedance amplifier.
The document “Fully Monolithic CMOS nickel micromechanical resonator oscillator”, Huang et al. MEMS 2008 provides a MEMS device provided with a movable element in the form of movable plates linked together through beams and which device may be integrated into a feedback loop comprising an adjustable gain transresistor amplifier.
The document “CMOS MEMS Oscillator for Gas Chemical Detection,” Bedair et al., IEEE 2004, discloses in turn a microelectronic device provided with a MEMS resonator and a pre-amplifier, a phase compensation amplifier and a spectrum analyzer forming a closed loop system.
In order to oscillate and keep oscillating a NEMS or MEMS device, conditions called “Barkhausen” conditions of gain and phase shift should preferably be met.
The document U.S. 2010/0308931 discloses a MEMS controlling device as a feedback loop provided with an analog circuit for inducing a delay or phase shift, this phase shift being adjustable.
The phase shift generated by this circuit can in turn be variable depending on the oscillation frequencies of the MEMS. With such a control circuit, for high frequencies, the analog delay circuit is likely to introduce a significant attenuation of the signal for exciting the MEMS.
The document “Digital Oscillator Circuit using Synchronous Pulse Driving” of Roubicek et al., IEEE 2008 provides a controlling device of an electromechanical system with feedback loop in which digitizing is implemented, the device being provided with a means for introducing a phase shift.
The problem of implementing an improved MEMS microelectronic device capable of oscillating in a wide range of used frequencies and resonators occurs.
The present invention first relates to a device for controlling a MEMS micro-electro-mechanical system or NEMS nano-electromechanical system comprising a feedback loop, provided with:
The digital signal output from the digitizing means and the signal that is fed back to the input of the electromechanical system are thus advantageously of the same frequency and phase-shifted by a phase shift corresponding to the delay programmed by means of the delay module.
The programmable delay module is configured such that to induce a delay to the digital signal, it does not require, in contrast to the devices according to the prior art, to perform a frequency synthesis.
The digitizing means can be in the form of a comparator.
To fulfil the oscillation conditions of the MEMS or NEMS, and overcome the phase shift introduced by the different elements of a feedback loop, a known and controlled phase shift is implemented.
Digitizing said given signal that is desired to be delayed, and said delay module enable a phase shift to be introduced without attenuating this signal and regardless of the signal frequency.
Thus, the controlling device according to the invention can be adapted to a wide range of MEMS and/or NEMS.
According to a first excitation mode of the MEMS or NEMS, the delayed digital signals may be a first signal of a frequency equal to the resonance frequency of the MEMS or NEMS and a second signal of a frequency equal to the resonance frequency of the MEMS or NEMS, the first signal and the second signal being preferably of the same amplitude and being in opposite phases.
The programmable delay module may comprise:
The programmable delay module may further comprise means forming a phase-locked loop,
the means for delivering a plurality of phase-shifted signals comprising a voltage-controlled delay line having a first input receiving said digital signal and delivering a feedback signal, the control voltage of the delay line depending on a difference between said digital signal and said feedback signal.
The delay introduced by the delay module is thus a locked delay independent of the voltages and amplitude of the inputted signal thereof. The controlling device may further comprise: means for measuring frequency of said digital signal.
The controlling device may further include a configuration selecting module having a first input connected to the digitizing means and a second input, the configuration selecting module being also provided with a first output and a second output connected to the programmable delay module.
The configuration selecting module can be provided to assume:
The configuration selecting module can thus enable the feedback loop to be placed in an open loop configuration, wherein the measurements of delay introduced by the elements of the controlling device can be made, and in another, closed loop, configuration.
The configuration selecting module can be provided such that:
Tp
(ET/ST)-config1
=Tp
(CS/ST)-config2
+Tp
(ET/CE)-config2 and Tp(CE/CS)-config1≈0 or Tp(CE/CS)-config1<<Tp(CS/ST)-config2 and Tp(CE/CS)-config1<<Tp(ET/CE)-config2,
with
Tp(ST/ET)-config1: the propagation time of a signal in said first configuration between said second input and said first output,
Tp(CS/ST)-config2: the propagation time of a signal in said second configuration between the first input and the first output,
and Tp(ET/CE)-config2: the propagation time of a signal in said second configuration between the second input and the second output, Tp(CS/CE)-config1 the propagation time of a signal in said first configuration between the first input and the second output.
By Tp(CE/CS)-config1<<Tp(CS/ST)-config2 it is meant that Tp(CE/CS)-config1 is at least ten times or at least a hundred times lower than Tp(CS/ST)-config2.
And by Tp(CE/CS)-config1<<Tp(ET/CE)-config2 it is meant that Tp(CE/CS)-config1 is at least ten times or a hundred times lower than Tp(ET/CE)-config2.
Tp(CS/ST)-config2 and Tp(ET/CE)-config2 can be for example in the order of several nanoseconds.
Tp(CE/CS)-config1 can be for example in the order of several picoseconds, for example in the order of one or several hundreds of picoseconds.
The controlling device may further comprise:
said given delay being selected such that: n/(Fr)−(Tp(ET/ST)-config1−Tesbo), where n is an integer and Fr the resonance frequency of the MEMS or NEMS.
The controlling device may further comprise: an output interface provided with charge and/or voltage level adapter means at the output of the programmable delay module.
The present invention also relates to a microelectronic device comprising at least one MEMS or at least one NEMS and a controlling device as previously defined.
The present invention will be better understood upon reading the description of exemplary embodiments given purely by way of indicative and non-limiting example, in reference to the accompanying drawings in which:
A first exemplary controlling device, implemented according to the invention, is illustrated in
This controlling device enables an excitation of a MEMS or NEMS to be performed, for example a MEMS or NEMS resonator, in order to oscillate it and/or keep it in oscillation.
The controlling device can be in the form of a feedback loop first comprising a first stage 120 or a module 120 comprising a gain/filtering chain which can be analog and enable a signal SA from a MEMS or NEMS resonator 110 to be amplified.
This chain can be made of a differential amplifier or a transimpedance amplifier or TIA (transimpedance) amplifier and/or one or more low-pass and/or high-pass filters.
An exemplary embodiment of the gain/filtering chain of the first stage 120 is given in
An amplified signal SB thus comes from the first stage 120 and is digitized using digitizing means comprising a voltage comparator 130 which is for example asynchronous.
An exemplary embodiment of such a comparator 130 is given in
This comparator 130 is referred to as “asynchronous” insofar as it is not sampled by a reference clock. The comparator 130 may comprise a differential amplifier with inputs E+ and E− made of transistors M1, M2, M3, M4, M8, M5. The comparator 130 may also be made of a gain stage comprising transistors M7, M6.
The gain stage is followed by a series of inverters 131, 133, 135 for performing a charge matching with the next stage of the controlling device.
At the output of the digitizing means 130, a digital signal Sc is delivered. This digital signal Sc can be used by a digital block 150 for performing a frequency measurement of the digital signal Sc.
An exemplary embodiment of a frequency measurement block 150 is illustrated in
The frequency measurement block 150 may be formed by two main modules 153, 155 that can be produced by using synchronous counters.
A first module 155 of the block 150 is a two to the N divider.
On a first input E2 of the first module 155, a reference signal Href is at a reference frequency FREF for example a value of 1024 MHz.
An output S2 of this block is a signal Smes of a period Tmes which may be for example 2048 μs and have for example a high level of duration in the order of 1024 μs when N=21.
An AND gate 151 receives the digital signal Sc on a first input and the signal Smes from the first module 155 on a second input. This AND gate 151 delivers a signal to an input E1 of a second module 153 of the block 150.
The second module 153 of the block 150 is made of a synchronous counter, for example triggered on the rising edge, that is to say, at each rising edge applied to its input E1, the value stored in the counter is incremented by one unit.
Another input RAZ of the second module 153 is used to reset the value of the counter. An output S1 enables the current counter value to be delivered.
Timing diagrams C10, C20, C30, C40, respectively representative of the reset signal RAZ of the second module 153, of the output signal Smes of the first module 155, of the output signal of the AND gate delivered at the input E1 of the second module 153, of the data signal at the output of the second module 153 are given in
The measurement can be carried out in 3 phases:
In a first phase called “initialization”, the synchronous counter 153 is initialized via the reset signal RAZ.
In a second phase called “counting”: when the signal Smes at the output of the first module 155 is in a high state or equal to a logical level ‘1’, at each rising edge of the digital signal, the value of the counting implemented by the second module 153 is incremented.
In a third phase of transfer and computation: when the signal Smes at the output of the first module 155 returns to a low state or a logical level ‘0’, the value M of the counter 153 is transferred to a computing unit;
the computation of an average period Txm of a digital signal can be performed using a formula: Txm=(0.5*Tmes)/M.
For example, with a value of reference frequency FREF of the clock signal of 1024 MHz, for N=21, the period of Tmes is 2048 μs and the duration of the high level of 1024 μs.
For example for M=20000, Txm=0.5*2048 μs/20000=51.2 ns is computed.
For M=20001, Txm=0.5*2048 μs/20001=51.19744 ns is computed.
A periodic or permanent measurement can be implemented. The result of this measurement can be stored in a memory.
The digital signal Sc is also injected into a module 170 forming a programmable delay cell for example to generate one or more digital output signals SD1, SD2 with a known delay with respect to the input signal Sc, this delay being adjustable or programmable, and selected from a plurality of predetermined delays.
The delay introduced in the feedback loop enables to compensate for that generated by the other elements of the loop and deliver an excitation signal or signals to the resonator according to a determined phase difference fulfilling the oscillation conditions of the resonator.
The module 170 enables a delay independent of the frequency of the signal detected at the output of the MEMS or NEMS to be induced. The module 170 also enables a delay without attenuation of the signal entering this module to be induced.
The programmable delay module 170 may be formed using a DLL (“Delay Locked Loop”) architecture such as that shown for example in
In this exemplary embodiment, the module 170 includes a phase comparator 172, a charge pump 174, a voltage-controlled delay line 177 and a decoder 179.
The phase comparator 172, when activated by a signal EN compares the input signal SC acting as a reference signal and a signal Sdly corresponding to the last signal generated at the end of the delay line 177. The phase comparator 172 delivers two logical signals UP and DOWN, which are the image of the phase shift between the two signals SC and Sdly to be synchronized. When the two signals Sc and Sdly are not yet synchronized, the logical signals UP and DOWN have different durations. When the two signals SC and Sdly are in phase, the loop is locked.
The duration difference between the UP and DOWN signals is converted by the charge pump 174 into a proportional voltage Vcp which controls the delay line 177.
The decoder 179 may in turn be provided with a plurality of selecting inputs, for example, k=6 bit inputs SLR1, . . . , SLR6 of the decoder 179 to select a delay value among several ones, in particular 2k, determined delay values, for example 26 available delayed signals delivered by the delay line 177.
This delay line 177 receives as an input the signal SC delivered by the previous stage of the loop as well as the DC voltage Vcp delivered by the charge pump 174 converter.
The delay line 177 is thus likely to deliver several, in particular 2k, determined delayed signals, for example 26 delayed signals to the outputs OUT1, . . . , OUT64, of the delay line 177 respectively.
A first output OUT1, when selected, enables for example a zero delay to be delivered, while a 64th output OUT64, when selected, enables for example a delay equal to the period of the signal Sc for example 50 ns, to be delivered and the intermediate outputs can deliver for example a delay of between 0.1 ns and 50 ns, for example in the order of 20 ns.
The decoder 179 allows to select a Mth given output OUTM from the outputs OUT1, . . . , OUT64, of the delay line 177 and deliver a first signal SD1 from this given output OUTM according to the order indicated by the selecting signals SLR1, . . . , SLR6.
The decoder 179 may also be provided for outputting a second signal SD2 having a frequency and an amplitude equal to those of the first signal SD1 but phase-shifted with respect to SD1 by a predetermined phase shift, for example in phase quadrature or in a phase opposite to that of the first signal SD1 according to the selected excitation mode of the resonator.
A first excitation mode of the resonator 110 in which a signal is applied to the resonance frequency Fr of phase 0° of said first so-called “excitation” pad of the MEMS or NEMS resonator and a signal equal to half the resonance frequency Fr/2 of a phase 180° on a second so-called “excitation” pad of the MEMS or NEMS resonator 110 may be provided.
A second excitation mode of the resonator can be provided so that it applies a signal SE1 of frequency Fr/2 and phase 0° on the first pad of the resonator and a signal SE2 at Fr/2 of phase 90° to the second excitation pad. This second excitation mode enables the gain to be maximized.
At the delay module 170, switching from the first excitation mode of the second excitation mode can be enabled using a selection bit SLF of the decoder 179.
In the first excitation mode, the signals SD1 and SD2 output from the delay module 170 may respectively have a phase of (360°*M)/64 and a phase of) ((360°*M/64)+180° and an excitation frequency Fe.
In the second excitation mode, the signals SD1 and SD2 may respectively have a phase of (360°*N)/64 and a phase of)((360°*N)/64+90° and a frequency equal to Fe/2.
With such a module 170, the delay or phase shift introduced is adjustable in a wide range of delays or phase shifts and valid whatever the phase shifts introduced by each block or module of the feedback loop.
With such a module 170, the amplitude of the signals SD1 and SD2 does not vary as a function of the frequency range within which lies the resonance frequency of the MEMS 110 or NEMS 110.
With such a module 170, a locked delay which is independent of the supply voltages of the controlling device is introduced.
The delayed signal(s) SD1, SD2 output from the programmable delay stage 170 may then be shaped by an output interface module 190 to be applied to excitation means 110 of the resonator.
This shaping module 190 can generate signals SE1 SE2 having voltage levels adapted to the resonator and serving as excitation signals for actuating the resonator.
The output interface module 190 allows to adapt in level or charge the output signal(s) SD1, SD2 of the programmable delay module 170 to means for exciting the resonator. This output interface 190 may be produced using one or more inverters and one or more level translators.
An exemplary embodiment of an output interface module 190 is given in
This module may be made of buffer memories commonly known as input “buffers” 191, 192, for receiving digital signals according to a first range of amplitudes or voltages, for example, in the order of 1 volt, from a translator level 194 provided to deliver amplitude-enhanced signals to output buffers 195, 196. The module 190 is provided for transmitting signals in a second range of voltages or amplitudes higher than the first range and for example in the order 3 volts.
The module 190 receives digital signals and delivers digital or analog signals. Digital to analog conversion is performed internally or at the output of the module 190, for example by filtering.
In one case, for example, where the resonator 110 is of the type described in connection with
To hold oscillation conditions, the programmable delay module enables a constant phase shift to be established between the input of the first stage and the excitation signals SE1, SE2.
An alternative embodiment of the controlling device previously described is given in connection with
For this alternative, the controlling device comprises, between the digitizing means 130 and the delay unit 170, a configuration selecting module 210 suitable for switching between a first configuration wherein the feedback loop has a first configuration or a first arrangement, and a second configuration wherein the feedback loop has a second configuration or a second arrangement.
The first configuration may enable the controlling device to be placed in a closed loop configuration while the second configuration may be intended to place the device in an open loop configuration.
The configuration selecting module 210 comprises a first input CS connected to the output of the comparator 130 and a second input ET on which a test signal is to be applied.
The configuration selecting module 210 is also provided with a first output ST from which a test signal is to be extracted and a second output CE connected to the programmable delay module 170.
The configuration selecting module 210 is provided to adopt a first configuration wherein the first input CS is connected to the first output ST and the second input ET is connected to the second output CE. The configuration selecting module 210 is also provided to assume a second configuration in which the first input CS is connected to the second output CE, the second input ET being connected to the first output ST.
An example of implementation of such a configuration selecting module is given in
Switching from the first configuration to the second configuration can be achieved depending on the state of a configuration selecting logical signal Ssc.
This module 210 may be formed from 2 to 1 multiplexers, 213 and 215 and buffers 211, 217.
On its first input CS, the module 210 is likely to receive a digital signal Sc from the comparator 130. The first input CS of the module 210 is connected to an input ‘1’ of a first 2-to-1 type multiplexer 213, whereas the second input ET of the module 210 is connected via the buffer 211 to an input, ‘0’ of the first multiplexer 213. This first multiplexer 213 is provided to transmit at the output S one of its two inputs CS and ET, for example according to the following truth table:
A further buffer 217 is provided at the output of the first multiplexer 213.
The first input CS of the module 210 is also connected to an input ‘0’ of a second 2-to-1 type multiplexer 215, while the first input ET of the module 210 is connected to an input ‘1’ of the second multiplexer 215. The second multiplexer 215 is also provided to transmit at the output S one of its two inputs CS and ET, for example by following the following truth table.
The module 210 can thus follow the truth table below:
The configuration selecting module 210 may also be produced so that, and in particular the buffers 211 and 217 may be provided so that the propagation delays between the inputs ET, CS and the outputs ST, CE fulfil the following relationships r1 and r2:
Tp
(ET/ST)-config1
=Tp
(CS/ST)-config2
+Tp
(ET/CE)-config2 (r1)
with:
Tp
(CS/CE)-config1≈0, or
Tp
(CS/CE)-config1
<<Tp
(CS/ST)-config2 and
Tp
(CS/CE)-config1
<<Tp
(ET/CE)-config2 (r2)
By Tp(CS/CE)-config1<<Tp(CS/ST)-config2, it is meant that Tp(CS/CE)-config1 is provided at least ten times or at least a hundred times lower than Tp(CS/ST)-config2.
By Tp(CS/CE)-config1<<Tp(ET/CE)-config2 it is meant that Tp(CS/CE)-config1 is provided at least ten times or at least a hundred times lower than Tp(ET/CE)-config2.
Tp(CS/ST)-config2 and Tp(ET/CE)-config2 can be for example in the order of several nanoseconds.
Tp(CS/CE)-config1 may for example be in the order of several picoseconds for example in the order of one or several hundreds of picoseconds.
Using this configuration selecting module 210, it is possible to conduct an evaluation of the delay or phase shift introduced by the module 170 and which is intended to be selected so as to allow to provide oscillating the resonator and/or hold oscillation thereof.
A method for determining the delay or phase shift to be selected and produced by the module 170 can be the following one:
First the resonance frequency Fr of the resonator 110 is determined by one or more prior actions.
The resonance frequency Fr can be determined, for example, by a direct measurement on the MEMS or NEMS. In the case where the resonator studied is of the type described in relation to
Then, the configuration selecting module 210 is placed in the first configuration to determine the delay Tes=Tp(ET/ST)-config1 between the second input ET of the module 210 and the first output ST, for example using a test signal.
Then, the programmable delay block 170 is programmed so as to introduce a zero delay, while the configuration selector 210 is placed in the second configuration.
A Tesbo delay is then determined between the second input ET and the first output ST when the configuration selecting module 210 is in the second configuration and the controlling device is in open loop.
For this, a frequency signal equal to the resonance frequency Fr previously determined is injected.
The Tesbo delay is such that:
Tesbo=Tp
(CS/ST)-config2
+Tp
(ET/CE)-config2
+Tbo
with Tbo being the delay generated by the rest of the modules and circuits of the device.
The Tbo delay is deduced by the relationship Tbo=Tesbo−Tes (if relationship r1 holds).
The ideal delay Ti to be generated by the programmable delay block is determined to ensure that:
T
1
=n/F−Tbo
where n is a positive integer, with F the frequency of the signal at the input of the device close to or equal to Fr, the resonance frequency of the resonator NEMS, so that:
T
1
=n/Fr−Tbo.
Then a “possible” delay Tr is determined from the whole of programmable delays of the delay module. The delay Tr is chosen equal to k*(Tdelay max/total number of elementary delays), where k is an integer corresponding to the number of elementary delays selected by the value of the input SLF (Tdelay max being equal to or 1/Fr or a multiple of 1/Fr). The number k of retained elementary delays is such that Tr is as close as possible to T1, wherein Tr may be selected below or above T1.
One or more of these steps can be performed by means of a microprocessor associated with one or more digital processing modules, or by means of a data processing device, for example a computer.
After adjusting the delay (SLF), the configuration selecting module 210 is placed in the first configuration, so as to be placed in a closed loop. The first input ET can then be set to a defined state.
Oscillating the resonator can thus be ensured.
According to an alternative embodiment, it could be possible to use other types of circuits to produce a programmable delay module. For example in the case where a high frequency clock signal is available, N times higher than the resonance frequency of the resonator, it will be possible to provide a programmable delay circuit by using a counter by N.
According to another alternative embodiment, a digital delay can be implemented by providing a register whose data are managed in FIFO mode. For a frequency signal, for example in the order of 20 MHz, a register length for example of 50 clocked by a clock at 1 GHz may be provided.
Means for selecting an output of the register, for example as a multiplexer, enable to select an intermediate output of rank i, the signal outputted has a delay ΔT=i*1n=i/1E9 that is a phase shift Δφ=i*360*20e6/1E9, the register width used in the FIFO being identical to the number of bits of the analog digital converter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 12 53040 | Apr 2012 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2013/056912 | 4/2/2013 | WO | 00 |
