1. Field
This disclosure relates generally to non-volatile memories (NVMs) and logic transistors, and more particularly, integrating NVMs with logic transistors that have high-k gate dielectrics and metal gates using a gate-first methodology.
2. Related Art
The integration of non-volatile memories (NVMs) with logic transistors has always been a challenge due to the different requirements for the NVM transistors, which store charge, and the logic transistors which are commonly intended for high speed operation. The need for storing charge has been addressed mostly with the use of floating gates but also with nanocrystals or nitride. In any of these cases, the need for this unique layer makes integration of the NVM transistors and the logic transistors difficult. The particular type of charge storage layer can also have a large effect on the options that are available in achieving the integration.
Accordingly there is a need to provide an integration that improves upon one or more of the issues raised above.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
In one aspect, an integration of a non-volatile memory (NVM) cell in a NVM portion of an integrated circuit and a logic transistor in a logic portion of the integrated circuit includes forming the gate structure of the NVM cell in the NVM portion, including the charge storage layer, while masking the logic portion. The logic gate is formed while masking the NVM portion with a hard mask that is subsequently used to form sidewall spacers in the NVM portion. Source/drain implants are performed simultaneously in the NVM and logic portions. This is better understood by reference to the drawings and the following written description.
The semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOD, silicon, monocrystalline silicon, the like, and combinations of the above. Oxide layer refers to a silicon oxide layer unless otherwise noted. Similarly, nitride layer refers to a silicon nitride layer unless otherwise noted.
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Thus it is shown that metal gate transistors can be made in the presence of NVM cells, even if the NVM cells use nanocrystals, and further that the hard mask used during the metal etch can also subsequently be used in forming sidewall spacers used as an implant mask.
By now it should be appreciated that there has been provided a method of making a semiconductor device. The method includes depositing protective layers over a non-volatile memory gate structure on a memory region of a substrate, wherein the protective layers include a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer. The method further includes depositing a high-k dielectric layer over the protective layers and over a logic region of the substrate. The method further includes depositing a metal gate layer over the high-k dielectric layer in the memory and logic regions. The method further includes depositing a first polysilicon layer over the metal gate layer in the memory and logic regions. The method further includes patterning and etching the memory and logic regions to form a logic gate in the logic region to remove the protective layers in the logic region, wherein the protective layers remain in the memory region after the etching. The method further includes depositing a first layer of spacer material over the memory and logic regions. The method further includes removing the first layer of spacer material, the nitride layer and the second oxide layer from the memory region. The method further includes etching the first oxide layer along with the first layer of spacer material to form first spacers on the non-volatile memory gate structure and the logic gate. The method may further include forming the non-volatile memory gate structure including forming a select gate, forming a charge storage layer over the select gate in the memory region and over the logic region, depositing a second polysilicon layer over the charge storage layer. The method may have a further characterization by which etching the second polysilicon layer to form a control gate over a portion of a top and sidewall of the select gate, and removing the charge storage layer from areas of the memory region that do not underlie the control gate and from the logic region. The method may have a further characterization by which the charge storage layer includes nanocrystals between layers of dielectric material. The method may have a further characterization by which the second polysilicon layer is deposited in the memory region and the logic region. The method may have a further characterization by which the second polysilicon layer remains in the logic region until after the protective layers are deposited. The method may further include after forming the first spacers, creating halo implants in the substrate for the non-volatile memory gate structure and the logic gate. The method may further include, after forming the halo implants, forming second spacers on the first spacers of the non-volatile memory gate structure and the logic gate, forming source and drain regions for the logic gate and non-volatile memory gate structure, and forming self-aligned silicide regions on exposed portions of the source and drain regions. The method may further include depositing the protective layers in the logic region along with the memory region and removing the protective layers from the logic region before depositing the high-k dielectric layer over the logic region and the memory region.
Also described is a method of making a semiconductor device including forming a split gate memory gate structure on a memory region of a substrate. The method further includes protecting the split gate memory gate structure by depositing protective layers over the memory region including the memory gate structure and over a logic region of the substrate, wherein the protective layers include a material that creates a barrier to diffusion of metal. The method further includes retaining the protective layers over the memory region while forming a logic gate in the logic region, the logic gate includes a high-k dielectric layer and a metal layer. The method further includes depositing spacer material over the logic gate. The method further includes forming spacers on the memory gate structure and the logic gate, wherein the spacer on the logic gate is formed of the spacer material and the spacer on the memory gate structure is formed with one of the protective layers. The method may have a further characterization by which depositing the protective layers includes depositing the protective layers over the logic region along with the depositing the protective layers over the memory region. The method may have a further characterization by which the protective layers include a first oxide layer, the material that creates a barrier to diffusion of metal, and a second oxide layer, and the first oxide layer is used to form one of the spacers on the memory gate structure. The method may have a further characterization by which the forming the split gate memory gate structure includes forming a select gate, forming a charge storage layer over the select gate including depositing a bottom dielectric layer over the select gate, depositing nanocrystals over the bottom dielectric layer, and depositing a top dielectric layer over the nanocrystals, and forming a control gate over the charge storage layer. The method may have a further characterization by which the forming the control gate includes depositing a polysilicon layer over the memory region and the logic region and etching the polysilicon layer in the memory region while retaining the polysilicon layer in the logic region. The method may further include depositing the protective layers over the polysilicon layer in the logic region and removing the protective layers and the polysilicon layer in the logic region before forming the logic gate. The method may further include, before forming the spacers, depositing the spacer material over the protective layers in the memory region and the logic region while depositing the spacer material over the logic gate, depositing photoresist over the logic region, and in the memory region, removing the spacer material and at least the material that creates a barrier to diffusion of metal. The method may further include, after forming the spacers, simultaneously creating halo implants in the substrate for the non-volatile memory gate structure and the logic gate. The method may further include, after forming the halo implants, forming second spacers on the spacers of the non-volatile memory gate structure and the logic gate, simultaneously forming source and drain regions for the logic gate and non-volatile memory gate structure, and simultaneously forming self-aligned silicide regions on exposed portions of the source and drain regions.
Described also is a method of making a semiconductor device including forming a non-volatile memory gate structure in a memory region of a substrate. The forming the memory gate structure includes depositing polysilicon over the memory region and a logic region of the substrate, masking the polysilicon in the logic region and in portions of the memory region, and etching unmasked portions of the polysilicon to form a control gate of the memory gate structure. The method further includes depositing a first spacer material over the memory region and the logic region. The method further includes depositing a metal diffusion barrier layer over the first spacer material in the memory region and the logic region. The method further includes removing the first spacer material and the metal diffusion barrier layer from the logic region. The method further includes depositing a metal layer in the logic region and over the metal diffusion barrier layer in the memory region. The method further includes forming a metal gate from the metal layer in the logic region including removing the metal layer from the memory region. The method further includes forming a second spacer material in the logic region. The method further includes removing the metal layer and the metal diffusion barrier layer from the memory region. The method further includes etching the first spacer material to form a spacer on the memory gate structure while etching the second spacer material for form a spacer on the metal gate. The method may further include depositing a high-k dielectric layer in the logic region and the memory region before depositing the metal layer and removing the high-k dielectric layer in the memory region after removing the metal layer from the memory region. The method may have a further characterization by which, before depositing the polysilicon, forming a select gate and forming a charge storage layer over the select gate, wherein the forming the charge storage layer includes depositing a bottom dielectric layer over the select gate, depositing nanocrystals over the bottom dielectric layer, and depositing a top dielectric layer over the nanocrystals.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, different materials than those described may be found to be effective. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Number | Name | Date | Kind |
---|---|---|---|
5614746 | Hong et al. | Mar 1997 | A |
6087225 | Bronner et al. | Jul 2000 | A |
6194301 | Radens et al. | Feb 2001 | B1 |
6235574 | Tobben et al. | May 2001 | B1 |
6333223 | Moriwaki et al. | Dec 2001 | B1 |
6388294 | Radens et al. | May 2002 | B1 |
6509225 | Moriwaki et al. | Jan 2003 | B2 |
6531734 | Wu | Mar 2003 | B1 |
6635526 | Malik et al. | Oct 2003 | B1 |
6707079 | Satoh et al. | Mar 2004 | B2 |
6777761 | Clevenger et al. | Aug 2004 | B2 |
6785165 | Kawahara et al. | Aug 2004 | B2 |
6939767 | Hoefler et al. | Sep 2005 | B2 |
7154779 | Mokhlesi et al. | Dec 2006 | B2 |
7183159 | Rao et al. | Feb 2007 | B2 |
7190022 | Shum et al. | Mar 2007 | B2 |
7202524 | Kim et al. | Apr 2007 | B2 |
7208793 | Bhattacharyya | Apr 2007 | B2 |
7256125 | Yamada et al. | Aug 2007 | B2 |
7271050 | Hill | Sep 2007 | B2 |
7365389 | Jeon et al. | Apr 2008 | B1 |
7391075 | Jeon et al. | Jun 2008 | B2 |
7402493 | Oh et al. | Jul 2008 | B2 |
7405968 | Mokhlesi et al. | Jul 2008 | B2 |
7439134 | Prinz et al. | Oct 2008 | B1 |
7476582 | Nakagawa et al. | Jan 2009 | B2 |
7521314 | Jawarani et al. | Apr 2009 | B2 |
7524719 | Steimle et al. | Apr 2009 | B2 |
7544490 | Ferrari et al. | Jun 2009 | B2 |
7544980 | Chindalore et al. | Jun 2009 | B2 |
7544990 | Bhattacharyya | Jun 2009 | B2 |
7560767 | Yasuda et al. | Jul 2009 | B2 |
7795091 | Winstead et al. | Sep 2010 | B2 |
7799650 | Bo et al. | Sep 2010 | B2 |
7816727 | Lai et al. | Oct 2010 | B2 |
7821055 | Loiko et al. | Oct 2010 | B2 |
7906396 | Chiang et al. | Mar 2011 | B1 |
7932146 | Chen et al. | Apr 2011 | B2 |
7989871 | Yasuda | Aug 2011 | B2 |
7999304 | Ozawa et al. | Aug 2011 | B2 |
8017991 | Kim et al. | Sep 2011 | B2 |
8043951 | Beugin et al. | Oct 2011 | B2 |
8063434 | Polishchuk et al. | Nov 2011 | B1 |
8093128 | Koutny et al. | Jan 2012 | B2 |
8138037 | Chudzik et al. | Mar 2012 | B2 |
8168493 | Kim | May 2012 | B2 |
8298885 | Wei et al. | Oct 2012 | B2 |
8334198 | Chen et al. | Dec 2012 | B2 |
8372699 | Kang et al. | Feb 2013 | B2 |
8389365 | Shroff et al. | Mar 2013 | B2 |
8399310 | Shroff et al. | Mar 2013 | B2 |
8524557 | Hall et al. | Sep 2013 | B1 |
8536006 | Shroff et al. | Sep 2013 | B2 |
8536007 | Shroff et al. | Sep 2013 | B2 |
8679927 | Ramkumar et al. | Mar 2014 | B2 |
20010049166 | Peschiaroli et al. | Dec 2001 | A1 |
20020061616 | Kim et al. | May 2002 | A1 |
20030022434 | Taniguchi et al. | Jan 2003 | A1 |
20040075133 | Nakagawa et al. | Apr 2004 | A1 |
20040262670 | Takebuchi et al. | Dec 2004 | A1 |
20050145949 | Sadra et al. | Jul 2005 | A1 |
20060038240 | Tsutsumi et al. | Feb 2006 | A1 |
20060046449 | Liaw | Mar 2006 | A1 |
20060099798 | Nakagawa | May 2006 | A1 |
20060134864 | Higashitani et al. | Jun 2006 | A1 |
20060211206 | Rao et al. | Sep 2006 | A1 |
20060221688 | Shukuri et al. | Oct 2006 | A1 |
20070037343 | Colombo et al. | Feb 2007 | A1 |
20070077705 | Prinz et al. | Apr 2007 | A1 |
20070115725 | Pham et al. | May 2007 | A1 |
20070215917 | Taniguchi | Sep 2007 | A1 |
20070224772 | Hall et al. | Sep 2007 | A1 |
20070249129 | Hall et al. | Oct 2007 | A1 |
20070264776 | Dong et al. | Nov 2007 | A1 |
20080029805 | Shimamoto et al. | Feb 2008 | A1 |
20080050875 | Moon et al. | Feb 2008 | A1 |
20080067599 | Tsutsumi et al. | Mar 2008 | A1 |
20080105945 | Steimle et al. | May 2008 | A1 |
20080121983 | Seong et al. | May 2008 | A1 |
20080128785 | Park et al. | Jun 2008 | A1 |
20080145985 | Chi | Jun 2008 | A1 |
20080185635 | Yanagi et al. | Aug 2008 | A1 |
20080237690 | Anezaki et al. | Oct 2008 | A1 |
20080237700 | Kim et al. | Oct 2008 | A1 |
20080283900 | Nakagawa et al. | Nov 2008 | A1 |
20080290385 | Urushido | Nov 2008 | A1 |
20080308876 | Lee et al. | Dec 2008 | A1 |
20090050955 | Akita et al. | Feb 2009 | A1 |
20090065845 | Kim et al. | Mar 2009 | A1 |
20090072274 | Knoefler et al. | Mar 2009 | A1 |
20090078986 | Bach | Mar 2009 | A1 |
20090101961 | He et al. | Apr 2009 | A1 |
20090111229 | Steimle et al. | Apr 2009 | A1 |
20090179283 | Adams et al. | Jul 2009 | A1 |
20090225602 | Sandhu et al. | Sep 2009 | A1 |
20090256211 | Booth, Jr. et al. | Oct 2009 | A1 |
20090269893 | Hashimoto et al. | Oct 2009 | A1 |
20090273013 | Winstead et al. | Nov 2009 | A1 |
20090278187 | Toba | Nov 2009 | A1 |
20110031548 | White et al. | Feb 2011 | A1 |
20110095348 | Chakihara et al. | Apr 2011 | A1 |
20110204450 | Moriya | Aug 2011 | A1 |
20110260258 | Zhu et al. | Oct 2011 | A1 |
20120034751 | Ariyoshi et al. | Feb 2012 | A1 |
20120104483 | Shroff et al. | May 2012 | A1 |
20120132978 | Toba et al. | May 2012 | A1 |
20120142153 | Jeong | Jun 2012 | A1 |
20120248523 | Shroff et al. | Oct 2012 | A1 |
20120252171 | Shroff et al. | Oct 2012 | A1 |
20130026553 | Horch | Jan 2013 | A1 |
20130037886 | Tsai et al. | Feb 2013 | A1 |
20130065366 | Thomas et al. | Mar 2013 | A1 |
20130084684 | Ishii et al. | Apr 2013 | A1 |
20130137227 | Shroff et al. | May 2013 | A1 |
20130171785 | Shroff et al. | Jul 2013 | A1 |
20130171786 | Shroff et al. | Jul 2013 | A1 |
20130178027 | Hall et al. | Jul 2013 | A1 |
20130178054 | Shroff et al. | Jul 2013 | A1 |
20130264633 | Hall et al. | Oct 2013 | A1 |
20130264634 | Hall et al. | Oct 2013 | A1 |
20130267074 | Hall et al. | Oct 2013 | A1 |
20130323922 | Shen et al. | Dec 2013 | A1 |
20140035027 | Chakihara et al. | Feb 2014 | A1 |
20140050029 | Kang et al. | Feb 2014 | A1 |
20140120713 | Shroff et al. | May 2014 | A1 |
Number | Date | Country |
---|---|---|
2009058486 | May 2009 | WO |
Entry |
---|
Office Action—Allowance mailed Feb. 21, 2014 in U.S. Appl. No. 13/441,426. |
Office Action—Allowance mailed Feb. 28, 2014 in U.S. Appl. No. 13/442,142. |
Office Action—Allowance mailed Mar. 3, 2014 in U.S. Appl. No. 13/790,014. |
Office Action—Allowance mailed Mar. 6, 2014 in U.S. Appl. No. 13/491,771. |
Office Action—Allowance mailed Mar. 11, 2014 in U.S. Appl. No. 13/907,491. |
Office Action—Allowance mailed Mar. 12, 2014 for U.S. Appl. No. 13/790,225. |
Chen, J.H., et al., “Nonvolatile Flash Memory Device Using Ge Nanocrystals Embedded in HfA10 High-k Tunneling and Control Oxides: Device Fabrication and Electrical Performance”, IEEE Transactions on Electron Devices, vol. 51, No. 11, Nov. 2004, pp. 1840-1848. |
Kang, T.K., et al., “Improved characteristics for Pd nanocrystal memory with stacked HfAlO—SiO2 tunnel layer”, Sciencedirect.com, Solid-State Electronics, vol. 61, Issue 1, Jul. 2011, pp. 100-105, http://wwww.sciencedirect.com/science/article/pii/S0038110111000803. |
Krishnan, S., et al.., “A Manufacturable Dual Channel (Si and SiGe) High-K Metal Gate CMOS Technology with Multiple Oxides for High Performance and Low Power Applications”, IEEE, Feb. 2011 IEEE International Electron Devices Meeting (IEDM), 28.1.1-28.1.4, pp. 634-637. |
Lee, J.J., et al., “Theoretical and Experimental Investigation of Si Nanocrystal Memory Device with HfO2 High-K Tunneling Dielectric”, IEEE Transactions on Electron Devices, vol. 50, No. 10, Oct. 2003, pp. 2067-2072. |
Liu, Z., et al., “Metal Nanocrystal Memories—Part I: Device Design and Fabrication”, IEEE Transactions on Electron Devices, vol. 49, No. 9, Sep. 2002, pp. 1606-1613. |
Mao, P., et al., “Nonvolatile memory devices with high density ruthenium nanocrystals”, Applied Physics Letters, vol. 93, Issue 24, Electronic Transport and Semiconductors, 2006. |
Mao, P., et al., “Nonvolatile Memory Characteristics with Embedded high Density Ruthenium Nanocrystals”, http://iopscience.iop.org/0256-307X/26/5/056104, Chinese Physics Letters, vol. 26, No. 5, 2009. |
Pei, Y., et al., “MOSFET nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and HfO2 High-k Blocking Dielectric”, IEEE Transactions of Nanotechnology, vol. 10, No. 3, May 2011, pp. 528-531. |
Wang, X.P., et al., Dual Metal Gates with Band-Edge Work Functions on Novel HfLaO High-K Gate Dielectric, IEEE, Symposium on VLSI Technology Digest of Technical Papers, 2006. |
U.S. Appl. No. 13/402,426, Hall, M.D., et al., “Non-Volatile Memory Cell and Logic Transistor Integration”, Office Action—Allowance—May 3, 2013. |
U.S. Appl. No. 13/789,971, Hall, M.D., et al, “Integration Technique Using Thermal Oxide Select Gate Dielectric for Select Gate and Replacement Gate for Logic ”, Office Action—Allowance—May 15, 2013. |
U.S. Appl. No. 13/491,771, Hall et al , “Integrating Formation of a Replacement Ggate Transistor and a Non-Volatile Memory Cell Using a High-K Dielectric”, Office Action—Rejection, Sep. 9, 2013. |
U.S. Appl. No. 13/442,142, Hall, M.D., et al., “Logic Transistor and Non-Volatile Memory Cell Integration”, Office Action—Ex Parte Quayle, Apr. 4, 2013. |
U.S. Appl. No. 13/442,142, Hall, M.D., et al., “Logic Transistor and Non-Volatile Memory Cell Integration”, Office Action—Allowance, Aug. 2, 2013. |
U.S. Appl. No. 13/907,491, Hall, M.D., et al., “Logic Transistor and Non-Volatile Memory Cell Integration”, Office Action—Rejection, Sep. 13, 2013. |
U.S. Appl. No. 12/915,726, Shroff, M., et al., “Non-Volatile Memory and Logic Circuit Process Integration”, Office Action—Restriction, Jul. 31, 2012. |
U.S. Appl. No. 12/915,726, Shroff, M., et al., “Non-Volatile Memory and Logic Circuit Process Integration”, Office Action—Allowance, Dec. 10, 2012. |
U.S. Appl. No. 13/781,727, Shroff, M., et al., “Methods of Making Logic Transistors and non-Volatile Memory Cells”, Office Action—Rejection, Aug. 22, 2013. |
U.S. Appl. No. 13/077,491, Shroff, M.., et al., “Non-Volatile Memory and Logic Circuit Process Integration”, Office Action—Rejection, Aug. 15, 2012. |
U.S. Appl. No. 13/077,491, Shroff, M.., et al., “Non-Volatile Memory and Logic Circuit Process Integration”, Office Action—Rejection, Feb. 6, 2013. |
U.S. Appl. No. 13/077,491, Shroff, M.., et al., “Non-Volatile Memory and Logic Circuit Process Integration”, Office Action—Allowance, Jun. 18, 2013. |
U.S. Appl. No. 13/077,501, Shroff, M.., et al., “Non-Volatile Memory and Logic Circuit Process Integration”, Office Action—Allowance, Nov. 26, 2012. |
U.S. Appl. No. 13/313,179, Shroff, M., et al., “Method of Protecting Against via Failure and Structure Therefor”, Office Action—Rejection, Aug. 15, 2013. |
U.S. Appl. No. 13/307,719, Shroff, M., et al., “Logic and Non-Volatile Memory (NVM) Integration”, Office Action—Allowance, May 29, 2013. |
U.S. Appl. No. 13/343,331, Shroff, M., et al., “Non-Volatile Memory (NVM) and Logic Integration”, Office Action—Rejection, Mar. 13, 2013. |
U.S. Appl. No. 13/343,331, Shroff, M., et al., “Non-Volatile Memory (NVM) and Logic Integration”, Office Action—Allowance, Jun. 24, 2013. |
U.S. Appl. No. 13/441,426, Shroff, M., et al., “Non-Volatile Memory (NVM) and Logic Integration”, Office Action—Allowance, Sep. 9, 2013. |
U.S. Appl. 13/780,574, Hall, M.D., et al., Non-Volatile Memory (NVM) and Logic Integration, Office Action—Allowance, Sep. 6, 2013. |
U.S. Appl. 13/491,760, Shroff, M.., et al., “Integrating Formation of a Replacement Gate Transistor and a Non-Volatile Memory Cell Using an Interlayer Dielectric”, Office Action—Allowance, Jul. 1, 2013. |
U.S. Appl. No. 13/491,771, Hall, M., et al., “Integrating Formation of a Replacement Gate Transistor and a Non-Volatile Memory Cell Using a High-K Dielectric”, filed Jun. 8, 2012. |
U.S. Appl. No. 13/790,225, Hall, M., et al., “Integrating Formation of a Replacement Gate Transistor and a non-Volatile Memory Cell Having Thin Film Storage”, filed Mar. 8, 2013. |
U.S. Appl. No. 13/790,014, Hall, M., et al., “Integrating Formation of a Logic Transistor and a None-Volatile Memory Cell Using a Partial Replacement Gate Technique”, filed Mar. 8, 2013. |
U.S. Appl. No. 13/955,665, Perera, a.H., “Non-Volatile Memory (NVM) and High K and Metal Gate Integration Using Gate First Methodology”, filed Jul. 31, 2013. |
U.S. Appl. No. 13/928,666, Hong, C. M., et al., “Non-Volatile Memory (NVM) and High Voltage Transistor Integration”, filed Jun. 27, 2013. |
U.S. Appl. No. 13/780,591, Hall, M.D., et al., “Non-Volatile Memory (NVM) and Logic Integration”, filed Feb. 28, 2013. |
U.S. Appl. No. 13/491,760, Shroff, M.D., et al., “Integrating Formation of a Replacement Gate Transistor and a Non-Volatile Memory Cell Using an Interlayer Dielectric”, filed Jun. 8, 2012. |
U.S. Appl. No. 13/661,157, Shroff, M.D., et al., “Method of Making a Logic Transistor and a Non-Volatile Memory (NVM) Cell”, file Oct. 26, 2012. |
U.S. Appl. No. 13/781,727, Shroff, M., et al., “Methods of Making Logic Transistors and non-Volatile Memory Cells”, Office Action—Restriction, Jun. 21, 2013. |
Office Action mailed Nov. 22, 2013 in U.S. Appl. No. 13/780,591. |
Office Action mailed Jan. 31, 2014 in U.S. Appl. No. 13/781,727. |
Office Action mailed Dec. 24, 2013 in U.S. Appl. No. 13/790,225. |
Office Action mailed Dec. 24, 2013 in U.S. Appl. No. 13/790,014. |
Office Action mailed Dec. 31, 2013 in U.S. Appl. No. 13/442,142. |
Office Action mailed Jan. 16, 2014 in U.S. Appl. No. 13/491,771. |
U.S. Appl. No. 13/781,727, Office Action—Allowance, May 12, 2014. |
U.S. Appl. 13/441,426, Shroff, M. D., et al., Office Action—Allowance, mailed Jun. 9, 2014. |
U.S. Appl. No. 13/907,491, Office Action—Rejection, Sep. 3, 2013. |
U.S. Appl. No. 13/343,331, Office Action—Allowance, Nov. 8, 2013. |
U.S. Appl. No. 13/928,666, Hong, Office Action—Rejection, mailed Jul. 23, 2014. |
U.S. Appl. No. 14/041,662, Perera, Office Action—Restriction, mailed Aug. 1, 2014. |
U.S. Appl. No. 13/969,180, Perera, Office Action—Allowance, mailed Aug. 5, 2014. |
U.S. Appl. No. 13/781727, Shroff, Office Action—Allowance, mailed Aug. 15, 2014. |
U.S. Appl. No. 13/973,549, Hong, Office Action—Restriction, mailed Aug. 26, 2014. |