Non-volatile memory structure and method of fabrication

Information

  • Patent Grant
  • 7638850
  • Patent Number
    7,638,850
  • Date Filed
    Wednesday, May 24, 2006
    18 years ago
  • Date Issued
    Tuesday, December 29, 2009
    14 years ago
Abstract
A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
Description
FIELD OF THE INVENTION

The present invention relates to volatile memory devices, such as nitride read only memory (NROM) cells generally and to their structure and methods of fabrication in particular.


BACKGROUND OF THE INVENTION

Dual bit memory cells are known in the art. One such memory cell is the NROM (nitride read only memory) cell 10, shown in FIG. 1A to which reference is now made, which stores two bits 12 and 14 in a nitride based layer 16, such as an oxide-nitride-oxide (ONO) stack, sandwiched between a polysilicon word line 18 and a channel 20. Channel 20 is defined by buried bit line diffusions 22 on each side which are isolated from word line 18 by a thermally grown oxide layer 26, grown after bit lines 22 are implanted. During oxide growth, bit lines 22 may diffuse sideways, expanding from the implantation area.


NROM cells are described in many patents, for example in U.S. Pat. No. 6,649,972, assigned to the common assignees of the present invention, whose disclosure is incorporated herein. As shown in FIG. 1B, to which reference is now briefly made, NROM technology employs a virtual-ground array architecture with a dense crisscrossing of word lines 18 and bit lines 22. Word lines 18 and bit lines 22 optimally can allow a 4-5 F2 size cell, where F designates the design rule (i.e. minimum size of an element) of the technology in which the array was constructed. For example, the design rule for a 70 nm technology is F=70 nm. However, most NROM technologies which use the more advanced processes of less than 170 nm employ a larger cell, of 5-6 F2′ due to the side diffusion of the bit lines.


A common problem is the integrity of bit line oxides 26. As can be seen in FIG. 1A, they are thick in a middle 25 but shrink to an “oxide beak” 27 at the sides. In general, middles 25 are of good quality but beaks 27 are of poor quality, and thus are susceptible to breakdown. Moreover, the thickness of middles 25 is sensitive to the concentration of n+ doping at the surface of bit line 22 and is thus, difficult to control. In older generation technologies, the solution to this was high temperature oxidation. However, this causes substantial thermal drive, which increases the side diffusion of bit lines 22.


Another common problem is that the NROM manufacturing process is significantly different than the periphery CMOS manufacturing process but, to create a wafer with both CMOS and NROM elements, both processes are integrated together. This affects the characterization of the CMOS transistors.


The following patents and patent applications attempt to solve these issues and to improve scaling. US 2004/0157393 to Hwang describes a manufacturing process for a non-volatile memory cell of the SONOS type which attempts to reduce or minimize the undesirable effects of small dimension components. U.S. Pat. No. 6,686,242 B2 to Willer et al. describes an NROM cell that they claim can be implemented within a 4-5 F2 area. U.S. Ser. No. 11/247,733, filed Oct. 11, 2005, assigned to the common assignees of the present invention, and US 2005/255651 to Qian et al. describe further processes for manufacturing NROM cells.


Each of the above patents and patent applications utilizes a dual poly process (DPP), where a first polysilicon layer is deposited in columns between which bit lines 22 are implanted. Word lines 18 are then deposited as a second polysilicon layer, cutting the columns of the first polysilicon layer into islands between bit lines 22. In most of the above patents and patent applications, to maximize the effective length Leff of the channel under the first polysilicon layer, spacers, such as of oxide or of nitride, are generated next to the first polysilicon layer and the bit lines are implanted into the reduced width openings. A thermal drive is then applied and the bit lines then diffuse outwardly, towards the first polysilicon columns.


Unfortunately, some of the bit lines occasionally do not reach the first polysilicon layer. Without the overlap between the bit lines and the first polysilicon, which acts as the gate for the memory cell, the cells do not work.


SUMMARY OF THE PRESENT INVENTION

An object of the present invention is, at least, to increase the effective width Leff of the channel without increasing the feature size.


There is therefore provided, in accordance with a preferred embodiment of the present invention, a method for creating a non-volatile memory array. The method includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.


Moreover, in accordance with a preferred embodiment of the present invention, generating polysilicon columns includes generating spacers to the sides of the mask columns and etching at least the first polysilicon layer between the spacers to generate the increased-width polysilicon columns.


Further, in accordance with a preferred embodiment of the present invention, the spacers are nitride or oxide.


Still further, in accordance with a preferred embodiment of the present invention, generating bit lines includes implanting the bit lines and performing a rapid thermal anneal.


Additionally, in accordance with a preferred embodiment of the present invention, the etching etches to a top layer of the ONO layer, a bottom layer of the ONO layer or the substrate.


Alternatively, in accordance with a preferred embodiment of the present invention, the etching etches to either a bottom layer of the ONO layer or the substrate and also includes depositing a protective spacer between the polysilicon columns.


Further, in accordance with a preferred embodiment of the present invention, generating the polysilicon columns also includes removing the mask columns and the spacers after the etching.


Moreover, in accordance with a preferred embodiment of the present invention, depositing the oxide occurs before removing the mask columns and the spacers. Alternatively, depositing the oxide occurs after removing the mask columns and the spacers.


Further, in accordance with a preferred embodiment of the present invention, the method includes planarizing the array to the height of the increased-width polysilicon columns and removing the mask columns and the spacers before the planarizing. Alternatively, the method includes planarizing the array to the height of the mask columns and removing the mask columns and the spacers after the planarizing.


Still further, in accordance with a preferred embodiment of the present invention, generating the polysilicon columns includes etching polysilicon between the mask columns and generating polysilicon spacers to the sides of the polysilicon columns. This embodiment may also include depositing second polysilicon on top of the planarized array, etching the second polysilicon into word lines, removing a portion of the deposited oxide between the increased-width polysilicon columns and the word lines and etching the increased-width polysilicon columns between the word lines into gates.


Further, in accordance with a preferred embodiment of the present invention, thickness of the polysilicon columns and/or the second polysilicon is at least 20 nm thick.


Additionally, in accordance with a preferred embodiment of the present invention, the non-volatile memory array is a nitride read only memory (NROM) array.


Moreover, in accordance with a preferred embodiment of the present invention, the method includes generating either a spacer or a liner after word lines are formed.


Further, in accordance with a preferred embodiment of the present invention, the method includes implanting an anti-punchthrough implant in a substrate at least between word lines.


Still further, in accordance with a preferred embodiment of the present invention, the method includes implanting an anti-punchthrough implant in a substrate between at least one of the spacer and the liner associated with the word lines.


Alternatively, in accordance with a preferred embodiment of the present invention, the method may include depositing conductive material on top of the planarized array and etching the conductive material into word lines and the polysilicon columns into gates.


There is also provided, in accordance with a preferred embodiment of the present invention, a method for creating a non-volatile memory array. This method includes depositing mask columns of a given width on a layer of polysilicon overlaying an ONO layer covering a substrate, implanting pocket implants in the substrate between the mask columns and through the polysilicon layer and the ONO layer, creating spacers to the sides of the mask columns, etching the polysilicon layer between the spacers thereby generating increased-width polysilicon columns, removing the mask columns and the spacers, generating bit lines in the substrate between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.


There is also provided, in accordance with a preferred embodiment of the present invention, a non-volatile memory cell. The cell includes columns of channels of a given width in a semiconductor substrate, columns of junctions at the edges of the channels, columns of reduced-width diffusion bit lines between the junctions, increased-width polysilicon gates over charge trapping dielectric over the portions of the channels and overlapping at least portions of the junctions, reduced-width bit line oxides at least between the polysilicon gates and polysilicon word lines perpendicular to the columns connecting rows of the polysilicon gates.


Additionally, in accordance with a preferred embodiment of the present invention, the junctions are pocket implants.


Moreover, in accordance with a preferred embodiment of the present invention, the increased-width polysilicon gates are formed of first polysilicon and polysilicon spacers. Alternatively,. the increased-width polysilicon gates are formed of first polysilicon.


Further, in accordance with a preferred embodiment of the present invention, the bit line oxides extend to a height of the polysilicon gates under the polysilicon word lines and are shorter than the height between the polysilicon word lines.


Still further, in accordance with a preferred embodiment of the present invention, the bit line oxides extend to a height above the polysilicon gates. Alternatively, the bit line oxides extend to a height of the polysilicon gates. In another embodiment, the bit line oxides next to the polysilicon gates are wider at a top thereof than at a bottom thereof.





BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:



FIG. 1A is a schematic illustration of an NROM memory cell;



FIG. 1B is a schematic illustration of a layout of the cell of FIG. 1A;



FIGS. 2A and 2B together are a flow chart illustration of a manufacturing method for a novel memory cell;



FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I are cross-sectional illustrations of the cell at various points during the method of FIGS. 2A and 2B;



FIGS. 4A and 4B are top view illustrations of a memory array manufactured by the method of FIGS. 2A and 2B;



FIGS. 5A and 5B together are a flow chart illustration of an alternative method to that of FIGS. 2A and 2B;



FIG. 6 is a graphical illustration of the cell at one point during the method of FIGS. 5A and 5B;



FIGS. 7A and 7B together are a flow chart illustration of a further alternative method to that of FIGS. 2A and 2B;



FIG. 8 is a cross-sectional illustration of the cell at one point during the method of FIGS. 7A and 7B;



FIGS. 9A and 9B together are a flow chart illustration of another manufacturing method for a novel memory cell;



FIGS. 10A, 10B, 10C and 10D are cross-sectional illustrations of the cell at various points during the method of FIGS. 9A and 9B; and



FIGS. 11A, 11B and 11C are expanded isometric illustrations of the cell during generation of word lines in the method of FIGS. 9A and 9B.





It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.


DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.


Reference is now made to FIGS. 2A and 2B, which, together, illustrate a novel process for manufacturing nitride read only memory (NROM) arrays which may attempt to ensure the presence of an overlap at the junction of the bit lines with the polysilicon gates. Reference is also made to FIGS. 3A-3I which show the results of various steps of FIG. 2 and to FIGS. 4A and 4B which show the layout of various steps of FIG. 2. As is discussed in more detail hereinbelow, the present invention may provide a smaller cell size and, with the more reliable overlap, the present invention may provide cells with increased reliability.


After preparation of a substrate 30 (FIG. 3A), an ONO layer 32 may be laid down (step 100) over the entire wafer, where, in an exemplary embodiment, the bottom oxide layer may be 3-7 mn thick, the nitride layer may be 3-7 nm thick and the top oxide layer may be 6-14 nm thick.


A mask may be laid down and the ONO layer from the periphery (e.g. area of the chip designated for CMOS operation) may be removed (step 102), after which the gate oxides of the periphery may be grown (not shown) and a threshold voltage (Vt) doping may be implanted (also not shown) for the CMOS periphery. It will be appreciated that the operations of step 102 are high thermal budget operations. Moreover, as will be seen hereinbelow, they are the last high thermal budget operations in the present process.


In step 106, a first polysilicon layer 31 may be laid down over the entire chip, covered by a hard mask 33, such as of SiON (silicon oxy-nitride) or of nitride. An exemplary first polysilicon layer 31 may be 20-100 nm thick and hard mask 33 may be 20-50 nm thick.


An etch may be performed (step 108) to generate bit line openings 37 (FIG. 3C) in hard mask 33. The etch may involve laying down a photoresist in a column pattern covering the periphery and the areas of the memory array not destined to be bit lines and then etching with an appropriate etchant. For example, a SiON etch may be used if hard mask 33 is of SiON. The etch may be set to stop at first polysilicon layer 31.



FIG. 3C shows the results of step 108. Two columns of hard mask 33 are shown on top of first polysilicon layer 31, which, in turn, is shown on top of ONO layer 32.


Pocket implants 41 may now be implanted (step 110) between mask columns 33 and through both first polysilicon layer 31 and ONO layer 32. An exemplary pocket implant may be of 1-5×1013/cm2 of Boron (BF2), at an angle of 0-15°, where the angle may be limited by the width of bit line opening 37 and the height of mask 33. Part of pocket implant 41 may scatter and diffuse under mask columns 33. In an alternative embodiment, the pocket implant may be of Boron (BF2) or Indium.


Pocket implants 41 form junctions to channels 51 (FIG. 3D), which junctions are active parts of memory cells and, as discussed hereinabove, must be covered by the polysilicon gate of the cell in order for the cell to operate.


In step 112, spacers 42 may be generated on the sides of hard mask columns 33, where spacers 42 may be of nitride or oxide. Typically, such spacers may be generated by first depositing a liner, such as of 10-25 nm, and etching it with an anisotropic etch.


It will be appreciated that spacers 42 may define a mask for etching (step 113) first polysilicon layer 31 and, optionally, for etching (step 114) ONO layer 32. If no ONO etch happens, then the polysilicon etch may be set to stop on the top oxide layer. However, if step 114 happens, then the ONO etch may be set to stop at the bottom oxide, labeled 36. It may leave bottom oxide 36 or may etch a portion of it, typically leaving 2 nm.


The result of steps 112, 113 and 114 may be reduced width, bit line openings, now labeled 37′ in FIG. 3D. It will be appreciated that reduced width bit line openings 37′ may increase the width of polysilicon columns 34 and ONO columns 32′. Moreover, it will be appreciated that, by design, increased width, polysilicon columns 34 extend over pocket implants 41 and will extend over bit lines 50 after they scatter during implantation and side diffusion, thereby ensuring that, by design, polysilicon columns 34 have an overlap with the active junction of the cell.


Bit lines 50 may be implanted (step 115) through reduced width, bit line openings 37′, followed by a rapid thermal anneal (RTA). In one exemplary embodiment, the bit line implant is of Arsenic of 2×1015/cm2 at 10-20 Kev and with an angle of 0 or 7% to the bit line. During the rapid thermal anneal, bit lines 50 may diffuse deeper into substrate 30 and sideways, under ONO columns 32′.


The extent of the diffusion may depend on numerous factors. However, because bit lines 50 may be implanted between polysilicon columns 34, (rather than between oxide or nitride spacers next to polysilicon columns, as in the prior art), any diffusion of bit lines 50 will be under polysilicon columns 34. Thus, the present invention may ensure the presence in every memory cell of some overlap between the bit lines and the polysilicon gate (to be made from polysilicon columns 34 in a later step).


The ensured overlap may enable cells to be placed closer together while still maintaining the same effective length Leff of channel 51. In the prior art, the width W of the mask columns to define polysilicon columns 34 was the width of the desired effective channel length plus the desired amount of overlap (W=Leff+2*overlap). In the present invention, however, the width of hard mask 33 may be narrower, by at least the width of spacers 42, to provide the same desired effective channel length, since polysilicon columns 34 extend to the edges of implanted bit lines 50 (W=Leef+2*overlap−2*spacers).


In step 116, an oxide filler 52 may be deposited on the wafer. As can be seen in FIG. 3E, oxide filler 52 may fill reduced bit line openings 37′ and may also cover other parts of the wafer. In step 118, a CMP (chemical mechanical planarization) process may be performed to remove excess oxide filler 52, typically back to hard mask 33. The result of step 118 is shown in FIG. 3F.


In step 120, hard mask 33 and spacers 42 may be removed from the wafer. If hard mask 33 and spacers 42 are both of nitride, then they may be etched via a nitride wet etch. If hard mask 33 and spacers 42 are of oxide, then they may be etched with an oxide etch over the entire wafer. As shown in FIG. 3G, this step may leave polysilicon columns 34 exposed between bit line oxides 43, formed of oxide filler 52 and bottom oxide 36. It will be appreciated that bit line oxides 43, which are also exposed, are formed as blocked columns with openings 45 above first polysilicon columns 34 therebetween.


In step 122, a second polysilicon layer 54 (of 50-150 nm) and a silicide layer 55 may then be deposited (step 122) on the entire wafer. As shown in FIG. 3H, second polysilicon layer 54 may cover bit line oxides 43 and may extend, as extensions 47, into openings 45 to electrically connect to first polysilicon columns 34. Second polysilicon layer 54 may be coated with silicide layer 55.


Layers 34, 54 and 55 may then be etched (step 124) into word lines 56 (FIG. 3I), which may be in rows perpendicular to the bit line columns. To etch the word lines, another hard mask may first be deposited over silicide layer 55, followed by an etch of the hard mask, silicide layer 55, second polysilicon layer 54 and first polysilicon columns 34. The etch may continue into one or more of the ONO layers 32 or not, as desired.



FIG. 3I shows one word line 56. It is a row 60 having a plurality of gates 62, where each gate 62 stands on an ONO column 32′. Each gate 62 may comprise a gate 34′ of first polysilicon and an extension 47′ of second polysilicon. For clarity, FIG. 3I does not show bit line oxides 43 between gates 62.


It will be appreciated that polysilicon gates 62 overlap bit lines 50, irrespective of any variation in side diffusion of bit lines 50. Moreover, bit line oxides 43 may be blocked and self-aligned to polysilicon gates 62. Furthermore, word lines 56 may extend above and perpendicular to buried diffusion bit lines 50, which may be insulated from them by blocked bit line oxides 43.


In another embodiment, the step of depositing silicide layer 55 may be replaced with a much later salicide (self aligned silicidation) process (step 132)


The layout of the array may be seen more clearly in FIG. 4A. As can be seen, hard mask 33 may be laid out in columns with spacers 42 to their sides. Pocket implant 41 may be present at least under spacers 42. Due to the scattering and side diffusion of pocket implant 41, the edge of pocket implant 41 may also have a tail (not shown) under the area defined by hard mask 33. First polysilicon columns 34 and ONO columns 32′ may have a width equivalent to the combined width of mask 33 and spacers 42.


Bit lines 50 may be implanted between the columns and may be covered by oxide filler 52. Once hard mask 33 may be removed, word lines 56 may be laid out in rows, extending into the columns between bit lines 50. As can be seen, when word lines 56 may be etched, the polysilicon between rows 56 may be etched, leaving polysilicon gates 62, formed of first and second polysilicon.


Gates 62 may form the gates of each NROM cell and they are connected together in a row via rows 60. In addition, polysilicon layers 34 and 54 may form the gates, and possibly some interconnections, in the CMOS periphery.


A sidewall oxide 58 (FIG. 4B) may optionally be generated (step 125) to cover the word line surfaces that may be exposed as a result of etch step 124.


In step 126, lightly doped drain (LDD) implants for the CMOS transistors may be implanted. There is typically one mask for the n-LDD implants (for n-channel devices) and another mask for the p-LDD implants (for p-channel devices). Both implants may be of 1-5×1013/cm2.


A thin oxide liner or partial spacer, of about 10-20 nm, may then be deposited (step 127), along and between word lines 56. This liner may serve as part of the CMOS spacer and may be completed after implanting of an anti-punchthrough implant 59 (step 128). However, if salicidation of word lines 56 is desired (as shown in step 132), an oxide spacer may be preferred in order to remove the oxide covering word lines 56 and to enable word lines 56 to be salicidized.


In step 128, an anti-punchthrough implant 59 may be generated in the spaces between bit lines 50 not covered by word lines 56. An exemplary anti-punchthrough implant may be of Boron (B) of 15 Kev at 5×1012/cm2 or 30 Kev at 3×1012/cm2. Alternatively, the anti-punchthrough implant may comprise a multiplicity of implants with different energies and doses in the same location. For example, there might be three consecutive implants of Boron, of 5×1012 at 15 Kev, 3×1012 at 25 Kev and 3×1012 at 35 Kev. Alternatively, the Boron may be replaced by BF2 or Indium.


Finally, oxide spacers may be created (step 130) for the transistors in the CMOS periphery. The spacers may cover the entire wafer and may fill or partially fill between word lines 56, providing an insulation between word lines 56. In step 132, a salicide process (i.e. self-aligned silicidation), such as is known in the art, may be optionally performed on the chip if second polysilicon layer 54 was not covered with silicide layer 55. This process may cause salicidation of the polysilicon throughout the chip which may reduce the resistances of the word lines and of the CMOS junctions.


Reference is now made to FIGS. 5A and 5B, which illustrate an alternative embodiment of the method of the present invention and to FIG. 6, which may illustrate the array after the CMP step 118. In this embodiment, steps 100-112 remain the same. However, the polysilicon etch of step 113 may be set to leave most of the top oxide layer intact and a step 140 may be added to remove hard mask 33 and spacers 42 before the implantation (in step 115) of bit lines 50. As a result and as shown in FIG. 6, CMP step 118 may trim bit line oxide 52 back to the height of polysilicon columns 34, rather than to the combined height of polysilicon columns 34 and hard mask 33, as in FIG. 3G of the previous embodiment.


Reference is now made to FIGS. 7A and 7B, which illustrate a further alternative embodiment of the method of the present invention and to FIG. 8, which may illustrate the array after the addition of a protective spacer 144. In this embodiment, steps 100-112 remain the same. However, there are two etch steps, as in the first embodiment of FIG. 2A, a polysilicon etch (step 113) and an ONO etch (step 114) to bottom oxide 36.


In order to protect the edge of the nitride layer from removal during the removal of hard mask 33, which, in this embodiment is of nitride, a protective oxide spacer 144 may be created (step 142). Spacer 144 may be relatively thin, such as of 5-8 nm, and may create a slightly smaller bit line opening 37′ for implantation and rapid thermal anneal (step 115) of bit lines 50. Spacer 144 may also be used to optimize the overlap of pocket implants 41 to bit lines 50 for better control of the punchthrough and reliability of the device.


After the implantation, hard mask 33 and spacers 42 may be removed (step 140A), leaving oxide spacers 144, after which oxide may be deposited (step 116) to fill bit line openings 37′. Oxide spacers 144 may become part of bit line oxides 43 covering bit lines 50. CMP step 118 may trim oxide fill 52 and oxide spacers 144 back to the height of polysilicon columns 34.


Reference is now made to FIGS. 9A and 9B, which illustrate an alternative embodiment of the present invention also providing a super-lithographic width polysilicon layer. Reference is also made to FIGS. 10A-10D which show the results of various steps of FIG. 9A and to FIGS. 11A -11C, which show the results of the word line etch of FIG. 9B.


The first steps of this embodiment are similar to steps 100-102 of the previous embodiment.


In step 206, a first polysilicon layer may be laid down over the entire chip as in the first embodiment. A SiON (silicon oxynitride) or nitride hard mask 336, of 20-50 nm, may then be deposited in a column pattern covering the areas of the memory array not destined to be bit lines. An etch may be performed (step 208) to generate bit line openings 337 by removing the areas of polysilicon layer between columns of hard mask layer 336. The etching step typically may remove polysilicon and may be set to remove none or a minimum of the top layer of ONO layer 332. FIG. 10A shows the results of the etch process for one embodiment of the present invention. Two columns 334 of polysilicon and hard mask 336 are shown on top of ONO layer 332.


A pocket implant 341, as in the previous embodiment, may now be implanted (step 210) between polysilicon columns 334 and through ONO layer 332.


In step 212, polysilicon spacers 342 may be generated on the sides of polysilicon columns 334 to decrease the width of bit line openings, labeled 337′ in FIG. 10B. Polysilicon spacers 342 may be formed by depositing polysilicon in bit line openings 337 and then etching them back anisotropically with a polysilicon etch. The etch may be set to stop on either the top or the bottom oxide of ONO layer 332. FIG. 10B shows the first embodiment, with no etching of ONO layer 332.


Once spacers 342 have been formed, bit lines 350 may be implanted (step 214), as in the previous embodiment, within reduced bit line openings 337′. In step 216, an oxide filler 352 may be deposited on the chip to fill reduced bit line openings 337′ and may cover other parts of the chip.


It will be appreciated that polysilicon spacers 342 may cover pocket implants 341 and may provide an overlap of the gate (to be formed from polysilicon column 334 and polysilicon spacers 342) over the junction


In step 218, a CMP process may be performed to remove the excess oxide filler 352 as well as hard mask 336 and a top portion 341 of spacer 342 from the top of the chip. The result of step 218 is shown as a sectional view in FIG. 10C. As can be seen, the planarization may be designed to remove material until it reaches the top of polysilicon 334.


A second polysilicon layer 354 and a coating 372 of SiON may then be deposited (step 220) on the array. The result of step 220 is shown in FIG. 10D. SiON 372 and second polysilicon 354 may now be etched (step 221) into word lines, which, as in the previous embodiment, may be in rows perpendicular to the bit line columns. It will be appreciated that the word line etch operation (step 221) must etch through SiON coating 372, second polysilicon 354, first polysilicon 334 and polysilicon spacer 342, down to ONO layer 332.


Since polysilicon spacers 342 may be at least partially covered by the oxide filler, otherwise known as “bit line oxide” 352, step 221 may be divided into three etch operations, a first etch (step 222) of SiON coating 372 and second polysilicon 354, a bit line oxide etch (step 223) to expose the rounded edges of polysilicon spacer 342 and a second polysilicon etch (step 224) to etch both the first polysilicon layer 334 and polysilicon spacers 342 into islands. The results of steps 222, 223 and 224 are shown in FIGS. 11A, 11B and 11C, respectively, which are expanded, isometric views of the array.


As can be seen in FIG. 11A, first etch (step 222) of SiON coating 372 and second polysilicon 354 may generate rows 356 of second polysilicon 345 and SiON coating 372. The etch may be set to stop on first polysilicon 334 or it may be a timed etch designed not to go through first polysilicon 334.


Between rows 356, bit line oxides 352 may be exposed alongside first polysilicon 334. Unfortunately, as shown in FIG. 11A, at least a portion of an upper surface 343 of polysilicon spacer 342 may be partially masked by bit line oxide 352 and thus, polysilicon spacer 342 would not have been reliably etched in a single polysilicon etch operation.



FIG. 11B illustrates the result of the oxide etch of step 223. In an exemplary embodiment, 20-30 nm of bit line oxide 352 may be removed, leaving about 30-70 nm of reduced bit line oxide, here labeled 352′, above ONO 332. Reduced bit line oxide 352′ may serve to protect bit line 350 during the polysilicon etch of step 224. It is noted that there may now be two bit line oxide thickness, that of bit line oxide 352 under the word line and that of reduced bit line oxide 352′ between word lines.


The removal of a portion of bit line oxide 352 may expose upper surfaces 343 of spacers 342 in rows between word lines 356, such that spacers 342 may now be etched (step 224) between rows 256, together with first polysilicon columns 334.



FIG. 11C illustrates the result of step 224. ONO layer 332 has been exposed where not covered by reduced bit line oxide 352′ and polysilicon columns 334 and spacers 342 have been formed into super-lithographic width polysilicon gates 334′ which connect between channel 374 and polysilicon rows 356.


The process may now continue as in the first embodiment, from step 125 of FIG. 2B.


While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims
  • 1. A non-volatile memory array comprising: columns of channels in a semiconductor substrate; columns of junctions at the edges of said channels; columns of diffusion bit lines between said junctions; polysilicon gates over charge trapping dielectric over said portions of said channels and overlapping at least portions of said junctions; a polysilicon spacer which forms at least a portion of said polysilicon gates; and bit line oxides extending to a height of said polysilicon gates under polysilicon word lines and are shorter than a height between said polysilicon word lines.
  • 2. The array according to claim 1 and wherein said junctions are pocket implants.
  • 3. The array according to claim 1 and wherein said polysilicon gates are at least partially formed of a first polysilicon layer and at least a portion of a polysilicon spacer.
  • 4. The array according to claim 1 and wherein said polysilicon gates are at least partially formed of a first polysilicon layer.
  • 5. The array according to claim 1 and further comprising bit line oxides extending to a height above said polysilicon gates.
  • 6. The array according to claim 1 and further comprising bit line oxides extending to a height of said polysilicon gates.
  • 7. The array according to claim 1 and further comprising bit line oxides next to said polysilicon gates and said oxides being wider at a top thereof than at a bottom thereof.
CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part application claiming benefit from U.S. patent application Ser. No. 11/247,733, filed Oct. 11, 2005, which application claims benefit from U.S. Provisional Patent Application 60/618,165, filed Oct. 14, 2004, which applications are hereby incorporated in their entirety by reference.

US Referenced Citations (550)
Number Name Date Kind
3881180 Gosney, Jr. Apr 1975 A
3895360 Cricchi et al. Jul 1975 A
3952325 Beale et al. Apr 1976 A
4016588 Ohya et al. Apr 1977 A
4017888 Christie et al. Apr 1977 A
4145703 Blanchard et al. Mar 1979 A
4151021 McElroy Apr 1979 A
4173766 Hayes Nov 1979 A
4173791 Bell Nov 1979 A
4247861 Hsu et al. Jan 1981 A
4257832 Schwabe et al. Mar 1981 A
4281397 Neal et al. Jul 1981 A
4306353 Jacobs et al. Dec 1981 A
4342102 Puar Jul 1982 A
4342149 Jacobs et al. Aug 1982 A
4360900 Bate Nov 1982 A
4373248 McElroy Feb 1983 A
4380057 Kotecha et al. Apr 1983 A
4388705 Sheppard Jun 1983 A
4389705 Sheppard Jun 1983 A
4404747 Collins Sep 1983 A
4435786 Tickle Mar 1984 A
4448400 Harari May 1984 A
4471373 Shimizu et al. Sep 1984 A
4494016 Ransom et al. Jan 1985 A
4507673 Aoyama Mar 1985 A
4521796 Rajkanan et al. Jun 1985 A
4527257 Cricchi Jul 1985 A
4586163 Koike Apr 1986 A
4613956 Paterson et al. Sep 1986 A
4630085 Koyama Dec 1986 A
4663645 Komori et al. May 1987 A
4665426 Allen et al. May 1987 A
4667217 Janning May 1987 A
4672409 Takei et al. Jun 1987 A
4725984 Ip et al. Feb 1988 A
4733105 Shin et al. Mar 1988 A
4742491 Liang et al. May 1988 A
4758869 Eitan et al. Jul 1988 A
4760555 Gelsomini et al. Jul 1988 A
4761764 Watanabe Aug 1988 A
4769340 Chang et al. Sep 1988 A
4780424 Holler et al. Oct 1988 A
4839705 Tigelaar et al. Jun 1989 A
4847808 Kobatake Jul 1989 A
4857770 Partovi et al. Aug 1989 A
4870470 Bass, Jr. et al. Sep 1989 A
4888735 Lee et al. Dec 1989 A
4916671 Ichiguchi Apr 1990 A
4941028 Chen et al. Jul 1990 A
4961010 Davis Oct 1990 A
4992391 Wang Feb 1991 A
5021999 Kohda et al. Jun 1991 A
5027321 Park Jun 1991 A
5029063 Lingstaedt et al. Jul 1991 A
5042009 Kazerounian et al. Aug 1991 A
5075245 Woo et al. Dec 1991 A
5081371 Wong Jan 1992 A
5086325 Schumann et al. Feb 1992 A
5094968 Schumann et al. Mar 1992 A
5104819 Freiberger et al. Apr 1992 A
5117389 Yiu May 1992 A
5120672 Mitchell et al. Jun 1992 A
5142495 Canepa Aug 1992 A
5142496 Van Buskirk Aug 1992 A
5159570 Mitchell et al. Oct 1992 A
5168334 Mitchell et al. Dec 1992 A
5172338 Mehrotra et al. Dec 1992 A
5175120 Lee Dec 1992 A
5204835 Eitan Apr 1993 A
5214303 Aoki May 1993 A
5237213 Tanoi Aug 1993 A
5241497 Komarek Aug 1993 A
5260593 Lee Nov 1993 A
5268861 Hotta Dec 1993 A
5276646 Kim et al. Jan 1994 A
5280420 Rapp Jan 1994 A
5289412 Frary et al. Feb 1994 A
5293563 Ohta Mar 1994 A
5295092 Hotta et al. Mar 1994 A
5295108 Higa Mar 1994 A
5305262 Yoneda Apr 1994 A
5311049 Tsuruta May 1994 A
5315541 Harari et al. May 1994 A
5324675 Hayabuchi Jun 1994 A
5334555 Sugiyama et al. Aug 1994 A
5335198 Van Buskirk et al. Aug 1994 A
5338954 Shimoji Aug 1994 A
5345425 Shikatani Sep 1994 A
5349221 Shimoji Sep 1994 A
5350710 Hong et al. Sep 1994 A
5352620 Komori et al. Oct 1994 A
5357134 Shimoji Oct 1994 A
5359554 Odake et al. Oct 1994 A
5361343 Kosonocky et al. Nov 1994 A
5366915 Kodama Nov 1994 A
5375094 Naruke Dec 1994 A
5381374 Shiraishi et al. Jan 1995 A
5393701 Ko et al. Feb 1995 A
5394355 Uramoto et al. Feb 1995 A
5399891 Yiu et al. Mar 1995 A
5400286 Chu et al. Mar 1995 A
5402374 Tsuruta et al. Mar 1995 A
5412601 Sawada et al. May 1995 A
5414693 Ma et al. May 1995 A
5418176 Yang et al. May 1995 A
5418743 Tomioka et al. May 1995 A
5422844 Wolstenholme et al. Jun 1995 A
5424567 Chen Jun 1995 A
5424978 Wada et al. Jun 1995 A
5426605 Van Berkel et al. Jun 1995 A
5434825 Harari et al. Jul 1995 A
5436478 Bergemont et al. Jul 1995 A
5436481 Egawa et al. Jul 1995 A
5440505 Fazio et al. Aug 1995 A
5450341 Sawada et al. Sep 1995 A
5450354 Sawada et al. Sep 1995 A
5455793 Amin et al. Oct 1995 A
5467308 Chang et al. Nov 1995 A
5477499 Van Buskirk et al. Dec 1995 A
5495440 Asakura Feb 1996 A
5496753 Sakurai et al. Mar 1996 A
5508968 Collins et al. Apr 1996 A
5518942 Shrivastava May 1996 A
5521870 Ishikawa May 1996 A
5523251 Hong Jun 1996 A
5523972 Rashid et al. Jun 1996 A
5530803 Chang et al. Jun 1996 A
5534804 Woo Jul 1996 A
5537358 Fong Jul 1996 A
5544116 Chao et al. Aug 1996 A
5553018 Wang et al. Sep 1996 A
5553030 Tedrow et al. Sep 1996 A
5557221 Taguchi et al. Sep 1996 A
5557570 Iwahashi Sep 1996 A
5559687 Nicollini et al. Sep 1996 A
5563823 Yiu et al. Oct 1996 A
5568085 Eitan et al. Oct 1996 A
5579199 Kawamura et al. Nov 1996 A
5581252 Thomas Dec 1996 A
5583808 Brahmbhatt Dec 1996 A
5590068 Bergemont Dec 1996 A
5590074 Akaogi et al. Dec 1996 A
5592417 Mirabel Jan 1997 A
5596527 Tomioka et al. Jan 1997 A
5599727 Hakozaki et al. Feb 1997 A
5600586 Lee et al. Feb 1997 A
5606523 Mirabel Feb 1997 A
5608679 Mi et al. Mar 1997 A
5612642 McClinyock Mar 1997 A
5617357 Haddad et al. Apr 1997 A
5623438 Guritz et al. Apr 1997 A
5627790 Golla et al. May 1997 A
5633603 Lee May 1997 A
5636288 Bonneville et al. Jun 1997 A
5644531 Kuo et al. Jul 1997 A
5654568 Nakao Aug 1997 A
5656513 Wang et al. Aug 1997 A
5657332 Auclair et al. Aug 1997 A
5661060 Gill et al. Aug 1997 A
5663907 Frayer et al. Sep 1997 A
5672959 Der Sep 1997 A
5675280 Nomura Oct 1997 A
5677867 Hazani Oct 1997 A
5677869 Fazio et al. Oct 1997 A
5683925 Irani et al. Nov 1997 A
5689459 Chang et al. Nov 1997 A
5694356 Wong et al. Dec 1997 A
5696929 Hasbun et al. Dec 1997 A
5708608 Park et al. Jan 1998 A
5712814 Fratin et al. Jan 1998 A
5712815 Bill et al. Jan 1998 A
5715193 Norman Feb 1998 A
5717581 Canclini Feb 1998 A
5717632 Richart et al. Feb 1998 A
5717635 Akatsu Feb 1998 A
5726946 Yamagata et al. Mar 1998 A
5748534 Dunlap et al. May 1998 A
5751037 Aozasa et al. May 1998 A
5751637 Chen et al. May 1998 A
5754475 Bill et al. May 1998 A
5760445 Diaz Jun 1998 A
5760634 Fu Jun 1998 A
5768192 Eitan Jun 1998 A
5768193 Lee et al. Jun 1998 A
5771197 Kim Jun 1998 A
5774395 Richart et al. Jun 1998 A
5777919 Chi-Yung et al. Jul 1998 A
5781476 Seki et al. Jul 1998 A
5781478 Takeuchi et al. Jul 1998 A
5783934 Tran Jul 1998 A
5784314 Sali et al. Jul 1998 A
5787036 Okazawa Jul 1998 A
5793079 Georgescu et al. Aug 1998 A
5801076 Ghneim et al. Sep 1998 A
5805500 Campardo et al. Sep 1998 A
5808506 Tran Sep 1998 A
5812449 Song Sep 1998 A
5812456 Hull et al. Sep 1998 A
5812457 Arase Sep 1998 A
5815435 Van Tran Sep 1998 A
5822256 Bauer et al. Oct 1998 A
5825683 Chang et al. Oct 1998 A
5825686 Schmitt-Landsiedel et al. Oct 1998 A
5828601 Hollmer et al. Oct 1998 A
5834851 Ikeda et al. Nov 1998 A
5835935 Estakhri et al. Nov 1998 A
5836772 Chang et al. Nov 1998 A
5841700 Chang Nov 1998 A
5847441 Cutter et al. Dec 1998 A
5861771 Matsuda et al. Jan 1999 A
5862076 Eitan Jan 1999 A
5864164 Wen Jan 1999 A
5867429 Chen et al. Feb 1999 A
5870334 Hemink et al. Feb 1999 A
5870335 Khan et al. Feb 1999 A
5875128 Ishizuka et al. Feb 1999 A
5877537 Aoki Mar 1999 A
5880620 Gitlin et al. Mar 1999 A
5886927 Takeuchi Mar 1999 A
RE36179 Shimoda Apr 1999 E
5892710 Fazio et al. Apr 1999 A
5903031 Yamada et al. May 1999 A
5910924 Tanaka et al. Jun 1999 A
5920503 Lee et al. Jul 1999 A
5920507 Takeuchi et al. Jul 1999 A
5926409 Engh et al. Jul 1999 A
5930195 Komatsu et al. Jul 1999 A
5933366 Yoshikawa Aug 1999 A
5933367 Matsuo et al. Aug 1999 A
5936888 Sugawara Aug 1999 A
5940332 Artieri Aug 1999 A
5946258 Evertt et al. Aug 1999 A
5946558 Hsu Aug 1999 A
5949714 Hemink et al. Sep 1999 A
5949728 Liu et al. Sep 1999 A
5963412 En Oct 1999 A
5963465 Eitan Oct 1999 A
5966603 Eitan Oct 1999 A
5969989 Iwahashi Oct 1999 A
5969993 Takeshima Oct 1999 A
5973373 Krautschneider et al. Oct 1999 A
5982666 Campardo Nov 1999 A
5986940 Atsumi et al. Nov 1999 A
5990526 Bez et al. Nov 1999 A
5991202 Derhacobian et al. Nov 1999 A
5999444 Fujiwara et al. Dec 1999 A
5999494 Holzrichter Dec 1999 A
6000006 Bruce et al. Dec 1999 A
6005423 Schultz Dec 1999 A
6011725 Eitan Jan 2000 A
6018186 Hsu Jan 2000 A
6020241 You et al. Feb 2000 A
6028324 Su et al. Feb 2000 A
6030871 Eitan Feb 2000 A
6034403 Wu Mar 2000 A
6034896 Ranaweera et al. Mar 2000 A
6037627 Kitamura et al. Mar 2000 A
6040610 Noguchi et al. Mar 2000 A
6044019 Cernea et al. Mar 2000 A
6044022 Nachumovsky Mar 2000 A
6063666 Chang et al. May 2000 A
6064226 Earl May 2000 A
6064251 Park May 2000 A
6064591 Takeuchi et al. May 2000 A
6074916 Cappelletti Jun 2000 A
6075402 Ghilardelli Jun 2000 A
6075724 Li et al. Jun 2000 A
6078518 Chevallier Jun 2000 A
6081456 Dadashev Jun 2000 A
6084794 Lu et al. Jul 2000 A
6091640 Kawahara et al. Jul 2000 A
6094095 Murray et al. Jul 2000 A
6097639 Choi et al. Aug 2000 A
6107862 Mukainakano et al. Aug 2000 A
6108240 Lavi et al. Aug 2000 A
6108241 Chevallier Aug 2000 A
6117714 Beatty Sep 2000 A
6118207 Ormerod et al. Sep 2000 A
6118692 Banks Sep 2000 A
6122198 Haddad et al. Sep 2000 A
6128226 Eitan et al. Oct 2000 A
6128227 Kim Oct 2000 A
6130572 Ghilardelli et al. Oct 2000 A
6130574 Bloch et al. Oct 2000 A
6133095 Eitan et al. Oct 2000 A
6134156 Eitan Oct 2000 A
6137718 Reisinger Oct 2000 A
6147904 Liron Nov 2000 A
6150800 Kinoshita et al. Nov 2000 A
6154081 Pakkala et al. Nov 2000 A
6156149 Cheung et al. Dec 2000 A
6157242 Fukui Dec 2000 A
6157570 Nachumovsky Dec 2000 A
6163048 Hirose et al. Dec 2000 A
6163484 Uekubo Dec 2000 A
6169691 Pasotti et al. Jan 2001 B1
6171909 Ding et al. Jan 2001 B1
6175523 Yang et al. Jan 2001 B1
6181597 Nachumovsky Jan 2001 B1
6181605 Hollmer et al. Jan 2001 B1
6185143 Perner et al. Feb 2001 B1
6188211 Rincon-Mora et al. Feb 2001 B1
6190966 Ngo et al. Feb 2001 B1
6192445 Rezvani Feb 2001 B1
6195196 Kimura et al. Feb 2001 B1
6198342 Kawai Mar 2001 B1
6201282 Eitan Mar 2001 B1
6201737 Hollmer et al. Mar 2001 B1
6205056 Pan et al. Mar 2001 B1
6205059 Gutala et al. Mar 2001 B1
6208200 Arakawa Mar 2001 B1
6208557 Bergemont et al. Mar 2001 B1
6214666 Mehta Apr 2001 B1
6215148 Eitan Apr 2001 B1
6215697 Lu et al. Apr 2001 B1
6215702 Derhacobian et al. Apr 2001 B1
6218695 Nachumovsky Apr 2001 B1
6219277 Devin et al. Apr 2001 B1
6219290 Chang et al. Apr 2001 B1
6222762 Guterman et al. Apr 2001 B1
6222768 Hollmer et al. Apr 2001 B1
6233180 Eitan et al. May 2001 B1
6240032 Fukumoto May 2001 B1
6240040 Akaogi et al. May 2001 B1
6246555 Tham Jun 2001 B1
6252442 Malherbe Jun 2001 B1
6252799 Liu et al. Jun 2001 B1
6256231 Lavi et al. Jul 2001 B1
6261904 Pham et al. Jul 2001 B1
6265268 Halliyal et al. Jul 2001 B1
6266281 Derhacobian et al. Jul 2001 B1
6272047 Mihnea et al. Aug 2001 B1
6275414 Randolph et al. Aug 2001 B1
6281545 Liang et al. Aug 2001 B1
6282133 Nakagawa et al. Aug 2001 B1
6282145 Tran et al. Aug 2001 B1
6285246 Basu Sep 2001 B1
6285574 Eitan Sep 2001 B1
6285589 Kajitani Sep 2001 B1
6285614 Mulatti et al. Sep 2001 B1
6292394 Cohen et al. Sep 2001 B1
6297096 Boaz Oct 2001 B1
6297143 Foote et al. Oct 2001 B1
6297974 Ganesan et al. Oct 2001 B1
6304485 Harari et al. Oct 2001 B1
6307784 Hamilton et al. Oct 2001 B1
6307807 Sakui et al. Oct 2001 B1
6320786 Chang et al. Nov 2001 B1
6324094 Chevallier Nov 2001 B1
6326265 Liu et al. Dec 2001 B1
6330192 Ohba et al. Dec 2001 B1
6331950 Kuo et al. Dec 2001 B1
6335874 Eitan Jan 2002 B1
6337502 Eitan et al. Jan 2002 B1
6339556 Watanabe Jan 2002 B1
6343033 Parker Jan 2002 B1
6346442 Aloni et al. Feb 2002 B1
6348381 Jong Feb 2002 B1
6348711 Eitan Feb 2002 B1
6351415 Kushnarenko Feb 2002 B1
6353356 Liu Mar 2002 B1
6353554 Banks Mar 2002 B1
6353555 Jeong Mar 2002 B1
6356469 Roohparvar et al. Mar 2002 B1
6359501 Lin et al. Mar 2002 B2
6374337 Estakhri Apr 2002 B1
6385086 Mihara et al. May 2002 B1
6396741 Bloom et al. May 2002 B1
6400209 Matsuyama et al. Jun 2002 B1
6400607 Pasotti et al. Jun 2002 B1
6407537 Antheunis Jun 2002 B2
6410388 Kluth et al. Jun 2002 B1
6417081 Thurgate Jul 2002 B1
6418506 Pashley et al. Jul 2002 B1
6426898 Mihnea et al. Jul 2002 B1
6429063 Eitan Aug 2002 B1
6433624 Grossnikle et al. Aug 2002 B1
6436766 Rangarajan et al. Aug 2002 B1
6436768 Yang et al. Aug 2002 B1
6438031 Fastow Aug 2002 B1
6438035 Yamamoto et al. Aug 2002 B2
6440797 Wu et al. Aug 2002 B1
6442074 Hamilton et al. Aug 2002 B1
6445030 Wu et al. Sep 2002 B1
6449188 Fastow Sep 2002 B1
6449190 Bill Sep 2002 B1
6452438 Li Sep 2002 B1
6456528 Chen Sep 2002 B1
6456533 Hamilton et al. Sep 2002 B1
6458656 Park et al. Oct 2002 B1
6458677 Hopper et al. Oct 2002 B1
6469929 Kushnarenko et al. Oct 2002 B1
6469935 Hayashi Oct 2002 B2
6472706 Widdershoven et al. Oct 2002 B2
6477085 Kuo Nov 2002 B1
6490204 Bloom et al. Dec 2002 B2
6496414 Kasa et al. Dec 2002 B2
6504756 Gonzalez et al. Jan 2003 B2
6510082 Le et al. Jan 2003 B1
6512701 Hamilton et al. Jan 2003 B1
6519180 Tran et al. Feb 2003 B2
6519182 Derhacobian et al. Feb 2003 B1
6522585 Pasternak Feb 2003 B2
6525969 Kurihara et al. Feb 2003 B1
6528390 Komori et al. Mar 2003 B2
6529412 Chen et al. Mar 2003 B1
6532173 Lioka et al. Mar 2003 B2
6535020 Yin Mar 2003 B1
6535434 Maayan et al. Mar 2003 B2
6537881 Rangarjan et al. Mar 2003 B1
6538270 Randolph et al. Mar 2003 B1
6541816 Ramsbey et al. Apr 2003 B2
6552387 Eitan Apr 2003 B1
6555436 Ramsbey et al. Apr 2003 B2
6559500 Torii May 2003 B2
6562683 Wang et al. May 2003 B1
6566194 Ramsbey et al. May 2003 B1
6566699 Eitan May 2003 B2
6567303 Hamilton et al. May 2003 B1
6567312 Torii et al. May 2003 B1
6570211 He et al. May 2003 B1
6574139 Kurihara Jun 2003 B2
6577514 Shor et al. Jun 2003 B2
6577532 Chevallier Jun 2003 B1
6577547 Ukon Jun 2003 B2
6583005 Hashimoto et al. Jun 2003 B2
6583479 Fastow et al. Jun 2003 B1
6584017 Maayan et al. Jun 2003 B2
6590811 Hamilton et al. Jul 2003 B1
6593606 Randolph et al. Jul 2003 B1
6594181 Yamada Jul 2003 B1
6608526 Sauer Aug 2003 B1
6614052 Zhang Sep 2003 B1
6614295 Tsuchi Sep 2003 B2
6614686 Kawamura Sep 2003 B1
6614692 Maayan et al. Sep 2003 B2
6617179 Kim Sep 2003 B1
6617215 Halliyal et al. Sep 2003 B1
6618290 Wang et al. Sep 2003 B1
6624672 Confaloneri et al. Sep 2003 B2
6627555 Eitan et al. Sep 2003 B2
6630384 Sun et al. Oct 2003 B1
6633496 Maayan et al. Oct 2003 B2
6633499 Eitan et al. Oct 2003 B1
6633956 Mitani Oct 2003 B1
6636440 Maayan et al. Oct 2003 B2
6639271 Zheng et al. Oct 2003 B1
6639837 Takano et al. Oct 2003 B2
6639844 Liu et al. Oct 2003 B1
6639849 Takahashi et al. Oct 2003 B2
6642148 Ghandehari et al. Nov 2003 B1
6642573 Halliyal et al. Nov 2003 B1
6642586 Takahashi Nov 2003 B2
6643170 Huang et al. Nov 2003 B2
6643177 Le et al. Nov 2003 B1
6643178 Kurihara Nov 2003 B2
6643181 Sofer et al. Nov 2003 B2
6645801 Ramsbey et al. Nov 2003 B1
6649972 Eitan Nov 2003 B2
6650568 Iijima Nov 2003 B2
6653190 Yang et al. Nov 2003 B1
6653191 Yang et al. Nov 2003 B1
6654296 Jang et al. Nov 2003 B2
6664588 Eitan Dec 2003 B2
6665769 Cohen et al. Dec 2003 B2
6670241 Kamal et al. Dec 2003 B1
6670669 Kawamura Dec 2003 B1
6674138 Halliyal et al. Jan 2004 B1
6677805 Shor et al. Jan 2004 B2
6680509 Wu et al. Jan 2004 B1
6686242 Willer et al. Feb 2004 B2
6690602 Le et al. Feb 2004 B1
6700818 Shappir et al. Mar 2004 B2
6717207 Kato Apr 2004 B2
6723518 Papsidero et al. Apr 2004 B2
6731542 Le et al. May 2004 B1
6738289 Gongwer et al. May 2004 B2
6744692 Shiota et al. Jun 2004 B2
6765259 Kim Jul 2004 B2
6768165 Eitan Jul 2004 B1
6781876 Forbes et al. Aug 2004 B2
6788579 Gregori et al. Sep 2004 B2
6791396 Shor et al. Sep 2004 B2
6794249 Palm et al. Sep 2004 B2
6794280 Chang Sep 2004 B2
6831872 Matsuoka Dec 2004 B2
6836431 Chang Dec 2004 B2
6871258 Micheloni et al. Mar 2005 B2
6885585 Maayan et al. Apr 2005 B2
6885590 Zheng et al. Apr 2005 B1
6912160 Yamada Jun 2005 B2
6917544 Maayan et al. Jul 2005 B2
6928001 Avni et al. Aug 2005 B2
6937523 Eshel Aug 2005 B2
6967872 Quader et al. Nov 2005 B2
6996692 Kuono Feb 2006 B2
7045849 Chen et al. May 2006 B2
7079420 Shappir et al. Jul 2006 B2
20010006477 Banks Jul 2001 A1
20020000606 Eitan Jan 2002 A1
20020004878 Norman Jan 2002 A1
20020004921 Muranaka et al. Jan 2002 A1
20020064911 Eitan May 2002 A1
20020132436 Eliyahu et al. Sep 2002 A1
20020140109 Keshavarzi et al. Oct 2002 A1
20020145465 Shor et al. Oct 2002 A1
20020145914 Ogura et al. Oct 2002 A1
20020191465 Maayan et al. Dec 2002 A1
20020199065 Subramoney et al. Dec 2002 A1
20030001213 Lai Jan 2003 A1
20030021155 Yachareni et al. Jan 2003 A1
20030072192 Bloom et al. Apr 2003 A1
20030076710 Sofer et al. Apr 2003 A1
20030117841 Yamashita Jun 2003 A1
20030131186 Buhr Jul 2003 A1
20030134476 Roizin et al. Jul 2003 A1
20030142544 Maayan et al. Jul 2003 A1
20030145176 Dvir et al. Jul 2003 A1
20030145188 Cohen et al. Jul 2003 A1
20030155659 Verma et al. Aug 2003 A1
20030190786 Ramsbey et al. Oct 2003 A1
20030197221 Shinozaki et al. Oct 2003 A1
20030202411 Yamada Oct 2003 A1
20030206435 Takahashi Nov 2003 A1
20030208663 Van Buskirk et al. Nov 2003 A1
20030209767 Takahashi et al. Nov 2003 A1
20030214844 Iijima Nov 2003 A1
20030218207 Hashimoto et al. Nov 2003 A1
20030218913 Le et al. Nov 2003 A1
20030222303 Fukuda et al. Dec 2003 A1
20030227796 Miki et al. Dec 2003 A1
20040012993 Kurihara Jan 2004 A1
20040013000 Torii Jan 2004 A1
20040014280 Willer et al. Jan 2004 A1
20040014290 Yang et al. Jan 2004 A1
20040021172 Zheng et al. Feb 2004 A1
20040027858 Takahashi et al. Feb 2004 A1
20040151034 Shor et al. Aug 2004 A1
20040153621 Polansky et al. Aug 2004 A1
20040157393 Hwang Aug 2004 A1
20040222437 Avni et al. Nov 2004 A1
20050020010 Hsu et al. Jan 2005 A1
20050117395 Maayan et al. Jun 2005 A1
20050140405 Do et al. Jun 2005 A1
20050232024 Atir et al. Oct 2005 A1
20050255651 Qian et al. Nov 2005 A1
20060084219 Lusky et al. Apr 2006 A1
20060126382 Maayan et al. Jun 2006 A1
20060126383 Shappir et al. Jun 2006 A1
Foreign Referenced Citations (68)
Number Date Country
0 656 628 Jun 1995 EP
0751560 Jun 1995 EP
0693781 Jan 1996 EP
0 822 557 Feb 1998 EP
0 843 398 May 1998 EP
0580467 Sep 1998 EP
0461764 Jul 2000 EP
1 071 096 Jan 2001 EP
1073120 Jan 2001 EP
1 091 418 Apr 2001 EP
1126468 Aug 2001 EP
0740307 Dec 2001 EP
1164597 Dec 2001 EP
1 207 552 May 2002 EP
1 223 586 Jul 2002 EP
1 365 452 Nov 2003 EP
001217744 Mar 2004 EP
1297899 Nov 1972 GB
2157489 Mar 1985 GB
54-053929 Apr 1979 JP
60-200566 Oct 1985 JP
60201594 Oct 1985 JP
63-249375 Oct 1988 JP
3-285358 Dec 1991 JP
04-226071 Aug 1992 JP
04-291962 Oct 1992 JP
05021758 Jan 1993 JP
06151833 May 1994 JP
06-232416 Aug 1994 JP
07193151 Jul 1995 JP
08-106791 Apr 1996 JP
08-297988 Nov 1996 JP
09-017981 Jan 1997 JP
09162314 Jun 1997 JP
10-106276 Apr 1998 JP
10 334676 Dec 1998 JP
11-162182 Jun 1999 JP
11-354758 Dec 1999 JP
2001-085646 Mar 2001 JP
2001-118392 Apr 2001 JP
2001-156189 Jun 2001 JP
2002-216488 Aug 2002 JP
3358663 Oct 2002 JP
WO 8100790 Mar 1981 WO
WO 9615553 May 1996 WO
WO 9625741 Aug 1996 WO
WO 9803977 Jan 1998 WO
WO 9931670 Jun 1999 WO
WO 9957728 Nov 1999 WO
WO 0046808 Aug 2000 WO
WO 0165566 Sep 2001 WO
WO 0165567 Sep 2001 WO
WO 0184552 Nov 2001 WO
WO 0243073 May 2002 WO
WO 03032393 Apr 2003 WO
WO 03036651 May 2003 WO
WO 03054964 Jul 2003 WO
WO 03063167 Jul 2003 WO
WO 03063168 Jul 2003 WO
WO 03079370 Sep 2003 WO
WO 03079446 Sep 2003 WO
WO 03083916 Oct 2003 WO
WO 03088258 Oct 2003 WO
WO 03088259 Oct 2003 WO
WO 03088260 Oct 2003 WO
WO 03088261 Oct 2003 WO
WO 03088353 Oct 2003 WO
WO 03100790 Dec 2003 WO
Related Publications (1)
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20060211188 A1 Sep 2006 US
Provisional Applications (1)
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60618165 Oct 2004 US
Continuation in Parts (1)
Number Date Country
Parent 11247733 Oct 2005 US
Child 11440624 US