Non-Volatile Semiconductor Memory and Manufacturing Process Thereof

Abstract

A non-volatile semiconductor memory which can suppress a leak current, improve dielectric strength and ensure large capacitance between a control gate and a floating gate and a manufacturing process thereof. A silicon nitride film is formed on the floating gate electrode layer of a memory cell and has a thickness of 5 nm or more. A high dielectric constant thin film is formed on the silicon nitride film. A control gate electrode layer is formed over the high dielectric constant thin film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the typical circuit configuration of a NAND type flash memory as a non-volatile semiconductor memory according to an embodiment of the present invention;

FIG. 2 is a schematic plan view showing the plan layout of the inside of the memory cell array of the NAND type flash memory as the non-volatile semiconductor memory according to the embodiment of the present invention;

FIG. 3 is a schematic sectional view cut on line III-III of FIG. 2;

FIG. 4 is a schematic sectional view cut on line IV-IV of FIG. 2;

FIGS. 5( a) and 5(b) are schematic sectional views showing a first step in the process of manufacturing a non-volatile semiconductor memory according to an embodiment of the present invention;

FIGS. 6( a) and 6(b) are schematic sectional views showing a second step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIGS. 7( a) and 7(b) are schematic sectional views showing a third step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIGS. 8( a) and 8(b) are schematic sectional views showing a fourth step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIGS. 9( a) and 9(b) are schematic sectional views showing a fifth step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIGS. 10( a) and 10(b) are schematic sectional views showing a sixth step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIGS. 11( a) and 11(b) are schematic sectional views showing a seventh step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIGS. 12( a) and 12(b) are schematic sectional views showing an eighth step in the process of manufacturing a non-volatile semiconductor memory according to the embodiment of the present invention;

FIG. 13 is a diagram showing the measurement of CVS-TDDB characteristics;

FIG. 14 is a diagram showing the measurement results of CVS-TDDB characteristics; and

FIG. 15 is a schematic sectional view in which the insulating layer between the high dielectric constant thin film and the control gate electrode layer is omitted.

Claims

1. A non-volatile semiconductor memory comprising: a substrate;a floating gate electrode layer formed over the substrate;a silicon nitride film formed on the floating gate electrode layer and having a thickness of 5 nm or more;a high dielectric constant thin film formed over the silicon nitride film; anda control gate electrode layer formed over the high dielectric constant thin film.

2. The non-volatile semiconductor memory according to claim 1, further comprising an insulating layer formed between the high dielectric constant thin film and the control gate electrode layer and having a wider band gap than that of the high dielectric constant thin film.

3. The non-volatile semiconductor memory according to claim 2, wherein the insulating layer is at least one of a silicon oxide film and a silicon nitride film.

4. The non-volatile semiconductor memory according to any one of claims 1 to 3, wherein the high dielectric constant thin film is made of at least one material selected from HfO2, Al2O3, Y2O3, MgO, Ta2O5, Bi2O3, BaMgF4, HfAlO, SrTiO3, PbTiO3, BaTiO3, BaSrTiO3, BSN, PZT and PLZT.

5. A manufacturing process of a non-volatile semiconductor memory, comprising the steps of: forming a floating gate conductive layer over a substrate;forming a silicon nitride film having a thickness of 5 nm or more on the floating gate conductive layer by thermal CVD;forming a high dielectric constant thin film over the silicon nitride film; andforming a control gate conductive layer over the high dielectric constant thin film.