Claims
- 1. A non-volatile semiconductor memory device comprising:
a first conductive semiconductor having a plurality of steps on a surface thereof; a second conductive semiconductor region formed on an upper portion and a bottom portion of each of said steps and being separated in a direction perpendicular to a main surface of said first conductive semiconductor to function as a source or a drain; a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on said first conductive semiconductor so as to coat at least a sidewall of each of said steps; and a gate electrode formed on said gate dielectric film.
- 2. The non-volatile semiconductor memory device according to claim 1, wherein a plurality of memory transistors each having said second conductive semiconductor region which functions as a source or drain region, said gate dielectric film, and said gate electrode are arranged in a matrix form, wherein:
said steps are formed to extend in a column direction at a predetermined interval in a row direction, said second conductive semiconductor region formed on the bottom portion of each of said steps and said second conductive semiconductor region formed on the upper portion of each of said steps are respectively disposed in and shared by two adjacent ones of said memory transistors in the row direction, and a plurality of said gate electrodes are arranged so as to extend in the row direction and are individually disposed between and shared by the memory transistors in the row direction and separated at a predetermined interval in the column direction.
- 3. The non-volatile semiconductor memory device according to claim 1, wherein said gate dielectric film comprises a lower dielectric film formed on said first conductive semiconductor, and a charge storage film formed on said lower dielectric film, wherein said charge storage film is comprised mainly of said charge storage means.
- 4. The non-volatile semiconductor memory device according to claim 3, wherein said lower dielectric film comprises a single film selected from or a laminated film comprised of two or more films selected from the group consisting of a silicon dioxide film, a silicon oxide nitride film which has no trap or does not have traps in an amount enough to change the threshold voltage of the transistor, a film comprised of an oxide of tantalum, titanium, zirconium, hafnium, lanthanum, or aluminum, and a film comprised of a silicate of tantalum, titanium, zirconium, hafnium, or lanthanum.
- 5. The non-volatile semiconductor memory device according to claim 3, wherein said charge storage film comprises a single film selected from or a laminated film comprised of two or more films selected from the group consisting of a silicon nitride film, a silicon oxide nitride film, a film comprised of an oxide of tantalum, titanium, zirconium, hafnium, lanthanum, or aluminum, and a film comprised of a silicate of tantalum, titanium, zirconium, hafnium, or lanthanum.
- 6. The non-volatile semiconductor memory device according to claim 1, wherein said gate dielectric film contains therein, as said charge storage means, a plurality of small particle-size conductors which are insulated from one another.
- 7. The non-volatile semiconductor memory device according to claim 3, wherein said gate dielectric film comprises an upper dielectric film formed on said charge storage film.
- 8. The non-volatile semiconductor memory device according to claim 7, wherein said upper dielectric film comprises a single film selected from or a laminated film comprised of two or more films selected from the group consisting of a silicon dioxide film, a silicon oxide nitride film which has no trap or does not have traps in an amount enough to change the threshold voltage of the transistor, a film comprised of an oxide of tantalum, titanium, zirconium, hafnium, lanthanum, or aluminum, and a film comprised of a silicate of tantalum, titanium, zirconium, hafnium, or lanthanum.
- 9. A process for fabricating a non-volatile semiconductor memory device, said process comprising the steps of:
forming a plurality of steps on a main surface of a first conductive semiconductor; forming a gate dielectric film on said first conductive semiconductor so as to coat at least a sidewall of each of said steps, wherein said gate dielectric film contains therein charge storage means which is spatially discrete; introducing a second conductive impurity into said first conductive semiconductor having said steps to form, on an upper portion and a bottom portion of each of said steps, a second conductive semiconductor region which functions as a source or a drain; and depositing a conductive film on said gate dielectric film and processing the resultant conductive film to form a gate electrode.
- 10. A process for fabricating a non-volatile semiconductor memory device, said process comprising the steps of:
forming a plurality of steps on a main surface of a first conductive semiconductor; introducing a second conductive impurity into said first conductive semiconductor having said steps to form, on an upper portion and a bottom portion of each of said steps, a second conductive semiconductor region which functions as a source or a drain; forming a gate dielectric film on said first conductive semiconductor so as to coat at least a sidewall of each said steps, wherein said gate dielectric film contains therein charge storage means which is spatially discrete; and depositing a conductive film on said gate dielectric film and processing the resultant conductive film to form a gate electrode.
Priority Claims (1)
Number |
Date |
Country |
Kind |
P2001-079123 |
Mar 2001 |
JP |
|
CROSS REFERENCES TO RELATED APPLICATIONS
[0001] The present document is based on Japanese Priority Document JP 2001-079123, filed in the Japanese Patent Office on Mar. 19, 2001, the entire contents of which being incorporated herein by reference.