Claims
- 1. An electrically programmable semiconductor memory device comprising:
- a semiconductive substrate;
- a plurality of data storage transistors formed in a surface area of said substrate and including a plurality of transistors coupled to each other in series each having an insulated carrier storage layer and a control gate disposed over and insulated from said carrier storage layer;
- a plurality of bit lines one of which is coupled to said plurality of transistors;
- first switch means connected to said plurality of transistors at a first node thereof, for selectively coupling said plurality of transistors to the one bit line;
- second switch means connected to said plurality of transistors at a second node thereof for selectively coupling said plurality of transistors to a source potential;
- program means for, while sequentially programming said plurality of transistors, changing an amount of charge carriers stored in the carrier storage layer of a selected transistor of said plurality of transistors by tunneling to cause said selected transistor to be programmed with given data, said program means causing said first switch means and said second switch means to turn on applying a first voltage to the one bit line, applying a second voltage to the control gate of the selected transistor, and applying a voltage to the control gate of each non-selected transistor to render each non-selected transistor conductive so that the first voltage is transmitted from the one bit line to said selected transistor; and
- wherein said first switch means includes a first insulated gate transistor and said second switch means includes a second insulated gate transistor, said first insulated gate transistor has a greater channel length than that of said second insulated gate transistor.
- 2. The memory device according to claim 1, wherein said data storage transistors comprise floating gate metal oxide semiconductor field effect transistors.
- 3. The memory device according to claim 1, wherein the program means erases said plurality of transistors by causing the first and second switch means to turn off, and applying the third voltage to the control gate of each of said plurality of transistors.
- 4. An electrically programmable and erasable semiconductor memory device comprising:
- a semiconductor substrate;
- an array of memory cell transistors formed in a surface area of said substrate, said transistors including a plurality of memory cell transistors coupled in series between first and second nodes, each memory cell transistor having a control gate and an insulated charged storage layer;
- a plurality of bit lines including a bit line connected with said plurality of memory cell transistors at the first node through a first switching transistor;
- word lines connected to control gates of said plurality of memory cell transistors;
- a second switching transistor coupled between the second node and a source potential;
- program means for allowing said plurality of memory cells to be written with data bits sequentially while causing said first and second switching transistors to turn on, and for, when a selected memory cell transistor is to be programmed, applying a high level voltage to at least one first non-selected memory cell transistor positioned between said first switching transistor and said selected memory cell transistor so as to permit a data bit to be transmitted from a bit line toward said selected memory cell transistor by way of said first switching transistor and said at least one first non-selected memory cell transistor, while applying a low level voltage to at least one second non-selected memory cell transistor, whereby tunneling of charge carriers occurs in the charge storage layer of said selected memory cell transistor; and wherein
- said first switching transistor has a channel length greater than that of said second switching transistor and those of said memory cell transistors so that an occurrence of punch through decreases in said first switching transistor.
- 5. The device according to claim 4, wherein each of said first and second switching transistors includes an insulated gate metal oxide semiconductor field effect transistor.
- 6. The device according to claim 5, wherein each of said plurality of memory cell transistors includes a floating-gate metal oxide semiconductor field effect transistor.
Priority Claims (10)
Number |
Date |
Country |
Kind |
62-233944 |
Sep 1987 |
JPX |
|
62-288375 |
Nov 1987 |
JPX |
|
62-290853 |
Nov 1987 |
JPX |
|
62-290854 |
Nov 1987 |
JPX |
|
62-290855 |
Nov 1987 |
JPX |
|
62-290857 |
Nov 1987 |
JPX |
|
62-329777 |
Dec 1987 |
JPX |
|
62-329778 |
Dec 1987 |
JPX |
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62-329779 |
Dec 1987 |
JPX |
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62-329780 |
Dec 1987 |
JPX |
|
Parent Case Info
This application is a Continuation of application Ser. No. 08/071,928, filed Jun. 4, 1993, abandoned, which is a divisional of application Ser. No. 07/875,600, filed Apr. 28, 1992, abandoned, which is a Cont. of application Ser. No. 07/629,029, filed Dec. 18, 1990, abandoned, which is a Cont. of application Ser. No. 07/244,854, filed Sep. 15, 1988, abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0134390 |
Oct 1981 |
JPX |
60-8559 |
Mar 1985 |
JPX |
60-23436 |
Jun 1985 |
JPX |
60-182162 |
Sep 1985 |
JPX |
Non-Patent Literature Citations (5)
Entry |
Adler, "Densely Arrayed EEPROM Having Low Voltage Tunnel Write", IBM Tech. Disc. Bull., vol. 27, No. 6, Nov. 1984, pp. 3302-3307. |
Shirota et al, "A New NAND Cell For Ultra High Density 5v Only EEPROMs", 1988 Symposium on VLSI Tech., Dig. of Tech Papers., May 10-13, 1988, pp. 33-34. |
Masuoka et al, "New Ultra High Density EPROM And Flash EPROM With NAND Structure Cell", Inter. Electron Devices Meeting (IEDM) Dig. of Tech. Papers, Dec. 6-9, 1987, pp. 552-555. |
Shelton, "Low Power EEPROM Can Be Reprogrammed Fast", Electronics, Jul. 31, 1980, pp. 89-92. |
"A High density EPROM cell and array", Symposium on VLSI technology digest of technical papers; pp. 89-90; May 1986; R. Stewart et al. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
875600 |
Apr 1992 |
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Continuations (3)
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Number |
Date |
Country |
Parent |
71928 |
Jun 1993 |
|
Parent |
629029 |
Dec 1990 |
|
Parent |
244854 |
Sep 1988 |
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