Claims
- 1. A non-volatile semiconductor storage apparatus, comprising:
- an array of memory cell transistors arranged in row and column directions;
- a first layer having first bit lines connected to drains of said memory cell transistors and extending in the column direction in zigzag form between paired columns of memory cell transistors;
- a second layer having second bit lines connected to sources of said memory cell transistors and extending in the column direction;
- word lines connected to control gates of said memory cell transistors and extending in the row direction; and
- a word line decoder selectively for keeping said word lines at a relatively high potential, an intermediate potential and a ground potential.
- 2. A non-volatile semiconductor storage apparatus according to claim 1, further comprising:
- first bit line decoders for selecting a first bit line from a plurality of first bit lines; and
- second bit line decoders for selecting a second bit line from a plurality of second bit lines.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-174516 |
Jul 1994 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 08/731,388 filed Oct. 15, 1996 now U.S. Pat. No. 5,671,177 which is a continuation of Ser. No. 08/460,681 filed Jun. 2, 1995 now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
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4-30469 |
Feb 1992 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
731388 |
Oct 1996 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
460681 |
Jun 1995 |
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