Patent Grant
7394687
1. Technical Field
The present application is generally related to the field of latches for storing logic states and, more specifically, to nonvolatile shadow latches that use two-terminal nanotube switches.
2. Discussion of Related Art
Volatile circuits have been and continue to be the norm in digital circuits. In the initial development phase, bipolar circuits were universally used for analog and digital circuits. Denser and more easily integrated but slower FET-based circuits soon followed, and were introduced for low cost and low power applications such as calculators, for example, while bipolar circuits were used for high speed applications. In order to eliminate static power dissipation present with bipolar, NMOS-only, or PMOS only chips, circuits based on complementary CMOS (combined NMOS and PMOS) devices were introduced and static power dissipation was virtually eliminated because power dissipation occurred only when circuits were switching. FET device scaling was introduced and used successfully to approximately double the number of circuits every two years, while increasing device and circuit performance, all at lower on-chip voltages to contain power dissipation to acceptable levels.
As the number of circuits grew into the millions, bipolar power dissipation became so high that CMOS was used to replace bipolar circuits, and CMOS became the technology of choice for the semiconductor industry for logic, memory, and analog products. Because of a common CMOS technology platform for a wide variety of electronic functions (memory, digital and analog circuits), system-on-chip (SoC) integrating hundreds of millions of circuits and billions of bits became possible. Migration to new denser technology generations enables more function per chip and is done for economic as well as performance reasons. New generations of technology (new technology nodes) result in transistor density improvements with increased current drive of device width and denser interconnect wiring. However, for sub-150 nm technologies, device threshold voltage scaling is increasingly difficult, resulting in high FET device OFF-state leakage currents and correspondingly high static power dissipation. Using conventional dimensional and voltage scaling is no longer sufficient for fast dense chips, SoCs for example, so that power dissipation is setting limits on the combination of speed and function per chip. At the 90 nm technology node, 25 to 50% of the total power (dynamic and static power) is due to leakage current-induced static power dissipation. Projections show that for products at the 65 nm technology node, static power dissipation will exceed dynamic (operating) power dissipation. New generations of technology are limited by power dissipation, especially static power dissipation due to poor scaling and associated high device OFF-state leakage currents. Because many applications such as PCs, cell phones, games, and others are portable and require battery operation, controlling power dissipation while enabling high speed operation is a requirement. Since power dissipation is setting limits on the combination of logic circuit size and operating speed, new chip architecture and circuit design solutions are needed in order to enable continued increases in high performance function.
One approach to power reduction by architecture and design described in U.S. Pat. No. 6,097,243, to Bertin et al., suggests an adjusting mechanism for reducing clock speeds when circuits have been inactive for a predetermined period of time to reduce dynamic power. Static power is also reduced by adjusting source-to-body voltage to increase threshold voltage and reduce associated leakage current. While this approach can reduce power dissipation for some circuits, both dynamic and static power dissipation still remains relatively high. Actually, threshold voltage modulation to reduce power dissipation may only be used in bulk CMOS technologies where body-regions can be modulated. SOI CMOS technology with isolated individual device body-regions cannot be modulated as described in U.S. Pat. No. 6,097,243.
In a related approach to power reduction by architecture and design described in Bertin et al. U.S. Pat. No. 6,097,241, where activity detection circuits monitor input circuit activity at the first logic stage and increase the speed of circuits in subsequent stages in order to enable high speed operation. Modulating device threshold voltage is required as well, with the associated limitations described further above with respect to U.S. Pat. No. 6,097,243.
In still another related approach to power reduction by architecture and design is described in U.S. Pat. No. 6,345,362, to Bertin et al., where plural on-chip functional units at different power levels are matched to instructions requiring various speeds using an on-chip control processor unit and on-chip power management unit to optimize chip power performance. Operating power and associated speed of each functional unit is adjusted by threshold voltage variation with the associated limitations as described further above with respect to U.S. Pat. No. 6,097,243.
A different approach to power reduction by architecture and design is described in U.S. Pat. No. 6,625,740, to Datar et al., where instructions are examined and code is rearranged such that circuits not required for a group of instructions are turned OFF. Circuit groups are turned ON as needed to process various instructions. In the example given, circuits are assumed to require 10 clock cycles to be in the OFF state, and 10 cycles to be restored to the full power state. Both dynamic and static power are reduced in those circuits where power is turned off, however, data is not retained in registers during power OFF and will be lost unless transferred to memory at power-off and transferred back at power-on.
A still different approach to power reduction by architecture and design is described in U.S. Pat. No. 6,658,634, to Goodnow et al., where logic is designed to ensure critical logic nets contain associated registers, and logic synthesis software is used to ensure that the clock can be selectively stopped and last data retained in registers in logic stages that are not required for particular sequences of instructions. While this method reduces dynamic power dissipation, static power dissipation remains high due to leakage currents.
In U.S. Pat. No. 5,986,962, to Bertin et al., power reduction is achieved by architecture and design such that each register (latch) has a corresponding shadow register (latch) designed (optimized) for low power retention (low leakage current CMOS devices). The state of the system is transferred to the shadow latches upon a transition to a low power mode, and power is removed from logic circuits in portions of the chip, or the entire chip. The logic state is restored to each register when power is restored. While this method significantly reduces both dynamic and static power, and in fact eliminates all power dissipation except for the low power shadow registers if the entire chip is turned OFF, the shadow registers introduce significant problems of their own. First, low power dissipation registers (latches) are sensitive to alpha particles and data integrity is an issue. Radiation hardening techniques could be applied to the latches, but some technology changes may be required. Second, static power is still dissipated in the low power shadow latches. Also, adding a low power shadow latch for each high performance latch significantly increases chip area which impacts chip design and reduces the number of chips per wafer, which in turn increases chip cost.
Highly integrated products with a wide variety of circuit functions such as high logic and memory content, system-on-chip (SoC) architecture for example, are an important part of current semiconductor industry design practices. Highly integrated product designs using bulk or SOI CMOS technologies are especially important for portable battery-operated systems that require a high level of integration and the mixed data and signal processing that SoC devices offer. Product requirements, especially in consumer applications, are subject to change as the design progresses. As a result, designs often utilize a combination of disparate elements including embedded, programmable logic functions such as general purpose (usually RISC architecture) embedded microprocessor cores, embedded DSPs, embedded ASIC designs (eASIC), embedded FPGAs, embedded memory, and other functions. Time-to-market with the desired product functions is vital to product success, so that typically there is insufficient time to optimize function for maximum performance at minimum total power dissipation using a more customized approach such as an optimized ASIC design, for example. Instead, designs must include programmable logic functions that dissipate more power than optimized designs in order to allow for flexibility in modifying product function near the end of the design cycle, and servicing multiple applications for economic reasons.
Migration to new denser technology generations enables more function per chip and is done for economic as well as performance reasons. New generations of technology (new technology nodes) result in transistor density improvements with increased current drive of device width and denser interconnect wiring. However, for sub-150 nm technologies, device threshold voltage scaling is increasingly difficult, resulting in high FET device OFF-state leakage currents and correspondingly high static power dissipation.
In order to successfully incorporate power management in highly integrated product designs, it is important to understand circuit design efficiency with respect to power dissipation.
The energy required for various operations is dominated by bandwidth.
If present single processor chip architectures and design methodologies were left unchanged, then power dissipation and latency associated with on-chip interconnection of logic and memory functions would become a dominant factor resulting in power-limited chip performance. Actually, chip architecture has responded and multiple, simple processors, distributed register files, explicit managed local memory, enhanced floor planning for more optimum placement, and other innovations have prevented on-chip interconnections to become a dominant power/performance limiting factor.
With these new evolving chip architectures and design methodologies, limitations to chip performance are primarily due to embedded logic and memory functions as has always been the case. However, these embedded circuits are increasingly difficult to scale as described further above, and static power dissipation is beginning to set performance on chip operation.
Static power in CMOS circuits is present even when no switching takes place. It is due to leakage current that flows because of poorly scaled device threshold voltages and operating voltages. Static power is reduced only by reducing voltages, preferably reducing the voltages in temporarily unused circuits to zero (selectively removing applied voltages from these circuits).
High speed chip design often uses logic design techniques referred to as concurrent operation. These techniques are pipelining and parallelism, in which logic function is divided into smaller pieces (sub blocks), called stages, such that the rate at which instructions are executed improves because many operations are executed at the same time. Concurrent logic design techniques are described in more detail in the following references: H. B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI”, Addison-Wesley Publishing Company, Inc, 1990, pp. 412-416; and David T. Wang, “Revisiting the FO4 Metric.”
An important aspect of concurrent logic operations is that the start of an instruction does not wait for previous ones to be completed. In this way, all portions of the hardware are utilized every cycle, making best use of available logic and increasing machine throughput. Dependencies between instructions prevent logic performance from achieving maximum possible performance; however instruction optimization is used to achieve faster performance using, for example, the pipelining technique.
The pipelining technique, for example, uses random logic blocks divided (separated) by registers (also referred to as register files, register banks, pipeline latches, or latches) that result in a substantially higher speed of operation; that is, pipelining used to improve the execution rate. Logic is divided into roughly equal smaller pieces, called stages, and a bank of registers (latches) is inserted to hold temporary values (logic states) at the interface of the logic stages. The logic clock frequency may then be increased to a level that is proportional to the inverse of the sum of the longest delay of the logic stages plus the latch delay overhead. Examples of logic stages, registers (single-latch and double-latch designs), and clocking are given in the H. B. Bakoglu reference book described further above, pp. 338-349. Examples of register (latch) design are given in the H. B. Bakoglu reference book, pp. 349-355. Designs are increasing the number of registers and decreasing the logic stage delay. By way of example, the number of registers (latches) used in the IBM 750 power PC chip is about 10,000 registers. The next generation power PC design, the IBM 970, uses about 300,000 registers.
Design Using Volatile Registers (Latches)
Power dissipation is an important consideration because it often sets the maximum performance limit of the logic function as discussed further above with respect to
In addition to the performance benefits of dividing random logic into smaller blocks, there is a testing benefit as well. Logic testing requires that each logic node be switched to both “ONE” and “ZERO” logic states. Chips with a large number of gates, tens and hundreds of millions, for example, cannot be tested efficiently unless the logic is subdivided into smaller stages (blocks). Smaller logic stages separated by latches enable logic testability to reach 98 to 99%, for example. The registers described herein may also be interconnected serially for test purposes. Logic test patterns (test vectors) are applied, and logic response is measured in order to identify and eliminate defective chips as is well known in the industry. The following references discuss design for logic testability: H Fujiwara, “Logic Design and Design for Testability”, Cambridge, Mass., the MIT press, 1985, pp. 238, 256-259; and P. H. Bardel, W. H. McAnney, and J. Savir, “Built-In Test for VLSI: Pseudorandom Techniques”, New York, N.Y., John Wiley & Sons, 1987, pp.38-43.
A number of different register file circuit designs are possible (see Bakoglu above). For example, a clocked synchronous register file stage circuit design may use a master latch stage circuit and a slave latch stage circuit with two non-overlapping clocks such as CLK1 and CLK2 illustrated in
The electrical characteristics of state of the art PC chips, e.g. the IBM 970 power PC chip used in Apple computers and SONY Playstations, illustrate the relationship between operating speed and dynamic and static power dissipation in high speed synchronized logic chips using two non overlapping clocks design. The IBM 970 chip operates at 1.3 volts, is designed at the 130 nm technology node using an SOI CMOS technology with copper wiring, and includes an on-board L1 Sync SRAM cache of 1 megabit, an on-board L2 Sync SRAM cache of 4 megabits, and a double-latch design with non-overlapping clocks CLK1 and CLK2 (similar in approach to synchronous logic function 5 of
In operation, at a clock periodicity of approximately 340 ps, a master latch has approximately 170 ps to accept data from a preceding logic stage, capture (latch) the data, and have the data ready for the slave latch. A slave latch has approximately 170 ps to accept data from a corresponding master latch, transmit the information to the next logic stage, and then latch the information.
The IBM 970 chip has a dynamic (active) power dissipation of approximately 90 watts and static (standby) power dissipation due to device leakage of 25 watts; static power is approximately 28% of the active power dissipation.
Input node 515 of master latch stage circuit 505 receives input signal VIN and drives CMOS transfer gate 530, which is connected to node 535, and drives a first storage node 535 formed by cross coupled CMOS inverters 545 and 550. Input signal VIN corresponds to VIN from logic 50 in
Input node 520 of slave latch stage circuit 510, which is also the output node of master latch stage circuit 505, drives inverter 570. The output of inverter 570 output VOUT on output node 525, and also drives the input of inverter 575. Output signal VOUT corresponds to VOUT in
In operation, a clocking scheme such as illustrated in
A master (L1) latch such as master (L1) latch 70 accepts data from a preceding logic stage 50 during the first half of the clock cycle time, captures and holds the data, and also transfers the information to a slave (L2) latch such as slave (L2) latch 75 at the beginning of the second half of the clock cycle time. A slave (L2) latch such as slave (L2) latch 75 accepts information from a corresponding master (L1) latch 70 at the beginning of the second half of the clock cycle time, transmits the information to the next logic stage 60, and latches the information before the end of the second half of the clock cycle time. If the clock is stopped during the first half of the clock cycle, then master (L1) latch 70 holds (stores) a logic state or data. If the clock is stopped during the second half of the clock cycle, then slave (L2) latch holds (or stores) a logic state or data. If power is removed or lost, the logic state or data are lost.
In operation, at the beginning of a clock cycle, clock CLK 540 transitions from high to low voltage and remains at low voltage for the first half the clock cycle, and complimentary clock CLKb 540′ transitions from low to high voltage and remains at high voltage for the first half of the clock cycle. CMOS transfer device 530 turns ON coupling input node 515 voltage VIN to storage node 535. CMOS transfer device 560 turns OFF and isolates the output of master latch stage circuit 505 from the input node 520 of slave latch stage circuit 510. CMOS transfer device 585 also turns OFF breaking the feedback path between the output 580 of inverter 575 and the input 520 of inverter 570 such that node 520 does not act as a storage node. Voltage VIN may transition to a voltage value corresponding to the correct logic state any time prior to the end of the first half of the clock cycle, providing sufficient time remains for cross coupled inverters 545 and 550 to store the corresponding logic state prior to clock transition at the beginning of the second half of the clock cycle.
Clock CLK 540 transitions from low to high voltage and remains at high voltage at the beginning of the second half of the clock cycle, and complimentary clock CLKb 540′ transitions from high to low voltage and remains at low voltage for the second half of the clock cycle. CMOS transfer device 530 turns OFF decoupling input node 515 voltage VIN from storage node 535, which remains in a state corresponding to input voltage VIN at the end of the first half of the clock cycle. CMOS transfer device 560 turns ON and transfers the state of storage node 555 to input 520 of inverter 570 that drives output node 525 to output voltage VOUT, and also drives the input of inverter 575. CMOS transfer device 585 turns ON which enables output 180 of inverter 575 to drive the input of inverter 570 and store the state of slave latch state stage circuit 510 until the end of the second stage of the clock cycle.
In U.S. Pat. No. 5,986,962, to Bertin et al., volatile low power shadow latches hold register file logic states or data so that volatile high performance register file power may be turned OFF to reduce static power dissipation as described above. However, volatile low power shadow latches must remain ON and therefore still dissipate power while storing logic states or data in backup mode because the storage is volatile, and information is lost if power is lost. Furthermore, volatile low power dissipating shadow latches use low bias current to minimize static power and are therefore very susceptible to disturb, in which stored logic states or data may be lost or corrupted. This may occur due to power supply noise, on-chip switching noise, alpha particle or other radiation disturb, for example. Also, shadow latches require additional chip area that can substantially increase chip size.
The present invention provides a non-volatile shadow latch using a nanotube switch.
Under one aspect, a non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus, and a shadow memory device coupled to the volatile storage device so as to receive and store the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch, wherein said nanotube switch stores the corresponding state of the shadow device. Under another aspect, the non-volatile nanotube switch includes a two terminal nanotube switch.
Under another aspect, the non-volatile memory cell further includes a coupling circuit capable of transferring the corresponding logic state of the volatile storage device to the shadow memory device in response to electrical stimulus, and also capable of transferring a logic state of the shadow memory device to the volatile storage device in response to electrical stimulus.
Under another aspect, the non-volatile memory cell further includes a coupling circuit which includes a program circuit providing an electrical pathway between the volatile storage device and the shadow memory device and responsive to a program signal to transfer a corresponding logic state of the volatile storage device to the shadow memory device; and a restore circuit providing an electrical pathway between the shadow memory device and the volatile storage device and responsive to a restore signal to transfer a logic state of the shadow memory device to the volatile storage device.
Under another aspect, the non-volatile memory cell further includes a coupling circuit which includes an erase circuit in electrical communication with the shadow memory device and responsive to an erase signal to erase a logic state of the shadow memory device.
Under another aspect, a first terminal of the nanotube switch is in electrical communication with an output node of the volatile storage device, and a second terminal of the nanotube switch is in electrical communication with a program/erase/read line.
Under another aspect, the non-volatile memory cell includes a controller in electrical communication with the volatile storage device and capable of monitoring a level of power to the volatile storage device. Under another aspect the controller is capable of applying electrical stimulus to the shadow memory device in response to a loss of power to the volatile storage device. The electrical stimulus transfers the logic state of the volatile storage device to the shadow memory device.
Under another aspect, the controller is capable of applying electrical stimulus to the shadow memory device in response to an increase of power to the volatile storage device. The electrical stimulus transfers the logic state of the shadow memory device to the volatile storage device.
Under another aspect, the state stored by the non-volatile nanoswitch is characterized by the resistance of an electrical pathway in the nanoswitch.
Under another aspect, the non-volatile memory cell includes a master latch stage capable of receiving a voltage and outputting that voltage to the volatile storage device. The voltage corresponds to a logic state. Under another aspect, a random logic stage produces the voltage corresponding to the logic state. Under another aspect, an onboard cache produces the voltage corresponding to the logic state.
In the Drawing:
Preferred embodiments of the present invention provide non-volatile shadow elements that include nanotube switches. In general, the non-volatile shadow elements are coupled to corresponding system volatile latches, also referred to as register file latches. In some embodiments, the shadow elements are coupled to corresponding system latches by coupling circuits. In other embodiments, the shadow elements are directly coupled to corresponding system latches. In general, the state of a system latch is transferred to a shadow element when the power is turned off to that latch. Accordingly, power may be turned off for an entire chip, or selectively turned off for one or more portions of a chip, and information in each system latch will be transferred to the corresponding shadow element. Then, when power is restored to the latch, the state stored in the shadow element will be transferred back to the corresponding system latch. This enables power to be turned OFF while saving critical data, and restoring operation of chip sub-functions as power is restored.
In preferred embodiments, the nonvolatile nanotube switches can be fabricated with processes that integrate well with existing CMOS technologies. In preferred embodiments, the nanotube switches in the non-volatile shadow elements include a nanotube article, which is in electrical communication with each of two conductive terminals. The nanotube article includes at least one nanotube. By applying appropriate electrical stimuli to at least one of the conductive terminals, the electrical resistance of the nanotube article between the two conductive terminals can be reprogrammably changed between a relatively high resistance, and a relatively low resistance. The relative resistance of the nanotube article characterizes the logical state stored in the non-volatile shadow element. The state is non-volatile, allowing the logical state to be stored (indefinitely) with zero power dissipation. Although in the described embodiments nanotube switches with two terminals are used, in general other kinds of nanotube switches can also be used.
Design Using Non-Volatile Register Files
Non-volatile nanotube switches can be used in embodiments of shadow storage devices that are nonvolatile (holds information when power is turned OFF), and are tolerant of harsh environments such as high temperature and high radiation levels. Further, non-volatile nanotube switches can be integrated easily with any CMOS process such as bulk CMOS or SOI CMOS, and require relatively little additional chip area to implement. The use of nonvolatile nanotube switches in the design of embodiments of nonvolatile register files is described further below. Nonvolatile register files have two modes of operation, a normal run mode, and a zero power dissipation logic state (or data) retention mode.
Non-Volatile Nanotube Switch
Embodiments of non-volatile two-terminal nanotube switches that can be included in the described shadow latches are described in U.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same,” the contents of which are incorporated herein in their entirety by reference. Associated structures using the switches, along with electrical characteristics, methods of fabricating, and methods of integrating the switches with existing semiconductor technology are described.
Conductive elements 15 and 20 are in contact with stimulus circuit 50. Stimulus circuit 50 electrically stimulates at least one of conductive elements 15 and 20, which changes the state of switch 10. More specifically, nanotube element 25 responds to the simulation by changing the resistance of switch 10 between conductive elements 15 and 20; the relative value of the resistance corresponds to the state of the switch. For example, if stimulus circuit 50 applies a first electrical stimulus, which may be for example a relatively high voltage and a current across conductive elements 15 and 20, then nanotube element 25 responds by changing the resistance of the device between conductive elements 15 and 20 to a relatively high resistance. This corresponds to an “erased” or “off” state of the device, where electrical conduction is relatively poor between conductive elements 15 and 20. The impedance between elements 15 and 20 may also be relatively high in this state. For example, if stimulus circuit 50 applies a second electrical stimulus, which may be for example a relatively low voltage and a current across conductive elements 15 and 20, then nanotube element 25 responds by changing the resistance of the switch between conductive elements 15 and 20 to a relatively low resistance. This corresponds to a “programmed” or “on” state of the device, where electrical conduction is relatively good, or even near-ohmic, between conductive elements 15 and 20. The impedance between elements 15 and 20 may also be relatively low in this state. The “erase” current associated with the relatively high “erase” voltage may be greater than or less than the “program” current associated with the relatively low “program” voltage. “Erase” and “program” currents are typically in the in the nano-Ampere or micro-Ampere range, and are determined by geometry and material selection of the nonvolatile two-terminal nanotube switch. In general, the resistance as well as the impedance between the first and second conductive elements of the device is a function of the state of the device, and can be determined by measuring electrical characteristics of the switch.
Conductive elements 15 and 20 are preferably made of a conductive material, and can be the same or different material depending on the desired performance characteristics of switch 10. Conductive elements 15 and 20 can, for example, be composed of metals such as Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, as well as other suitable metals, and combinations of these. Metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, including CNTs themselves (single walled, multiwalled, and/or double walled, for example), or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix may be used. Other kinds of conductor, or semiconductor, materials can also be used. Insulator 30 is preferably a suitable insulative material, for example SiO2, SiN, Al203, BeO, GaAs, polyimide, or other suitable material. Examples of conductive and insulative materials that can be used in 2-TNS 10 are described in greater detail in U.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same.”
In some embodiments, nanotube element (article) 25 is a fabric of matted carbon nanotubes (also referred to as a nanofabric). Nanotubes in the nanofabric may be randomly oriented, or may have an orientation that is not constrained to an orientation of nanotube element 25. Nanotube elements generally substantially conform to surfaces; in some embodiments, one or more terminals of a two-terminal nanotube switch have vertically oriented surfaces, and the nanotube element substantially conforms to at least a portion of the vertically oriented surface. In some embodiments, the nanotube element or fabric is porous, and material from conductive elements 15 and/or 20 may fill at least some of the pores in nanotube element 25. In some embodiments, nanotube element 25 includes single-walled nanotubes (SWNTs) and/or multiwalled nanotubes (MWNTs) and/or double-walled nanotubes (DWNTs). In some embodiments, nanotube element 25 includes one or more bundles of nanotubes. Generally, nanotube element 25 includes at least one nanotube. Methods of making nanotube elements and nanofabrics are known and are described in U.S. Pat. Nos. 6,784,028, 6,835,591, 6,574,130, 6,643,165, 6,706,402, 6,919,592, 6,911,682, and 6,924,538; U.S. Patent Publication Nos. 2005-0062035, 2005-0035367, 2005-0036365, and 2004-0181630; and U.S. patent application Ser. Nos. 10/341005, 10/341055, 10/341054, 10/341130, the contents of which are hereby incorporated by reference in their entireties (hereinafter and hereinbefore the “incorporated patent references”). Some embodiments for nanotube elements that can be used in 2-TNS 10 are described in greater detail in U.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same.”
Generally it is preferable that the values of the high and low resistances are separated by at least an order of magnitude. In some preferred embodiments, the “off” state has a resistance that is at least about 10 times higher than a resistance of the “on” state. In some preferred embodiments, the “off” state has an impedance that is at least about 10 times higher than an impedance of the “on” state. In some embodiments, the “programmed” or “on” state is characterized by a resistance (RON) between conductive elements 15 and 20 that is generally in the range of 100 Ohms to 1 M-Ohm. In some embodiments, the “erased” or “off” state is characterized by a resistance (ROFF) between conductive elements 15 and 20 that is generally in the range of 10 M-Ohm to 10 G-Ohm or more. The two states are non-volatile, i.e., they do not change until stimulus circuit 50 applies another appropriate electrical stimulus to at least one of conductive elements 15 and 20, and they retain state even if power is removed from the circuit. Stimulus circuit can also determine the state of 2-TNS 10 with a non-destructive read-out operation (NDRO). For example, stimulus circuit 50 may apply a low measurement voltage across conductive elements 15 and 20, and measure the resistance R between the conductive elements. This resistance can be measured by measuring the current flow between conductive elements 15 and 20 and from that calculating the resistance R. The stimulus is sufficiently weak that it does not change the state of the device. Another example of a method of determining the state of the cell by measuring pre-charged bit line capacitance discharge through (between) conductive elements 15 and 20 is described in U.S. patent application Ser. No. 11/274,967, filed on Nov. 15, 2005, entitled “Memory Arrays Using Nanotube Articles With Reprogrammable Resistance.” Example electrical stimuli and resistances for “programmed” and “erased” states for some embodiments of two-terminal nanotube switches, and example “read” stimuli, are described in greater detail in U.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same.”
In some embodiments, thermal and/or electrical engineering, that is, thermal and/or electrical management (design), can be used to enhance the performance of a two-terminal nanotube switch, as described in U.S. patent application No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same.”
Passivation of NRAM devices may be used to facilitate device operation in air, at room temperature, and as a protecting layer in conjunction with stacked material layers on top on the NRAM device. Operation of unpassivated NRAM devices are typically performed in an inert ambient, such as argon, nitrogen, or helium, or an elevated (greater than 125 C) sample temperature to remove adsorbed water from the exposed nanotubes. Therefore, the requirements of a passivation film are typically twofold. First, the passivation should form an effective moisture barrier, preventing exposure of the nanotubes to water. Second, the passivation film should not interfere with the switching mechanism of the NRAM device.
One approach to passivation involves cavities, which have been fabricated around the NRAM devices to provide a sealed switching region. Cavities both around individual devices (device-level passivation) and around an entire die of 22 devices (die-level passivation) have been demonstrated. However, the process flow to fabricate is complicated, with at least 2 additional lithography steps, and at least 2 additional etching steps required.
Another approach to passivation involves depositing a suitable dielectric layer over the NRAM devices. An example of this approach is the use of spin-coated polyvinyledenefluoride (PVDF) in direct contact with the NRAM devices. The PVDF is patterned into either die-level (over an entire die active region) or device-level patches (individual patches covering individual devices). Then a suitable secondary dielectric passivation film, such an alumina or silicon dioxide is used to seal off the PVDF and provide a passivation robust to NRAM operation. It is thought that NRAM operation thermally decomposes the overlying PVDF, hence a secondary passivation film is required to seal off the devices. Since the die level passivations are typically ˜100 micron square patches, this local decomposition can lead to ruptures of the secondary passivation, exposure of NRAM devices to air, and their subsequent failure. To avoid such failures of the secondary passivation film, the die-level passivated devices are “burned-in” electrically by pulsing the devices typically with 500 ns pulses from 4V to 8V in 0.5V steps. This is thought to controllably decompose the PVDF and prevent a rupture of the overlying secondary passivation film. After the burn-in procedure the die-level passivated NRAM devices operate normally. Devices passivated with a device-level PVDF coating and a secondary passivation film do not require such a burn in procedure and may be operated in air at room temperature directly at operating voltages. With device-level passivaton the PVDF is patterned in the exact shape of the CNT fabric, typically 0.5 microns wide and 1-2 microns long. It is thought that such small patches can decompose without stressing the secondary passivation film to failure. It is possible that for a given defect density in the secondary passivation, there are no defects on average over the smaller footprint of the device-level PVDF patches in comparison to the larger, die-level patches.
In this embodiment, nanotube element 25′ is patterned within a region that can be defined before or after deposition of conductive elements 15′ and/or 20′. Conductive element 15′ overlaps one entire end-region of nanotube element 25′, forming a near-ohmic contact. At the opposite end of nanotube element 25′, at overlap region 45′, conductive element 20′ overlaps nanotube element 25′ by a controlled overlap length 40′. Controlled overlap length may be for example in the range of 1 to 150 nm, or in the range of 15-50 nm. In one preferred embodiment, controlled overlap length 40′ is about 45 nm. The materials and methods of making switch 10′ may be similar to those described above for switch 10 of
Switches 10 and 10′ illustrated in figures 9A and 9B are intended to be illustrative examples of two-terminal nanotube switches that can be used in non-volatile shadow latches using a nanotube switch. Other embodiments of 2-TNS that can be used in non-volatile shadows latches are described in U.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same.”
Systems With Nonvolatile Shadow Latches Using A Nanotube Switch
Nonvolatile slave (L2) latch operates as a volatile slave (L2) latch during high speed chip operation. If power is to be reduced, then clock CLK is stopped during the second half of the clock cycle, after data has been latched in volatile slave (L2) latch. In one embodiment, the logic state of nonvolatile slave (L2) latch is transferred to a nonvolatile nanotube switch corresponding to switches 820, 820′, and 820″ by dedicated coupling circuits corresponding to dedicated coupling circuits 830, 830′, and 830″ as shown in
In the normal run mode, volatile master latch stage 1010 receives input voltage VIN, drives volatile slave latch stage 1015, is clocked (shown further below), and is powered from VDD supplied by power source 1045.
Volatile slave latch stage 1015 receives input from the output of volatile master latch 1010, supplies output voltage VOUT, is clocked (shown further below), and is powered from VDD supplied by power source 1045. Volatile slave latch stage 1015 is coupled to nonvolatile nanotube switch 1025 by coupling circuit 1020.
During transition from normal run mode to zero power nonvolatile retention mode, or from zero power nonvolatile retention mode to normal run node, nonvolatile nanotube switch 1025 is powered from VEPR supplied by power source 1045 through electrical connection 1030. Nonvolatile nanotube switch 1025 is connected to coupling circuit 1020 by electrical connection 1035.
In addition to electrical connection 1035 to nonvolatile nanotube switch 1025, coupling circuit 1020 is also connected to volatile slave latch stage 1015 by electrical connections 1040. A controller (not shown) supplies erase enable, program enable, restore enable, and set/clear enable pulses to coupling circuit 1020 as shown in
In the normal run mode, volatile master latch stage 1010′ receives input voltage VIN, drives volatile slave latch stage 1015′, is clocked (shown further below), and is powered from VDD supplied by power source 1045′.
Volatile slave latch stage 1015′ receives input from the output of volatile master latch 1010′, supplies output voltage VOUT, is clocked (shown further below), and is powered from VDD supplied by power source 1045′. Volatile slave latch stage 1015′ is coupled to nonvolatile nanotube switch 1025′ by electrical connection 1040′.
During transition from normal run mode to zero power nonvolatile retention mode, or from zero power nonvolatile retention mode to normal run node, nonvolatile nanotube switch 1025′ is powered from VEPR supplied by power source 1045′ through electrical connection 1030′.
A controller (not shown) supplies erase enable, program enable, restore enable, and set/clear enable pulses to nonvolatile nanotube switch 1025′ via VEPR connected to switch 1025′ by electrical connection 1030′ as shown in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
While in normal run mode, coupling circuit 1108 is inactive, and nonvolatile nanotube switch 1110 is not powered by VEPR and is also decoupled from volatile slave latch stage circuit 1106. Hence, volatile master latch stage circuit 1104 and volatile slave latch stage circuit 1106 operate in a normal (conventional) synchronized logic master/slave register run mode of operation at high speed clock rates, typically 3 GHz, with VDD=1.3 volts, for logic products fabricated using the 130 nm technology node.
In normal run mode, at the beginning of a clock cycle, clock CLK 1140 transitions from high to low voltage and remains at low voltage for the first half the clock cycle, and complimentary clock CLKb 1140′ transitions from low to high voltage and remains at high voltage for the first half of the clock cycle. CMOS transfer device 1130 turns ON coupling input node 1115 voltage VIN to storage node 1135. CMOS transfer device 1160 turns OFF and isolates the output of volatile master latch stage circuit 1104 from the input node 1120 of volatile slave latch stage circuit 1106. In normal run mode, clock CLK is connected to mode input 1192 of volatile slave latch stage circuit 1106, clock CLK is connected to CMOS transfer device 1185, and complimentary clock CLKb output of inverter 1190 is also connected to CMOS transfer device 1185, such that CMOS transfer device also turns OFF breaking the feedback path between the output 1180 of inverter 1175 and the input 1120 of inverter 1170 such that node 1120 does not act as a storage node. Voltage VIN may transition to a voltage value corresponding to the correct logic state any time prior to the end of the first half of the clock cycle, providing sufficient time remains for cross coupled inverters 1145 and 1150 to store the corresponding logic state on storage node 1155 prior to clock transition at the beginning of the second half of the clock cycle.
In normal run mode, clock CLK 1140 transitions from low to high voltage and remains at high voltage at the beginning of the second half of the clock cycle, and complimentary clock CLKb 1140′ transitions from high to low voltage and remains at low voltage for the second half of the clock cycle. CMOS transfer device 1130 turns OFF decoupling input node 1115 voltage VIN from storage node 1135, which remains in a state corresponding to input voltage VIN at the end of the first half of the clock cycle, and storage node 1155 remains in a complimentary state to storage node 1135. CMOS transfer device 1160 turns ON and transfers the state of storage node 1155 to input 1120 of inverter 1170 that drives output node 1125 to output voltage VOUT, and also drives the input of inverter 1175. In normal run mode, clock CLK is connected to mode input 1192 of volatile slave latch stage circuit 1106, clock CLK is connected to CMOS transfer device 1185, and complimentary clock CLKb output of inverter 1190 is also connected to CMOS transfer device 1185, such that CMOS transfer device also turns ON forming the feedback path between the output 1180 of inverter 1175 and the input 1120 of inverter 1170 such that node 1120 acts as a storage node. With CMOS transfer device 1185 turned ON, output 1180 of inverter 1175 drives the input of inverter 1170 and stores the state of slave latch state stage circuit 1110 until the end of the second stage of the clock cycle.
While in zero power logic state (or data) nonvolatile retention mode, coupling circuit 1108 is inactive, nonvolatile nanotube switch 1110 is not powered by VEPR, and is also decoupled from volatile slave latch stage circuit 1106. Volatile master latch stage circuit 1104 and volatile slave latch stage circuit 1106 power supplies are at zero volts.
In operation, when transitioning from normal run mode to zero power nonvolatile retention mode, coupling circuit 1108 must transfer the logic state from volatile slave latch stage circuit 1106 to nonvolatile nanotube switch 1110 before power is turned OFF. As illustrated in waveforms 1250 in
During the erase operation, an erase enable pulse transitions from zero volts to VDD (1.3 to 2.5 volts, for example) turning transistor 1220 ON and providing a conducting path between node 1116 and ground as illustrated in
Note that during the erase operation, transistors 1240, 1235, and 1230 are all OFF, isolating nonvolatile nanotube switch 1110 from volatile slave latch stage circuit 1106. Therefore, the erase operation may be performed any time during the normal run mode without impacting the performance of volatile slave latch stage circuit 1106, and can therefore be made transparent to the logic operation of the device.
As illustrated in
During the program operation, the erase enable voltage is held at zero volts and transistor 1220 is OFF. Also, the restore enable voltage is held at VDD so that transistor 1240 is OFF. Also, set/clear restore voltage is held at zero so transistor 1235 is OFF, such that only the program operation is enabled.
In operation, when transitioning from zero power nonvolatile retention mode to normal run mode, coupling circuit 1108 must transfer the logic state from nonvolatile nanotube switch 1110 to volatile slave latch stage circuit 1106 after power supply VDD is restored, but before clock operation begins. As illustrated in
As illustrated by waveforms 1300 in
During the restore operation, the erase enable voltage is held at zero volts and transistor 1220 is OFF. Also, the program enable voltage is held at zero volts, and transistor 1230 is OFF such that only the restore operation is enabled.
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
While in normal run mode, coupling circuit 1108′ is inactive, and nonvolatile nanotube switch 1110′ is not powered by VEPR and is also decoupled from volatile slave latch stage circuit 1106′. Hence, volatile master latch stage circuit 1104′ and volatile slave latch stage circuit 1106′ operate in a normal (conventional) synchronized logic master/slave register run mode of operation at high speed clock rates, typically 3 GHz, with VDD=1.3 volts, for logic products fabricated using the 130 nm technology node.
In normal run mode, at the beginning of a clock cycle, clock CLK 1140 transitions from high to low voltage and remains at low voltage for the first half the clock cycle, and complimentary clock CLKb 1140′ transitions from low to high voltage and remains at high voltage for the first half of the clock cycle. CMOS transfer device 1130′ turns ON coupling input node 1115′ voltage VIN to storage node 1135′. CMOS transfer device 1160′ turns OFF and isolates the output of volatile master latch stage circuit 1104′ from the input node 1120′ of volatile slave latch stage circuit 1106′. In normal run mode, clock CLK is connected to mode input 1192′ of volatile slave latch stage circuit 1106′, clock CLK is connected to CMOS transfer device 1185′, and complimentary clock CLKb output of inverter 1190′ is also connected to CMOS transfer device 1185′, such that CMOS transfer device also turns OFF breaking the feedback path between the output 1180′ of inverter 1175′ and the input 1120′ of inverter 1170′ such that node 1120′ does not act as a storage node. Voltage VIN may transition to a voltage value corresponding to the correct logic state any time prior to the end of the first half of the clock cycle, providing sufficient time remains for cross coupled inverters 1145′ and 1150′ to store the corresponding logic state on storage node 1155′ prior to clock transition at the beginning of the second half of the clock cycle.
In normal run mode, clock CLK 1140 transitions from low to high voltage and remains at high voltage at the beginning of the second half of the clock cycle, and complimentary clock CLKb 1140′ transitions from high to low voltage and remains at low voltage for the second half of the clock cycle. CMOS transfer device 1130′ turns OFF decoupling input node 1115′ voltage VIN from storage node 1135′, which remains in a state corresponding to input voltage VIN at the end of the first half of the clock cycle, and storage node 1155′ remains in a complimentary state to storage node 1135′. CMOS transfer device 1160′ turns ON and transfers the state of storage node 1155′ to input 1120′ of inverter 1170′ that drives output node 1125′ to output voltage VOUT, and also drives the input of inverter 1175′. In normal run mode, clock CLK is connected to mode input 1192′ of volatile slave latch stage circuit 1106′, clock CLK is connected to CMOS transfer device 1185′, and complimentary clock CLKb output of inverter 1190′ is also connected to CMOS transfer device 1185′, such that CMOS transfer device also turns ON forming the feedback path between the output 1180′ of inverter 1175′ and the input 1120′ of inverter 1170′ such that node 1120′ acts as a storage node. With CMOS transfer device 1185′ turned ON, output 1180′ of inverter 1175′ drives the input of inverter 1170′ and stores the state of slave latch state stage circuit 1110′ until the end of the second stage of the clock cycle.
While in zero power logic state (or data) nonvolatile retention mode, coupling circuit 1108′ is inactive, nonvolatile nanotube switch 1110′ is not powered by VEPR, and is also decoupled from volatile slave latch stage circuit 1106′. Volatile master latch stage circuit 1104′ and volatile slave latch stage circuit 1106′ power supplies are at zero volts.
In operation, when transitioning from normal run mode to zero power nonvolatile retention mode, coupling circuit 1108′ transfers the logic state from volatile slave latch stage circuit 1106′ to nonvolatile nanotube switch 1110′ before power is turned OFF. As illustrated in waveforms 1250′ in
During an erase operation, program enable input voltage is at zero volts, and transistor 1342 is held in an ON state by the output of inverter 1330. An erase enable pulse transitions from zero volts to VDD (1.3 to 2.5 volts, for example) turning transistor 1320 ON and providing a conducting path between node 1116′ and ground, through ON transistors 1342 and 1320 as illustrated in
Note that during the erase operation, transistors 1370, 1365, and 1343 are all OFF, isolating nonvolatile nanotube switch 1110′ from volatile slave latch stage circuit 1106′. Therefore, the erase operation may be performed any time during the normal run mode without impacting the performance of volatile slave latch stage circuit 1106′, and can therefore be made transparent to the logic operation of the device.
As illustrated in
During the program operation, the erase enable voltage is held at zero volts and transistor 1320 is OFF. Transistor 1342 is held in the OFF position by the output of inverter 1330. Also, the restore enable voltage is held at zero volts so that transistor 1370 is OFF. Also, restore precharge voltage is held at zero so transistor 1365 is OFF, such that only the program operation is enabled.
In operation, when transitioning from zero power nonvolatile retention mode to normal run mode, coupling circuit 1108′ transfers the logic state from nonvolatile nanotube switch 1110′ to volatile slave latch stage circuit 1106′ after power supply VDD is restored, but before clock operation begins. As illustrated in
As illustrated by waveforms 1300 in
During the restore operation, the erase enable voltage is held at zero volts and transistor 1320 is OFF. Also, the program enable voltage is held at zero volts, and transistor 1343 is OFF and transistor 1342 is ON such that only the restore operation is enabled.
As illustrated in
As illustrated in
As illustrated in
While in a normal run mode, all directly coupled nonvolatile nanotube switches 1110″ are in an OFF (high resistance) state and VEPR may be at or near zero volts. Hence, volatile master latch stage circuit 1104″ and volatile slave latch stage circuit 1106″ operate in a normal (conventional) synchronized logic master/slave register run mode of operation at high speed clock rates, typically 3 GHz with VDD=1.3 volts, for logic products fabricated using the 130 nm technology node.
In normal run mode, at the beginning of a clock cycle, clock CLK 1140″ transitions from high to low voltage and remains at low voltage for the first half the clock cycle, and complimentary clock CLKb 1140′″ transitions from low to high voltage and remains at high voltage for the first half of the clock cycle. CMOS transfer device 1130″ turns ON coupling input node 1115″ voltage VIN to storage node 1135″. CMOS transfer device 1160″ turns OFF and isolates the output of volatile master latch stage circuit 1104″ from the input node 1120″ of volatile slave latch stage circuit 1106″. In normal run mode, clock CLK is connected to mode input 1192″ of volatile slave latch stage circuit 1106″, clock CLK is connected to CMOS transfer device 1185″, and complimentary clock CLKb output of inverter 1190″ is also connected to CMOS transfer device 1185″, such that CMOS transfer device also turns OFF breaking the feedback path between the output 1180″ of inverter 1175″ and the input 1120″ of inverter 1170″ such that node 1120″ does not act as a storage node. Voltage VIN may transition to a voltage value corresponding to the correct logic state any time prior to the end of the first half of the clock cycle, providing sufficient time remains for cross coupled inverters 1145″ and 1150″ to store the corresponding logic state on storage node 1155″ prior to clock transition at the beginning of the second half of the clock cycle.
Referring to
In operation, nonvolatile nanotube switch 1110″ is erased (turned OFF) prior to normal operation of nonvolatile register file stage circuit 1102″. During an erase operation, input VIN illustrated in
With NFET 1178″ ON, a VEPR erase pulse transitions to 10 volts as illustrated in waveforms 1250″ of
In operation, when transitioning from normal run mode to zero power nonvolatile retention mode, the logic state of volatile slave latch stage circuit 1106″ is transferred directly to nonvolatile nanotube switch 1110″ before power is turned OFF. As illustrated in waveforms 1250″ in
As illustrated in
If the logic state of volatile latch stage circuit 1106″ is such that VOUT is at zero volts, for example, then common node 1125″ is at zero volts, PFET 1177″ is ON and NFET 1178″ is OFF, then common node 1180″ is at or near positive voltage VPS, 3.0 volts for example. Program pulse transitions from 0 to VP of 5 volts as illustrated in
In operation, when transitioning from zero power nonvolatile retention mode to normal run mode, the state of nonvolatile nanotube switch 1110″ must be transferred directly to volatile slave latch stage circuit 1106″ after power supply VDD is restored, but before clock operation begins. A control circuit shown in
In the first restore timing increment, VEPR transitions to a positive restore voltage VR, 2.2 volts for example. Restore enable is set at voltage VDD, CLK transitions high (VDD for example), and CLKb transitions low. VIN is held low, zero volts for example. Volatile master latch stage circuit 1104″ drives and holds volatile slave latch stage circuit 1106″ VOUT low, zero volts for example, which turns PFET 1177″ ON and NFET 1178″ OFF (
In the second restore timing increment, VEPR transitions from 2.2 volts to 0 volts. If nonvolatile nanotube switch 1110″ is in the OFF state, then common node 1180″ remains positive at 2.2 volts and VOUT remains at or near zero volts; however, if nonvolatile nanotube switch 1110″ is in the ON state, then common node 1180″ voltage is reduced. If PFET 1177″ ON channel resistance is 1.75 MΩ and the ON resistance of nonvolatile nanotube switch 1110″ is 1 MΩ, for example, then common node 1180″ voltage drops from 2.2 volts to 0.8 volts, and volatile slave latch stage circuit 1106″ switches to the opposite state, with VOUT positive, at VDD for example. PFET 1177″ turns OFF and NFET 1178″ turns ON.
In the third restore timing increment, an erase operation is carried out to ensure that nonvolatile nanotube switch 1110″ is in the OFF state. Erase voltage VEPR is ramped up from zero to VE or approximately 10 volts, for example. If nonvolatile nanotube switch 1110″ is in an ON state of 1 MΩ, for example, and NFET 1178″ is in an ON state of 200 KΩ, for example, then current flows through nonvolatile nanotube switch 1110″ and NFET 1178″ in series, and approximately 8.3 volts is applied across nonvolatile switch 1110″ with a current of approximately 8.3 uA. For nonvolatile nanotube switch 1110″ erase conditions of at least 8 volts, and current in the 1 to 8 uA range, nonvolatile nanotube switch 1110″ switches to an OFF state. If nonvolatile nanotube switch 1110″ is in the OFF state, 1 GΩ, for example, then essentially all of the 10 volts erase pulse appears across the nonvolatile nanotube switch 1110″, and switch 1110″ remains in the OFF state. At this time, the restore operation is complete, and normal operation of nonvolatile register file stage circuit 1102″ may begin.
Meeting Higher Voltage Erase and Programming Requirements For Non-Volatile Nanotube Switches
FET devices used in volatile master latch stage circuit 1104 and volatile slave latch stage circuit 1106, which are part of nonvolatile register file stage circuit 1100 shown in
As discussed further above with respect to nonvolatile nanotube switch 1110 operation described in
Mode selection input 1420 determines if outputs 1430 and 1435 supply an erase voltage of approximately 10 volts, a program voltage of approximately 5 volts, or a restore voltage in the range of 1.3 to 2.5 volts, for example. The restore voltage may be supplied from the VDD supply instead of high voltage circuit 1400.
Output conductor 1440 supplies voltage to multiple nonvolatile nanotube switches 1110, 1110′, and 1110″ using an output stage including high voltage compatible PMOS 1445 and high voltage compatible NMOS 1450. High voltage compatible PMOS 1445 is connected to high voltage source 1410 by conductor 1430 and high voltage compatible NMOS 1450 is connected to ground. VREF voltages are zero volts (ground). A pre-output stage comprising high voltage compatible PMOS 1455 and high voltage compatible NMOS 1460 drives the input of the output stage. High voltage compatible PMOS 1455 is connected to high voltage source 1410 by conductor 1455 and high voltage compatible NMOS 1460 is connected to ground. The input of the pre-output stage is controlled by the output of decoder 1465. Input signals S1-SN determine which output conductor 1440 will be selected. The output of decoder 1465 connects to high voltage source 1410.
High voltage circuit 1400 layouts as described in U.S. Pat. No. 5,818,748 result in output conductor 1440 spacing with corresponding adjacent conductors of approximately two times the spacing when using low voltage circuits. For this invention, where nonvolatile nanotube switches 1110, 1110′, and 1110″ are used as shadow devices in register files, such output conductor 1440 spacing provide greater density than is required by this invention.
Transistors used in coupling circuit 1108 and 1108′ illustrated in
During a program operation, according to certain embodiments of the invention, a program voltage VEPR of 5 volts is applied to node 1112 of nonvolatile nanotube switch 1110 illustrated in
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in respects as illustrative and not restrictive.
This application claims priority under 35 U.S.C. § 119(e) to the following applications, the contents of which are incorporated herein in their entirety by reference: U.S. Provisional Patent Application No. 60/679,029, filed on May 9, 2005, entitled Reversible Nanoswitch;U.S. Provisional Patent Application No. 60/692,891, filed on Jun. 22, 2005, entitled Reversible Nanoswitch;U.S. Provisional Patent Application No. 60/692,918, filed on Jun. 22, 2005, entitled NRAM Nonsuspended Reversible Nanoswitch Nanotube Array; andU.S. Provisional Patent Application No. 60/692,765, filed on Jun. 22, 2005, entitled Embedded CNT Switch Applications For Logic. This application is related to the following applications, the contents of which are incorporated herein in their entirety by reference: U.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled Two-Terminal Nanotube Devices And Systems And Methods Of Making Same; andU.S. patent application Ser. No. 11/274,967, filed on Nov. 15, 2005, entitled Memory Arrays Using Nanotube Articles With Reprogrammable Resistance. This application is also related to U.S. patent application Ser. No. 11/032,983, filed on Jan. 10, 2005, entitled Storage Elements Using Nanotube Switching Elements; and U.S. patent application Ser. No. 11/231,213, filed on Sep. 20, 2005, entitled Random Access Memory Including Nanotube Switching Elements.
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