The present invention relates to the structure of a nonvolatile memory and, more particularly, to the structure of a flash memory with an ultra-low program current and a high-homogeneity erase architecture and a method of operating the same.
The complementary metal oxide semiconductor (CMOS) fabrication technology has become a common fabrication method of application specific integrated circuits (ASIC). Today, electrically erasable programmable read only memories (EEPROM) have been widely used in electronic products because of their non-volatile functions of electrically writing and erasing data.
Nonvolatile memory cells are programmable. Electric charges are stored to change the gate voltages of memory cell transistors, or electric charges are not stored to keep the original gate voltages of memory cell transistors. The erase operation removes all electric charges stored in nonvolatile memory cells to let all nonvolatile memory cells restore to the original gate voltages of memory cell transistors. Therefore, in the structure of a conventional nonvolatile memory cell, an extra conducting layer is added to store electric charges in addition to the gate layer of the transistor, hence forming a double-layer structure. As compared to the common CMOS fabrication process, there are more steps of film deposition, etch, and photolithography, hence increasing the cost, complicating the process, lowering the yield and lengthening the fabrication time.
A single-gate EEPROM structure has thus been proposed. This structure, however, has the problems of low reliability, interference from non-selected memory cells during the program step, and over erase.
Besides, in the erase method of the conventional EEPROM, stored electric charges will move from the floating gate to the transistor to be removed due to the Fowler-Nordheim tunneling (F-N tunneling) effect. Because the structure of a single-gate EEPROM memory cell is a sandwich structure of transistor substrate-floating gate-capacitor substrate, stored electric charges can be released to either direction according to the direction of the applied electric field, hence more deteriorating the problem of over erase of the single-gate EEPROM.
Accordingly, the present invention aims to propose a modified structure of a nonvolatile memory cell and a method of operating the same to effectively solve the above problems in the prior art and also shrinking the memory cell.
An object of the present invention is to provide a nonvolatile memory cell structure and a method of operating the same, wherein a single floating gate is used. When performing a program step, a nontrivial voltage is applied to the source or a back bias is applied to the transistor substrate to form a wider and depleted source/substrate junction, thereby improving the efficiency of current flowing to the floating gate and thus greatly reducing the current requirement of performing a program step to a single gate EEPROM.
Another object of the present invention is to provide a method of operating a nonvolatile memory cell. Through enhancing the source-drain voltage, the F-N tunneling current is regulated to perform an erase action to accomplish the effect of high-homogeneity erase.
Another object of the present invention is to provide a nonvolatile memory cell to accomplish the effects of a low operation current, high reliability and also miniaturize the size of the whole memory chip.
According to the present invention, a single-gate EEPROM memory cell comprises a MOFET and a capacitor structure. The MOSFET comprises a conducting gate stacked on the surface of a dielectric film. The dielectric layer is located on a semiconductor substrate. Two highly conductive doped regions are located at two sides of the conducting gate to form a source and a drain. The capacitor structure, the same as the transistor, is a sandwich structure of plate-dielectric layer-plate. The plate of the capacitor structure and the gate of the MOSFET are electrically connected together. The plate of the capacitor structure and the gate of the MOSFET form a single floating gate of the EEPROM memory cell. The semiconductor substrate is p-type, while the doped regions are an n-well; or the semiconductor substrate is n-type, while the doped regions are a p-well.
The method of operating the single-gate EEPROM comprises the program step of applying a nontrivial voltage to the source or a back-bias to the substrate of the MOSFET and the erase step of raising the source-drain voltage to regulate the F-N tunneling current. All operations of performing the program and erase steps to EEPROM of different structures are embraced within the scope of the invention.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
a) is a structure diagram with four terminals disposed in the first embodiment of
b) shows an effective circuit of
As shown in
As shown in
(1) a nontrivial source voltage program:
Therefore, Vcontrol>Vdrain>Vsource>Vsubstrate=0 (The NMOSFET is turned on to produce a gate current).
Or (2) a substrate back-bias program:
Therefore, Vcontrol>Vdrain>Vsource>Vsubstrate (The NMOSFET is turned on to produce a gate current).
As shown in
An ultra-low-current program condition of the single-gate EEPROM memory cell 30 in
(1) a nontrivial source voltage program:
Therefore, Vcontrol<Vdrain<Vsource<Vwell (The PMOSFET is turned on to produce a gate current), and Vcontrol>Vsubstrate (A back-bias is formed at the control gate/substrate N/P junction).
Or (2) a substrate back-bias program:
Therefore, Vcontrol<Vdrain<Vsource<Vwell (The PMOSFET is turned on to produce a gate current), and Vcontrol>Vsubstrate (A back-bias is formed at the control gate/substrate N/P junction).
As shown in
An ultra-low-current program condition of the single-gate EEPROM memory cell 30 in
(1) a nontrivial source voltage program:
Therefore, Vcontrol<Vdrain<Vsource<Vsubstrate (The PMOSFET is turned on to produce a gate current).
Or (2) a substrate back-bias program:
Therefore, Vcontrol<Vdrain<Vsource<Vsubstrate (The PMOSFET is turned on to produce a gate current).
As shown in
An ultra-low-current program condition of the single-gate EEPROM memory cell 30 in
(1) a nontrivial source voltage program:
Therefore, Vcontrol>Vdrain>Vsource>Vwell (The NMOSFET is turned on to produce a gate current), and Vcontrol<Vsubstrate (A reverse bias is formed at the control gate/substrate's N/P junction).
Or (2) a substrate back-bias program:
Therefore, Vcontrol>Vdrain>Vsource>Vwell (The NMOSFET is turned on to produce a gate current), and Vcontrol<Vsubstrate (A reverse bias is formed at the control gate/substrate's N/P junction).
The structure of
Using the same fabrication process, the memory cell in
In the present invention, when performing a program step, a nontrivial voltage is applied on the source of the single-gate MOSFET of the EEPROM memory cell. This nontrivial source voltage can produce a reverse voltage at the junction between the source and the substrate. The voltage drop between the source and the drain will allow channel carriers to move from the source to the drain. The reverse bias between the source and the substrate will further expand to the depleted junction region to produce a higher carrier density near the channel surface. The high carrier density near the channel surface will enhance the gate current effect to lower the total current required for program. Therefore, the reliability, program interference and program speed can be much improved. As compared to the technique of using no source voltage in the prior art, the improvement of the gate current efficiency can be as high as several hundred times.
Therefore, the program method of the present invention can greatly lower the current requirement of single-gate EEPROM. When erasing single-gate EEPROM, electric charges stored in the floating gate will be released to the substrate, and the voltages of the source and the drain of the MOSFET relative to the transistor substrate are raised to higher values to regulate the electric field distribution, hence lessening the problem of over erase. Besides, applying a back-bias to the semiconductor substrate can produce a wider depleted source-substrate junction to improve the efficiency of current flowing to the floating gate. This operation way can greatly lower the current requirement of performing a program step to single-gate EEPROM. Moreover, as for performing an erase step to single-gate EEPROM, the F-N tunneling current flows from the capacitor substrate via the floating gate to the transistor substrate. The voltages of the source and the drain of the MOSFET relative to the transistor substrate are raised to higher values to regulate the electric field distribution, hence lessening the problem of over erase.
During the program step, a high positive voltage is applied to each selectable word line. Meanwhile, a voltage of Vdd and a positive voltage much smaller than Vdd are applied to a bit line cut off from the detection circuit to accomplish the ultra-low-current program for positive logic and negative logic, respectively.
When performing an erase step, a high voltage is applied to several word lines of the same block, and a slightly positive voltage is applied to the sources and the drains of transistors to accomplish program homogeneity.
When performing a read-out step, the memory cell array is cut off from a high voltage circuit. Readout of a row is accomplished by applying a voltage of Vdd to select a word line. Because a higher gate value is not used to turn on the cell transistor, other bit lines won't be charged when charging the bit line on the cell transistor.
To sum up, the present invention proposes an EEPROM that can be fabricated with a single floating gate and the common CMOS fabrication process. Conducting gates of a capacitor structure and a transistor are connected together to form the single floating gate with a small size. Through the program step of applying a nontrivial voltage on the source or a back-bias on the transistor substrate and the erase step of raising the source-drain voltage to regulate the F-N tunneling current, the effects of ultra-low program current and high-homogeneity erase can be accomplished, thereby greatly improving the reliability, program interference and program speed.
Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
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Number | Date | Country | |
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20050270850 A1 | Dec 2005 | US |