Patent Grant
8482069
1. Field of the Invention
The present invention relates to a structure and a manufacturing method of an insulated gate semiconductor device having an SOI (silicon-on-insulator) structure, particularly an insulated-gate field-effect transistor (hereinafter referred to simply as IG-FET). An example of the insulated-gate semiconductor device having a SOI structure is a semiconductor device formed on an SOS (silicon-on-sapphire) substrate or a SIMOX (separated-by-implanted oxygen) substrate.
In particular, the invention relates to a technique that is effective in forming a very small element having a channel length of less than 0.35 μm (particularly less than 0.1 μm). Thus, the invention can be applied to various semiconductor integrated circuits such as ICs, VLSIs, and ULSIs that are formed by integrating IG-FETs.
The term “semiconductor device” as used in this specification means a “device or apparatus that utilizes a semiconductor to operate for an intended purpose,” and covers not only semiconductor elements such as an IG-FET but also integrated circuits formed by integrating semiconductor elements, and even electronic apparatuses incorporating such integrated circuits. In the specification, for convenience of description, various terms such as a semiconductor element, an integrated circuit, and an electronic apparatus are used where appropriate.
In another aspect, the present invention relates to the configuration of a nonvolatile memory formed by using a semiconductor. In particular, the invention for the nonvolatile memory in which the channel length is 2 μm or less or even 0.5 μm or less.
2. Description of the Related Art
In recent years, integrated circuits such as VLSIs are being miniaturized steadily, and the width of interconnections comes to decrease to 0.35-0.1 μm or less than 0.35 μm, or even to less than 0.01 μm (dimensions of a deep submicron processing range).
On the other hand, low power consumption is also required, which makes the lower power consumption characteristic of CMOS ICs indispensable. Where a CMOS IC is miniaturized, a problem of a latch-up phenomenon may occur between an n-type FET and a p-type FET. IG-FETs having an SOI structure solve this problem.
Because of complete insulation between a substrate and an element, IG-FETs having an SOI structure can greatly reduce a parasitic capacitance occurring there and hence allow pursuit of high-speed operation.
Thus, semiconductor devices having an SOI structure now attract much attention as next-generation high-speed elements and demand for those is expected to increase further in the future.
Such semiconductor elements have been miniaturized according to the scaling rule, and it is generally known that miniaturization of an integrated circuit leads to improvements in its characteristics. However, in microprocessing in a submicron range, problems may occur where the scaling rule does not apply in simple form.
A typical example of such problems is the short channel effects. The short channel effects are caused by a phenomenon that as the width of the gate electrode becomes shorter, that is, the channel forming region becomes shorter, the charge in the channel forming region, which should be controlled by the gate voltage, comes to be also influenced by the depletion layer charge and electric field and the potential profile in the source/drain region.
Normally, the current flowing through the channel region 3305 is controlled only by the gate voltage Vg. In this case, the portion of the depletion layer (indicated by the broken line 3307) in the vicinity of the channel region 3305 is substantially parallel with the channel, to allow formation of a uniform electric field.
However, as the drain voltage Vd is increased, the depletion layer in the vicinity of the drain region 3304 extends toward the channel region 3305 and the source region 3303, so that the charge and the electric field in the drain depletion layer come to influence the depletion layer in the vicinity of the source region 3303 and the channel region 3305 as indicated by a solid line 3308. As a result, the on-current varies depending on a complex electric field profile and is hard to control only by the gate voltage Vg.
Referring to
When a sufficiently large drain voltage Vd is applied, the energy band diagram changes to one indicated by broken lines in
In semiconductor elements, say, IG-FETs, the short-channel effects typically appear as a reduction in threshold voltage Vth and a reduction in device breakdown voltage due to the punch-through phenomenon. It is known that if the degree of influence of the gate voltage on the drain current is lowered by the punch-through phenomenon, the subthreshold characteristic is deteriorated.
The reduction in threshold voltage occurs in both n-channel and p-channel FETs in similar manners. The degree of the threshold voltage reduction depends on not only the drain voltage but also other various parameters such as the substrate impurity concentration, the source/drain diffusion layer depth, the gate oxide film thickness, and the substrate bias voltage.
Although the reduction in threshold voltage is desirable for the purpose of reducing the power consumption, in general a resulting reduction in the drive voltage of an integrated circuit causes demerits such as a difficulty in improving the frequency characteristic.
Further, when the channel length is shortened, the drain-side depletion layer is connected to the source-side depletion layer to lower the diffusion potential in the vicinity of the source, which in turn causes a current flow between the source and the drain even if a channel is not formed there. This is called the punch-through phenomenon.
When the punch-through phenomenon occurs, the drain current is not saturated even in the saturation range. Since a large current comes to flow as the drain voltage is increased, the source-drain breakdown voltage is considerably reduced which is a problem.
The deterioration in subthreshold characteristic due to the punch-through phenomenon means an increase in subthreshold coefficient (S-value), which in turn means deterioration in the switching characteristic of a FET.
It is seen that the slope of the characteristic decreases (the S-value increases) as the channel length is shortened, which means that the switching characteristic of a FET is more deteriorated as the channel length is shortened.
Various techniques have been proposed as means for suppressing the above-described short channel effects. For example, it was reported that in an SOI structure in which a substrate and an element are insulated from each other by a buried oxide film (by using a bonding technique, ion implantation, or some other technique), thinning the buried oxide film is effective in suppressing the short channel effects. However, this technique does not provide a complete solution.
A semiconductor device having an SOI structure in which the channel length is very short, i.e., about 0.1 μm, has a feature that impurity elements exist in the channel region at an extremely low probability (from one to some). Even at the room temperature, a phenomenon was observed that electrons move faster than in the ordinary case (the velocity overshoot effect; see K. Ohuchi et al., Jpn. J. Appl. Phys., Vol. 35, p. 960, 1996).
A high-speed semiconductor device was proposed whose high-speed operation performance was improved by utilizing the above effect. However, in such a high-speed semiconductor device, at present, the problems such as the punch-through phenomenon as one of the short channel effects and the associated deterioration in breakdown voltage (described above) remain unsolved.
As a means for suppressing the reduction in threshold voltage as one of the short channel effects, a technique has been employed in which an impurity element imparting one type of conductivity is added uniformly to the overall channel forming region and the threshold voltage is controlled by its addition amount. However, this method has a problem of a reduction in carrier mobility because the added impurity scatters carriers.
A single crystal silicon substrate as a mother substrate of an SOI substrate is manufactured by a FZ method with a very low oxygen content or a CZ method which allows oxygen to be contained to a certain extent to reduce stress and prevent a warp. Usually, a single crystal silicon substrate by the CZ method is used for memory ICs and logic ICs.
However, in a single crystal silicon substrate manufactured by the CZ method, the amount of warp increases due to a heat history and other factors as the oxygen content is reduced. Conversely, if the oxygen content is increased to such a level (usually, about 1-2×1018 atoms/cm3) that the amount of warp becomes sufficiently small, there may occur a case that oxygen atoms prevent movement of carriers.
In the current semiconductor industry, semiconductor integrated circuits that are integrated to an extreme, and the key point for this purpose is to what extent each semiconductor element can be miniaturized. However, even if a technique for forming a fine pattern in the deep submicron range were developed, the above-described problems of the short channel effects would be fatal obstructions to the miniaturization of semiconductor elements.
The IC memories that perform data storage and holding in computers are generally classified into the RAM and the ROM. Examples of the RAM (random access memory) are the DRAM (dynamic RAM) and the SRAM (static RAM). If the power is turned off, data stored in the DRAM or the SRAM are lost.
On the other hand, examples of the ROM (read-only memory) are the mask ROM and the PROM (programmable ROM). The mask ROM and the PROM have an advantage that even if the power is turned off, data stored there are not lost. The PROM is classified into the EPROM (erasable PROM) in which data erasure is performed by using ultraviolet light, the EEPROM (electrically erasable PROM) in which data erasure is performed electrically, the flash memory (flash EEPROM) in which data erasure is performed en bloc electrically, and other types.
To fully utilize their marked advantage of permanent data holding, studies and developments on nonvolatile memories have been made energetically. At present, the possibility of using nonvolatile memories instead of magnetic memories is being discussed.
As for such IC memories, it is necessary to not only improve the reliability and performance but also increase the storage capacity. That is, as in the case of other types of ICs, such memory ICs are being developed according to the scaling law while miniaturization techniques are always adopted.
However, since basically nonvolatile memories store data according to the same principle of operation as field-effect transistors (hereinafter referred to as FETs), the short channel effect, which is known as causing serious problems in the FET operation, also causes serious problems in the operation of nonvolatile memories as the miniaturization advances.
In particular, the phenomenon called “punch-through” decreases the source-drain breakdown voltage and hence makes the current control with the gate electrode difficult. A SSW-DSA structure (Nikkei Microdevices, pp. 47-48, May issue, 1992) is a conventional example of increasing the punch-through resistance.
In the field of the FET, the SSW-DSA structure is a structure that utilizes a technique called a pocket structure in which an impurity region having the same conductivity type as the substrate is provided in the channel-drain junction portion. This structure can prevent the occurrence of a punch-through phenomenon by suppressing the expansion of the drain depletion layer.
However, in nonvolatile memories, electron-hole pairs are generated by positively causing impact ionization in the channel-drain junction portion. Therefore, a large amount of holes flow to the substrate side as electrons are injected into the floating gate.
However, in the SSW-DSA structure, a large amount of holes thus generated act in no other way than flow into the substrate terminal. This may cause a problem that a parasitic source-substrate-drain bipolar is formed to cause a kink phenomenon (an abnormal increase in drain current).
The present invention has been made to solve the above problems in the art, and an object of the invention is therefore to provide a technique for effectively suppressing the short channel effects due to miniaturization of semiconductor elements. The invention is intended to enable formation of very small elements in the deep submicron range which have been difficult to form conventionally due to the short channel effects.
According to the invention, there is provided an insulated-gate semiconductor device having a SOI structure, comprising a source region, a drain region, and a channel forming region that are formed by using a crystalline semiconductor formed on an insulative substrate or an insulating layer: and a gate insulating film and a gate electrode formed on the channel forming region, the channel forming region comprising carrier movement regions; and impurity regions formed artificially and locally for pinning of a depletion layer developing from the drain region toward the channel forming region and the source region, the impurity regions containing an impurity element for shifting an energy band in such a direction that movement of electrons is obstructed.
Further, there is provided an insulated-gate semiconductor device having a SOI structure, comprising a source region, a drain region, and a channel forming region that are formed by using a crystalline semiconductor formed on an insulative substrate or an insulating layer; and a gate insulating film and a gate electrode formed on the channel forming region, the channel forming region comprising carrier movement regions; and impurity regions formed artificially and locally for pinning of a depletion layer developing from the drain region toward the channel forming region and the source region, the impurity regions containing an impurity element for shifting an energy band in such a direction that movement of holes is obstructed.
Further, there is provided an insulated-gate semiconductor device having a SOI structure, comprising a source region, a drain region, and a channel forming region that are formed by using a crystalline semiconductor formed on an insulative substrate or an insulating layer; and a gate insulating film and a gate electrode formed on the channel forming region, the channel forming region comprising carrier movement regions; and impurity regions formed artificially and locally by adding an impurity element to control a threshold voltage to a given value, the impurity element shifting an energy band in such a direction that movement of electrons is obstructed.
Still further, there is provided an insulated-gate semiconductor device having a SOI structure, comprising a source region, a drain region, and a channel forming region that are formed by using a crystalline semiconductor formed on an insulative substrate or an insulating layer; and a gate insulating film and a gate electrode formed on the channel forming region, the channel forming region comprising carrier movement regions; and impurity regions formed artificially and locally by adding an impurity element to control a threshold voltage to a given value, the impurity element shifting an energy band in such a direction that movement of holes is obstructed.
According to another aspect of the invention, there is provided a manufacturing method of an insulated-gate semiconductor device having an SOI structure, comprising the steps of forming a crystalline semiconductor on an insulative substrate or an insulating layer; forming a source region, a drain region, and a channel forming region by using the crystalline semiconductor; forming impurity regions artificially and locally in the channel forming region so that the channel forming region includes carrier movement regions and the impurity regions by adding, to the channel forming region, an impurity element for shifting an energy band in such a direction that movement of electrons is obstructed; and forming a gate insulating film and a gate electrode on the channel forming region.
Further, there is provided a manufacturing method of an insulated-gate semiconductor device having an SOI structure, comprising the steps of forming a crystalline semiconductor on an insulative substrate or an insulating layer; forming a source region, a drain region, and a channel forming region by using the crystalline semiconductor; forming impurity regions artificially and locally in the channel forming region so that the channel forming region includes carrier movement regions and the impurity regions by adding, to the channel forming region, an impurity element for shifting an energy band in such a direction that movement of holes is obstructed; and forming a gate insulating film and a gate electrode on the channel forming region.
The main point of the invention is to effectively suppress a depletion layer developing from the drain region toward the channel forming region by the impurity regions that are formed artificially and locally in the channel forming region, to thereby prevent various problems of the short channel effects such as the punch-through phenomenon, deterioration of the subthreshold characteristic, and decrease in breakdown voltage.
The present inventors call a device according to the invention a “pinning semiconductor device” based on an analogy to formation of pins (corresponding to the impurity regions) in the channel forming regions. In this specification, “pinning” means “prevention” and the verb “to pin” is used to mean “to prevent.”
That is, the impurity regions are formed locally in the channel forming region and utilized as energy barriers. By utilizing the impurity regions as energy barriers, the drain region side depletion layer is prevented, in terms of energy, from expanding toward the channel forming region side, whereby an electric field formed in the channel forming region is allowed to be controlled only by the gate voltage.
In the invention, the impurity regions are formed by using an impurity element that shifts the energy band in such a direction that the movement of carriers (electrons or holes) is obstructed. In the case of an n-channel FET, an element belonging to group 13 (typically, boron) may be used as such an impurity element. In the case of a p-channel FET, an element belonging to group 15 (typically, phosphorus or arsenic) may be used as such an impurity element.
The impurity regions formed by adding the above impurity element can shift the energy band of the channel forming region, and thereby change the threshold voltage to the positive or negative side. Therefore, the concentration of the added impurity element should be at least a level that enables threshold voltage control (typically 1×1017 to 1×1020 atoms/cm3, and preferably 1×1018 to 1×1019 atoms/cm3).
To enable the impurity regions to control the threshold voltage, the concentration of the impurity element should be at least about 100 times the substrate impurity concentration (in a typical single crystal silicon substrate, about 1×1015 atoms/cm3). Therefore, the lower limit of the concentration is set at 1×1017 atoms/cm3. Further, a concentration higher than 1×1020 atoms/cm3 is not preferable because of an increased load on a device.
The added impurity element causes formation of high energy barriers. For example, when boron (B) which an impurity element for imparting p-type conductivity is added to an n-channel FET, an energy band of a channel forming region shown in
Naturally, the shift of the Fermi level results in a shift of the energy band in the channel forming region. The impurity regions which are the feature of the invention have a conductivity type opposite to that of the other regions; although having low conductivity, they can sufficiently serve as energy barriers.
Similarly, when phosphorus (P) or arsenic (As) which is an impurity element for imparting p-type conductivity is added to a p-channel FET, an energy band of a channel forming region shown in
In the invention, the fact that the “carrier movement regions” are intrinsic or substantially intrinsic is an important feature characteristic of a semiconductor device having a SOI structure. In this specification, the term “intrinsic region” means a region not containing any impurity elements such as a single crystal silicon layer epitaxially grown on a sapphire substrate, or a region to which neither an impurity element for imparting n-type or p-type conductivity nor an impurity element such as carbon, nitrogen, or oxygen is added intentionally.
The term “substantially intrinsic region” means a region in a crystalline semiconductor (typically single crystal silicon in this specification) in which region a conductivity type that occurs even without intentionally adding any impurity elements for imparting n-type or p-type conductivity is canceled out, or a region which exhibits the same conductivity type as the source and drain regions to such an extent that threshold voltage control is possible.
As for the substantially intrinsic region, in the vicinity of the surface of a crystalline semiconductor (crystalline silicon) the concentration of an impurity element (phosphorus or boron) for imparting one type of conductivity is less than 5×1015 atoms/cm3 (preferably less than 5×1014 atoms/cm3) and the oxygen concentration is less than 2×1018 atoms/cm3 (preferably less than 1×1017 atoms/cm3.
The term “in the vicinity of the surface of a crystalline semiconductor” means a region capable of functioning as part of a device, and is a single crystal layer of a SOI substrate or a region including at least a carrier moving region (inversion layer), for instance. Since naturally the impurity regions which are the feature of the invention contain a large number of impurity elements, as a matter of course the concentration thereof do not fall within the above-mentioned range.
In this specification, single crystal silicon is used as a typical example of a crystalline semiconductor. The term “single crystal silicon” covers not only single crystal silicon that is commonly used in current manufacture of les and LSIs but also single crystal silicon of a higher level (in an extreme case, an ideal one as manufactured in the outer space).
The SOI structure is generally classified into two structures: one structure in which a single crystal silicon layer is grown on an insulative substrate, as typified by a SOS substrate; and the other structure in which an insulating layer is formed in a single crystal silicon substrate, as typified by a SIMOX substrate and a wafer bonding Sal structure. In particular, the SIMOX substrate is the mainstream of the SOI structure after the year 1986.
The invention is applicable to all types of SOI substrates irrespective of their manufacturing methods. That is, in manufacturing a semiconductor device according to the invention, a manufacturer can determine, as desired, how to manufacture an SOI substrate or obtain a single crystal silicon layer.
The present invention has been made in view of the above problems, and another object of the invention is therefore to realize a high-performance memory by effectively preventing or weakening the short channel effect that occurs in miniaturizing nonvolatile memories.
According to a first aspect of the invention, there is provided a nonvolatile memory comprising a source region, a drain region, and an active region that are formed by using a single crystal semiconductor; impurity regions provided locally in the active region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a second aspect of the invention, there is provided a nonvolatile memory comprising a substrate having an insulating surface; a source region, a drain region, and an active region that are formed over the substrate by using a semiconductor thin film that is a single crystal or is substantially regarded as a single crystal; impurity regions provided locally in the active region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a third aspect of the invention, there is provided a nonvolatile memory comprising a source region, a drain region, and an active region that are formed by using a single crystal semiconductor; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a fourth aspect of the invention, there is provided a nonvolatile memory comprising a source region, a drain region, and an active region that are formed by using a single crystal semiconductor; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element, the impurity regions serving to prevent a depletion layer from expanding from the drain region toward the source region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a fifth aspect of the invention, there is provided a nonvolatile memory comprising a substrate having an insulating surface; a source region, a drain region, and an active region that are formed over the substrate by using a semiconductor thin film that is a single crystal or is substantially regarded as a single crystal; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a sixth aspect of the invention, there is provided a nonvolatile memory comprising a substrate having an insulating surface; a source region, a drain region, and an active region that are formed over the substrate by using a semiconductor thin film that is a single crystal or is substantially regarded as a single crystal; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element, the impurity regions serving to prevent a depletion layer from expanding from the drain region toward the source region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
In the above nonvolatile memories, it is preferable that the impurity regions be provided in striped form so as to reach both of the source region and the drain region.
In the above nonvolatile memories, it is preferable that an impurity element contained in the impurity regions have a concentration that is 1×1017 to 5×1020 atoms/cm3.
In the above nonvolatile memories, it is preferable that the substrate be a crystallized glass substrate provided with an insulating film on a surface thereof.
It is effective to use any of the above nonvolatile memories as a recording medium.
The main feature of the invention is that impurity regions are formed locally in the active region and the impurity regions prevent a depletion layer from expanding from the drain region toward the source region. In this specification, a region that is enclosed by a source region, a drain region, and field oxide films is called an active region and the active region is divided into striped impurity regions and channel forming regions.
Since the effect of preventing expansion of a depletion layer looks like pinning the depletion layer, the inventors define the term “pinning” as meaning “prevention” (or “suppression”).
The present invention will be hereinafter described in detail by using embodiments.
Embodiment 1
This embodiment will be described with reference to
In
Reference numeral 105 denotes impurity regions (hereinafter referred to as pinning regions) that are the most important feature of the invention. The pinning regions 105 are formed by adding an impurity having the same conductivity type as the silicon substrate 101. In the example of
The element selected from group-13 or group-15 elements shifts the energy band of single crystal silicon and thereby acts as an energy barrier to carriers (electrons or holes). In this sense, the pinning regions can also be called energy-banded-shifted regions. Elements other than the group-13 and group-15 elements can also be used as long as they have such an effect.
The effect of adding an energy-band-shifting element will be described below with reference to conceptual diagrams of
In the impurity-added region, although no change occurs in the energy band gap, the Fermi level (Ef) is moved to the valence band (Ev) side. As a result, the energy is shifted upward in appearance and hence an energy barrier having higher energy than the undoped regions by ΔE (for electrons) is formed.
If an impurity element (an element selected from group-15 elements) that shifts the energy band in such a direction as to obstruct the movement of holes is added to single crystal silicon, the energy band is changed to a state as shown in
In the impurity-added region, the Fermi level is moved to the conduction band (Ec) side. As a result, the energy is shifted downward in appearance and hence an energy barrier having higher energy than the undoped regions by ΔE (for holes) is formed.
As described above, an energy difference of ΔE occurs between the undoped regions where the impurity is not added and the pinning regions 105. The height of the energy (i.e., potential) barrier depends on the concentration of the added impurity element. In the invention, the impurity element concentration is adjusted in a range of 1×1017 to 5×1020 atoms/cm3 (preferably 1×1018 to 5×1019 atoms/cm3).
Since the formation of the pinning regions 105 is enabled by microprocessing technology, it is necessary to use an impurity adding method suitable for microprocessing, such as ion implantation or an FIB (focused ion beam) method. Where an impurity adding method using a mask is employed, it is desirable to use microprocessing, for instance, forming a mask pattern by electron beam lithography.
Most typically, the pinning regions 105 are formed in such a manner that the pinning regions 105 are approximately parallel with channel forming regions 106 and the pinning regions 105 and the channel forming regions 106 are arranged alternately as shown in
It is effective to form pinning regions 105 at side end portions of the active region where the active region is in contact with the field oxide films 102. The formation of pinning regions 105 at the side end portions can reduce leak current that passes through the side end portions.
It is sufficient to form the pinning regions 105 so that they at least reach the junction portion of the active region and the drain region 104 (i.e., the drain junction portion). The intended effect can be obtained by preventing the expansion of the depletion layer at the drain junction portion because the depletion layer that causes the punch-through phenomenon develops from the drain junction portion. That is, the expansion of the depletion layer can be suppressed by forming dot-like or elliptical pinning regions 105 in the active region so that part of them exist in the drain junction portion.
Naturally, a more effective pinning effect can be obtained by forming the pinning regions 105 so that they reach both of the source region 103 and the drain region 104 as shown in
It is desirable that the implantation depth of the pinning regions 105 be greater than the junction depth of the source region 103 and the drain region 104. Therefore, it is necessary the implantation depth be 0.1-0.5 μm (preferably 0.2-0.3 μm).
Now, the channel length and the channel width will be defined with reference to
The width of an arbitrary pinning region 304 is called a pinning width vj. The pinning width vj may be set to 1 μm or less, typically 0.01-0.2 μm and preferably 0.05-0.1 μm. An effective pinning width V that is the sum of the widths of all pinning regions 304 existing in the active layer 303 is defined as
To obtain the pinning effect, it is necessary to form at least one pinning region 304 in the active region 303; that is, a condition n=1 or more needs to be satisfied. Where pinning regions 304 are formed at the side end portions (adjoining field oxide films) of the active region 303, a condition n=2 or more needs to be satisfied.
The width of a channel forming region 305 is called a channel width wi. The channel width wi can be set to any value. For memories in which large current is not required, the channel width wi may be set to 1 μm or less, typically 0.05-0.5 μm and preferably 0.1-0.3 μm.
An effective channel width W that is the sum of all channel widths wi is defined as
Where the pinning regions 304 are formed only at the side end portions of the active region 303, m=1 is satisfied. A more effective pinning effect can be obtained by forming pinning regions 304 also in regions other than the side end portions of the active region 303. In such a case, m becomes 2 or more.
A total channel width Wtotal that is the sum of the sum of the widths of all pinning regions 304 (i.e., the effective pinning width) and the sum of the widths of all channel forming regions 305 (i.e., the effective channel width) is defined as
Wtotal=V+W
The total channel width Wtotal corresponds to the width of the active region 303 (i.e., the length of the active region 303 in the direction perpendicular to the channel length direction). The direction along the total channel width Wtotal is called a channel width direction.
Since the invention is intended to be applied to nonvolatile memories having an extremely short channel length as mentioned above, the pinning regions 304 and the channel forming regions 305 need to be formed so as to have extremely small dimensions.
Returning to
The invention is characterized in that pinning regions are formed locally (i.e., in striped form) in a region of a conventional nonvolatile memory that serves as a channel forming region. Therefore, the other structures of the conventional nonvolatile memory can be employed as they are.
That is, a tunnel oxide film 107 is also formed on the single crystal silicon substrate 101 on which the source region 103, the drain region 104, and the pinning regions 105 are formed. The tunnel oxide film 107, which is formed by a thermal oxidation step, is required to have high film quality. In this embodiment, the thickness of the tunnel oxide film 107 is set to 11 nm. It goes without saying that the thickness of the tunnel oxide film 107 is not limited to this value.
In this embodiment, the pinning regions 105 may be formed even after the formation of the tunnel oxide film 107.
A first polysilicon layer as a floating gate 108 is formed on the tunnel oxide film 107. It is important to construct so that as shown in
A large amount of hot electrons are generated by concentrated electric fields at the above junction portions. Therefore, hot electrons can be injected at high efficiency by covering those junction portions with the floating gate 108.
After the formation of the floating gate 108, a first interlayer film 109, a second polysilicon layer as a control gate 110, a second interlayer film 111, and a bit line 112 are formed.
Naturally, a conductive layer such as a metal film can be used instead of the polysilicon layer. It is also effective to use, as the interlayer film, a laminated film as expressed by SiO2/SIN/SiO2 (commonly called an ONO film).
The two-layer polysilicon EEPROM of this embodiment is given a circuit representation shown in
In the EEPROM of this embodiment, the following voltages are applied at the time of data writing and erasure.
Naturally, the operation voltages are not limited to the values of Table 1. Further, the invention is not limited to the structure of the first embodiment and can be applied to any kinds of EEPROMs in which data is erased electrically.
Functions and Advantages of the Invention
A first advantage of the invention will be described below. In
Next, a second advantage will be described. In the invention, the narrow channel effect can be enhanced intentionally by the pinning regions. The narrow channel effect, which is a phenomenon observed when the channel width is extremely narrow, causes an increase in threshold voltage (refer to Koyanagi et al., “Submicron Devices I,” pp. 88-138, Maruzen Co., Ltd., 1987).
As seen from
In this manner, high-energy barriers are formed in the pinning regions 105 and the threshold voltage increases there. As a result, a threshold voltage that is observed as a value of the entire EEPROM also increases. This narrow channel effect becomes more remarkable as the effective channel width W decreases.
As described above, in the invention, since the concentration of an impurity that is added to the pinning regions 105 and the effective channel width W can be designed freely, the threshold voltage can be adjusted by controlling the degree of the narrow channel effect. That is, by properly controlling the pinning effect, the threshold voltage can be adjusted to a desired value by balancing a threshold voltage decrease due to the short channel effect with a threshold voltage increase due to the narrow channel effect.
Since a group-13 element is added to the pinning regions 105 in an n-type device and a group-15 element is added in a p-type device, the threshold voltage is shifted in the pinning regions 105 in a direction in which its absolute value increases (in the positive direction in an n-type device and in the negative direction in a p-type device). Since the threshold voltage increases locally, the threshold voltage of the entire device increases accordingly. Therefore, to adjust the threshold voltage to a desired value, it is important to set the concentration of an impurity that is added to the pinning regions 105 at a proper value.
Incidentally, in nonvolatile memories, discrimination between “0” and “1” is made by changing the threshold voltage by injecting charge (mainly electrons) into the floating gate and detecting whether current flows through the bit line when a certain voltage is applied. Therefore, if the threshold voltage is made unduly small by the short channel effect, it becomes necessary to discriminate between “0” and “1” by applying a very small voltage. In this case, the device becomes prone to be influenced by noise or the like and the possibility of occurrence of an erroneous operation increases.
In contrast, in the invention, since the threshold voltage can be controlled to have a desired value by decreasing a threshold voltage reduction, the ability of discriminating between “0” and “1” is increased. Therefore, the invention can realize a nonvolatile memory having very high reliability.
Next, a third advantage will be described. The nonvolatile memory according to the invention has an advantage that majority carriers (electrons in an n-type device and holes in a p-type device) move through the channel forming regions 106 that are substantially intrinsic regions.
The term “substantially intrinsic region” basically means an undoped single crystal semiconductor region, and includes a region where conductivity type compensation is made intentionally by adding an impurity element of the opposite conductivity type, and a region having one conductivity type in a range where the threshold voltage can be controlled.
For example, it can be said that a silicon wafer having a dopant concentration of 5×1016 atoms/cm3 or less (preferably 5×1015 atoms/cm3 or less) and carbon, nitrogen, and oxygen contents of 2×1018 atoms/cm3 or less (preferably 5×1017 atoms/cm3 or less) is substantially intrinsic. In this sense, silicon wafers commonly used are substantially intrinsic unless an impurity is added intentionally in a process.
Where a carrier movement region is substantially intrinsic, a mobility reduction due to the impurity scattering is extremely small and hence high carrier mobility is obtained. Therefore, the carrier movement is dominated by the influence of the lattice scattering and a state that is very close to the ideal state is obtained.
Where the straight pinning regions 105 are formed so as to reach both of the source region 103 and the drain region 104 as shown in
As described above, each channel forming region interposed between pinning regions has an energy profile as shown in
Defining the movement paths of majority carriers decreases the degree of scattering due to self-collision of carriers, which greatly contributes to mobility increase. Further, since only a very small amount of impurity elements exist in the substantially intrinsic channel forming regions, the velocity overshoot effect occurs, which is a phenomenon that the electron mobility becomes higher than usual even at room temperature (refer to K. Ohuchi et al., Jpn. J. Appl. Phys., Vol. 35, p. 960, 1996). Therefore, the mobility becomes extremely high.
High carrier mobility that is obtained as described above is effective in shortening the charge write time and the charge read time, thereby increasing the memory performance. High carrier mobility means presence of carriers having high energy, and hence the charge writing efficiency is greatly increased by channel hot electron (CHE) injection.
Next, a fourth advantage of the invention will be described. Where the structure of the invention is employed, an electric field is concentrated to a large extent at the junction portions (typically, a p+/n++ junction or an n+/p++ junction is formed) of the pinning regions and the drain region. Therefore, there occur a large amount of electrons that are given high energy through acceleration or generated by impact ionization (collectively called hot electrons).
Therefore, charge injection into the floating gate is performed very efficiently and hence the data write time can be shortened; specifically, it is reduced to 1/10 to 1/100 of that of conventional cases. By utilizing the invention, the data write time of a 256 Mbit stacked flash memory, which will be realized in the future, can be made 10 ns/byte or less, preferably 0.01-1 ns/byte.
Since this means realization of a data write operation faster than that of magnetic memories, it becomes possible to replace all kinds of current hard disks that are magnetic memories with flash memories. Since very small chips of flash memories will have functions equivalent to those of conventional magnetic memories, the miniaturization and the price reduction of devices will be accelerated.
The invention is also effective in decreasing the voltage necessary for data writing (i.e., the write voltage). Specifically, by virtue of accelerated hot electron injection due to concentrated electric fields at the pinning regions/drain junction portions, charge of the same amount as in conventional cases can be injected by a write voltage that is ½ to 1/10 of conventional values.
Therefore, while current stacked flash memories requires a write voltage of about 10 V, the invention can realize a write voltage of 5 V or less, preferably about 1-3 V.
As described above, the hot electron inject efficiency at the drain junction portions can be increased by forming the pinning regions. This is effective in reducing the power consumption and increasing the degree of freedom in circuit designing.
Next, a fifth advantage will be described. The fact that the pinning regions of the invention have the functions of preventing the short channel effect and controlling the threshold voltage has been described above. In addition, the pinning regions of the invention have a very important role in preventing a parasitic bipolar from being rendered conductive due to impact ionization.
Conventionally, electrons of electron-hole pairs generated by impact ionization are injected into the floating gate. On the other hand, holes flow into the substrate and cause a substrate current, which renders a parasitic bipolar conductive.
In contrast, in the invention, holes generated by impact ionization immediately move into the pinning regions and extracted to the source region via the pinning regions. Therefore, the holes do not render a parasitic bipolar conductive and hence do not lower the source-drain breakdown voltage.
It goes without saying that this effect is particularly remarkable when the pinning regions are formed so as to reach both of the source and drain regions. Holes can be extracted more efficiently if the pinning regions are in contact with a pickup electrode in the source region.
Embodiment 2
This embodiment will be described with reference to
In
Although this is an example structure of an n-type EEPROM, it is also possible to construct a p-type EEPROM. A p-type EEPROM can be constructed by forming source and drain regions by adding boron to an n-type silicon substrate.
The single crystal silicon substrate having a buried oxide film may be a SIMOX substrate, a UNIBOND substrate (a smart cut method is used), or the like. Naturally, other types of known SOI substrates may also be used.
It is preferable that the thickness of a single crystal silicon thin film formed on the buried oxide film 601 be set to 10-100 nm (typically 30-50 nm). As the thickness decreases, the hot electron injection occurs more easily and hence the write voltage can be made smaller.
Reference numeral 605 denotes impurity regions (pinning regions) that are the most important feature of the invention. The pinning regions 605 are formed by adding an impurity having the same conductivity type as the silicon substrate 601 (i.e., the conductivity type opposite to that of the source region 603 and the drain region 604).
In this embodiment, since the p-type silicon substrate 601 is used (the single crystal silicon thin film is also p-type), the pinning regions 605 are formed by adding an element selected from group-13 elements (typically boron). Naturally, where an n-type silicon substrate is used (a p-type EEPROM is to be manufactured), pinning regions may be formed by adding an element selected from group-15 elements (phosphorus, arsenic, or the like).
The element selected from group-13 or group-15 elements shifts the energy band of single crystal silicon and thereby acts as an energy barrier to carriers (electrons or holes). In this sense, the pinning regions can also be called energy-banded-shifted regions. Elements other than the group-13 and group-15 elements can also be used as long as they have such an effect. In the invention, the impurity element concentration is adjusted in a range of 1×1017 to 5×1020 atoms/cm3 (preferably 1×1018 to 5×1019 atoms/cm3).
Since the formation of the pinning regions 605 is enabled by microprocessing technology, it is necessary to use an impurity adding method suitable for microprocessing, such as ion implantation or a FIB (focused ion beam) method. Where an impurity adding method using a mask is employed, it is desirable to use microprocessing, for instance, forming a mask pattern by electron beam lithography.
Most typically, the pinning regions 605 are formed in such a manner that the pinning regions 605 are approximately parallel with channel forming regions 606 and the pinning regions 605 and the channel forming regions 606 are arranged alternately as shown in
It is effective to form pinning regions 605 at side end portions of the active region where the active region joins to the field oxide films 602. The formation of pinning regions 605 at the side end portions can reduce leak current that passes through the side end portions.
It is sufficient to form the pinning regions 605 so that they at least reach the junction portion of the active region and the drain region 604 (i.e., the drain junction portion). The intended effect can be obtained by preventing the expansion of the depletion layer at the drain junction portion because the depletion layer that causes the punch-through phenomenon develops from the drain junction portion. That is, the expansion of the depletion layer can be suppressed by forming dot-like or elliptical pinning regions 605 in the active region so that part of them exist in the drain junction portion.
Naturally, a more effective pinning effect can be obtained by forming the pinning regions 605 so that they reach both of the source region 603 and the drain region 604 as shown in
It is desirable that the implantation depth of the pinning regions 605 be such that the pinning regions 605 reach or go into the buried oxide film 601. In this embodiment, since the thickness of the single crystal silicon thin film is set to 10-100 nm (typically 30-50 nm), the implantation depth of the pinning regions 605 may be adjusted in a range of 10-150 nm (typically 30-100 nm).
Now, the channel length and the channel width will be defined with reference to
The width of an arbitrary pinning region 304 is called a pinning width vj. The pinning width vj may be set to 1 μm or less, typically 0.01-0.2 μm and preferably 0.05-0.1 μm. An effective pinning width V that is the sum of the widths of all pinning regions 304 existing in the active layer 303 is defined as
To obtain the pinning effect, it is necessary to form at least one pinning region 304 in the active region 303; that is, a condition n=1 or more needs to be satisfied. Where pinning regions 304 are formed at the side end portions (adjoining field oxide films) of the active region 303, a condition n=2 or more needs to be satisfied.
The width of a channel forming region 305 is called a channel width wi. The channel width wi can be set to any value. For memories in which large current is not required, the channel width wi may be set to 3 μm or less, typically 0.1-2 μm and preferably 0.1-0.5 μm.
An effective channel width W that is the sum of all channel widths wi is defined as
Where the width of the active region 303 is extremely small, for instance, 0.3 μm or less, the number of pinning regions 304 that can be formed in the active region 303 is limited. In such a case, the pinning regions 304 may be formed only at the side end portions of the active region 303.
In such a case, the number m of channel forming regions 305 is equal to 1. A more effective pinning effect can be obtained by forming pinning regions 304 also in regions other than the side end portions of the active region 303. In such a case, m becomes 2 or more.
A total channel width Wtotal that is the sum of the sum of the widths of all pinning regions 304 (i.e., the effective pinning width) and the sum of the widths of all channel forming regions 305 (i.e., the effective channel width) is defined as
Wtotal=V+W
The total channel width Wtotal corresponds to the width of the active region 303 (i.e., the length of the active region 303 in the direction perpendicular to the channel length direction). The direction along the total channel width Wtotal is called a channel width direction.
Since the invention is intended to be applied to nonvolatile memories having an extremely short channel length as mentioned above, the pinning regions 304 and the channel forming regions 305 need to be formed so as to have extremely small dimensions.
Returning to
The invention is characterized in that pinning regions are formed locally (preferably in striped form) in a region of a conventional nonvolatile memory that serves as a channel forming region. Therefore, the other structures of the conventional nonvolatile memory can be employed as they are.
That is, a tunnel oxide film 607 is also formed on the single crystal silicon thin film on which the source region 603, the drain region 604, and the pinning regions 605 are formed. The tunnel oxide film 607 is formed by a thermal oxidation step because it is required to have high film quality. In this embodiment, the thickness of the tunnel oxide film 607 is set to 11 nm. It goes without saying that the thickness of the tunnel oxide film 607 is not limited to this value.
In this embodiment, the pinning regions 605 may be formed even after the formation of the tunnel oxide film 607.
A first polysilicon layer as a floating gate 608 is formed on the tunnel oxide film 607. It is important to construct so that as shown in
A large amount of hot electrons are generated by concentrated electric fields at the above junction portions. Therefore, hot electrons can be injected at high efficiency by overlapping those junction portions with the floating gate 608.
After the formation of the floating gate 608, a first interlayer film 609, a second polysilicon layer as a control gate 610, a second interlayer film 611, and a bit line 612 are formed.
Naturally, a conductive layer such as a metal film can be used instead of the polysilicon layer. It is also effective to use, as the interlayer film, a laminated film as expressed by SiO2/SIN/SiO2 (commonly called an ONO film).
The two-layer polysilicon EEPROM of this embodiment is given a circuit representation shown in
In the EEPROM of this embodiment, the following voltages are applied at the time of data writing and erasure.
Naturally, the operation voltages are not limited to the values of Table 1. Further, the invention is not limited to the structure of this embodiment and can be applied to any kinds of EEPROMs in which data is erased electrically.
Embodiment 3
The two-layer polysilicon EEPROMs of the first and second embodiments are classified into a byte erasure type (data erasure is performed on a unit memory element basis) and a flash type (data of collective memory elements are erased en bloc).
The flash EEPROM is also called the flash memory. The invention can be applied to either of the two types of EEPROMs.
There are various data erasing methods such as a source erasure type, a source/gate erasure type, and a substrate erasure type. The invention can be applied to any of those methods.
Embodiment 4
While the first and third embodiments were directed to the two-layer polysilicon EEPROM using a single crystal semiconductor, this embodiment is directed to a case where the invention is applied to a three-layer polysilicon EEPROM. This embodiment will be described below with reference to
Since an EEPROM of this embodiment has the same basic structure as the two-layer polysilicon EEPROM described in the first embodiment, the reference numerals used in
In the EEPROM that is configured according to the first embodiment, data erasure is performed by extracting, to the substrate side (the source region 103 or the bulk substrate 101), electrons that have been injected into the floating gate 108. In contrast, in the EEPROM that is configured according to this embodiment, data erasure is performed by extracting, to the erasing gate 701, electrons that have been injected into the floating gate 108.
Therefore, in
The EEPROM of this embodiment can be manufactured basically by the same process as that of the first embodiment with an exception that a step of forming the erasing gate 701 and the erasing gate insulating film 702 after formation of the pinning regions 105 is added.
An EEPROM having an erasing gate like the one of this embodiment is given a circuit representation shown in
In the EEPROM of this embodiment, the following voltages are applied at the time of data writing and erasure.
Naturally, the operation voltages are not limited to the values of Table 2. Further, the invention is not limited to the structure of this embodiment and can be applied to any kinds of EEPROMs having an erasing gate structure.
Embodiment 5
While the second and third embodiments were directed to the two-layer polysilicon EEPROM using a single crystal silicon substrate having a buried oxide film, this embodiment is directed to a case where the invention is applied to a three-layer polysilicon EEPROM. This embodiment will be described below with reference to
Since an EEPROM of this embodiment has the same basic structure as the two-layer polysilicon EEPROM described in the second embodiment, the reference numerals used in
In the EEPROM that is configured according to the second embodiment, data erasure is performed by extracting, to the source region, electrons that have been injected into the floating gate 608. In contrast, in the EEPROM that is configured according to this embodiment, data erasure is performed by extracting, to the erasing gate 801, electrons that have been injected into the floating gate 608.
Therefore, in
The EEPROM of this embodiment can be manufactured basically by the same process as that of the second embodiment with an exception that a step of forming the erasing gate 801 and the erasing gate insulating film 802 after formation of the pinning regions 605 is added.
An EEPROM having an erasing gate like the one of this embodiment is given a circuit representation shown in
In the EEPROM of this embodiment, the following voltages are applied at the time of data writing and erasure.
Naturally, the operation voltages are not limited to the values of Table 2. Further, the invention is not limited to the structure of this embodiment and can be applied to any kinds of EEPROMs having an erasing gate structure.
Embodiment 6
The nonvolatile memories according to the first to fifth embodiments utilize hot electron injection and Fowler-Nordheim current for data writing and erasure, respectively. This type of operation mode is called a stack mode.
The invention can also be applied to nonvolatile memories using Fowler-Nordheim current also for data writing. This type of operation mode is classified into a NAND type, an AND type, and a DINOR type.
In particular, in manufacturing a large-capacity memory of 256 Mbits or more, to improve the reliability (i.e., to elongate the life by decreasing the rate of deterioration) it is preferable to write data by using Fowler-Nordheim current.
Embodiment 7
The first embodiment was directed to the two-layer polysilicon EEPROM in which data erasure is performed electrically. On the other hand, the nonvolatile memory in which electrons that have been injected into the floating gate are extracted to the source or the substrate by exciting those by ultraviolet illumination or heating is called an EPROM. The invention can also be applied to the EPROM.
Among various kinds of EPROMs is a nonvolatile memory not using a floating gate in which a two-layer gate insulating film is provided between a control gate and a silicon substrate and hot electrons are captured by interface states of the two-layer gate insulating film. For example, a nonvolatile memory in which hot carriers are captured at the interface between a silicon oxide film and a silicon nitride film is called an NMOS nonvolatile memory.
Further, there are nonvolatile memories in which hot carriers are captured by metal clusters, silicon clusters, or the like that are formed intentionally at an interface between insulating films.
The invention can be applied to all kinds of EPROMs as exemplified above.
Embodiment 8
Since the invention is applicable to all kinds of conventional nonvolatile memories, it can be applied to all the known circuit configurations. This embodiment is directed to a case where the invention is applied to flash memories that are designed according to the NAND and NOR type architectures, respectively.
First, a description will be made of the configuration of a NAND-type memory circuit shown in
As shown in
Although this embodiment is directed to a case where eight memory transistors are connected to each other in series, the number of memory transistors is not limited to 8.
The selection transistor 902 is connected to a final-stage memory transistor 913. The other terminal of the selection transistor 902 is grounded. Even if it is connected to a power supply line, the memory circuit still operates properly.
The memory transistors 906-913 use word lines W1-W8 (914-921) as control gates, respectively.
Next, a description will be made of the configuration of a NOR-type memory circuit shown in
As shown in
The memory transistors 1002-1005 use word lines W1-W4 (1007-1010) as control gates, respectively.
Although NAND-type circuits as shown in
The configuration of the NOR-type circuit shown in
Although this embodiment is directed to the circuits that use nonvolatile memory cells having a two-layer electrode structure (polysilicon or the like), the same circuits can be configured by using nonvolatile memory cells having the three-layer electrode structure (including the erasing gate) as described above in the fourth or fifth embodiment.
Embodiment 9
This embodiment is directed to a case where a nonvolatile memory according to the invention is applied to a microprocessor that is integrated on one chip, such as a RISC processor or an ASIC processor.
The microprocessor of
In the microprocessor of
In this manner, the basic concept of the invention can be applied to MOSFETs as well as nonvolatile memories, as disclosed in detail in Japanese Patent Laid-Open No. Hei. 10-65163. Japanese Patent Laid-Open No. Hei. 10-65163 has a corresponding U.S. patent application Ser. No. 08/912,979, which is herein incorporated by reference.
The flash memory 14 uses nonvolatile memory cells according to the invention that form a memory circuit 20. Every memory cell that constitutes the memory circuit 20 is formed with pinning regions 21. It is possible to use nonvolatile memory cells according to the invention also in the cache memory 12.
As described above, in the example of
As occasion demands, a configuration shown in
In this manner, it is possible to determine, at the circuit designing stage, sections where pinning regions should be formed; a party who practices the invention may determine at will whether to form pinning regions in the entire circuit or only part of it. Where the invention is applied to a hybrid IC in which various functions are combined, such a high degree of freedom in circuit design is very effective.
Embodiment 10
This embodiment is directed to a case where a nonvolatile memory according to the invention that uses a single crystal silicon substrate having a buried oxide film is applied to a microprocessor such as a RISC processor or an ASIC processor that is integrated on one chip.
The microprocessor of
In the microprocessor of
In this manner, the basic concept of the invention can be applied to SOIFETs as well as nonvolatile memories, as disclosed in detail in Japanese Patent Laid-Open No. Hei. 10-93100. Japanese Patent Laid-Open No. Hei. 10-93100 has a corresponding U.S. patent application Ser. No. 08/931,697, which is herein incorporated by reference.
The flash memory 34 uses nonvolatile memory cells according to the invention that form a memory circuit 40. Every memory cell that constitutes the memory circuit 40 is formed with pinning regions 41. It is possible to use nonvolatile memory cells according to the invention also in the cache memory 32.
As described above, in the example of
As occasion demands, a configuration shown in
In this manner, it is possible to determine, at the circuit designing stage, sections where pinning regions should be formed; a party who practices the invention may determine at will whether to form pinning regions in the entire circuit or only part of it. Where the invention is applied to a hybrid IC in which various functions are combined, such a high degree of freedom in circuit design is very effective.
Embodiment 11
The second embodiment was directed to the case (typically a SIMOX substrate) where a buried oxide film is provided in a single crystal silicon substrate and a single crystal silicon thin film is formed on the buried oxide film. On the other hand, a single crystal silicon thin film can be formed on crystallized glass, quartz, or ceramics by utilizing a technique called a smart cut method.
Where crystallized glass is used, it is effective to cover the entire surfaces (front, back, and side surfaces) with insulating silicon films. This measure makes it possible to prevent pollution due to glass constituent substances even when a high-temperature heat treatment is performed.
Since it is possible to use a kind of crystallized glass having approximately the same thermal expansion coefficient as a silicon film, stress occurring in a silicon thin film can be minimized. This is very important in manufacturing a highly reliable device.
For example, in a case of manufacturing a LCD (liquid crystal display) that is constituted of TFTs and nonvolatile memory cells using a single crystal silicon thin film, no stress-induced warp occurs even if an inexpensive glass substrate is used as an opposed substrate as long as crystallized glass is used as a device-side substrate. (A warp may occur due to a difference in thermal expansion coefficient if quartz used as a device-side substrate, in which case it is necessary to use an expensive quartz substrate as an opposed substrate.)
As described above, constructing a nonvolatile memory in which crystallized glass is used as a substrate and a single crystal silicon thin film is formed on an insulating film that covers the substrate is very effective in manufacturing a low-price product. The invention can easily be applied to such a case.
Embodiment 12
Although the second, third, fifth to eighth, 10th, and 11th embodiments were directed to the SOI structure in which a single crystal silicon thin film is used as a semiconductor layer, the single crystal silicon thin film used in each of those embodiments may be replaced by a polysilicon film.
A nonvolatile memory according to this embodiment will be described with reference to
In
Although quartz may be used as a material having high heat resistance, an inexpensive crystallized glass substrate is used in this embodiment rather than an expensive quartz substrate. To prevent an escape of glass components, the crystallized glass substrate 50 is covered with a protective film 51 that is an insulating silicon film (a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like).
An active layer that is a polysilicon thin film having a unique crystal structure is formed on the protective film 51, and a source region 52, a drain region 53, pinning regions 54, and channel forming regions 55 are formed in the active layer by adding an impurity to it. A method for forming the polysilicon thin film will be described later.
Then, a gate insulating film 56 is formed on the surface of the active layer (polysilicon thin film). Subsequently, an erasing gate 57 and a tunnel oxide film 58 are formed and then a floating gate 59 is formed.
After a first interlayer film 60 is formed so as to cover the floating gate 59, a control gate 61, a second interlayer film 62, a ground line 63, and a bit line 64 are sequentially formed to complete a stacked nonvolatile memory (EEPROM).
In this embodiment, as described above, a polysilicon thin film having a unique crystal structure that has been developed by the present assignee is used as the active layer (including the source region, the channel forming region, and the drain region).
Although naturally a polysilicon thin film formed by a known method may be used, to increase the operation speed of the memory itself and decrease the write voltage, it is desirable to use a polysilicon thin film having the above-mentioned unique crystal structure.
A technique for forming a polysilicon thin film having the unique crystal structure will be described below with reference to
In
Where the amorphous silicon film 72 is formed by low-pressure CVD, it is preferable to remove films formed on the back and side surfaces before a later crystallization step. According to experiences of the inventors, the crystal state appears to be deteriorated if the crystallization step is executed with amorphous silicon films left on the back and side surfaces (the reason is unknown).
It is possible to use other semiconductor thin films such as a thin film of a silicon-germanium compound SiXGe1-X (0<X<1). The thickness of the amorphous silicon film 73 may be set to 25-100 nm (preferably 30-60 nm).
Then, the step of crystallizing the amorphous silicon film 72 is executed by using a technique that is disclosed in Japanese Patent Laid-Open No. Hei. 7-130652 of the present inventors. Although either of the techniques described in the first and second embodiments of this publication, in this invention it is preferable to use the technique of the second embodiment of this publication (described in more detail in Japanese Patent Laid-Open No. Hei. 8-78329).
In the technique disclosed in the publication No. Hei. 8-78329, a mask insulating film 73 for selecting a catalyst element adding region is formed first. A catalyst element containing layer 74 is formed by applying a solution containing a catalyst element for accelerating crystallization of the amorphous silicon film 72 by spin coating (see
The catalyst element may be one or a plurality of elements selected from nickel (Ni), cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), and lead (Pb). It is desirable to use nickel that has a good lattice matching relationship with silicon.
The above step of adding the catalyst element may be executed by ion implantation or plasma doping each of which uses a mask, rather than spin coating. Since the use of ion implantation or plasma doping facilitates reduction of the area occupied by the catalyst element adding region and control of the growth length of a lateral growth region, it is a technique effective in constructing a miniaturized circuit.
After the completion of the catalyst element adding step, hydrogen removal is performed at 500° C. for 2 hours. Then, the amorphous silicon film 72 is crystallized by performing a heat treatment at 500°-700° C. (typically 550°-650° C., preferably 570° C.) for 4-24 hours in an inert atmosphere, a hydrogen atmosphere, or an oxygen atmosphere (see
In this step, the crystallization of the amorphous silicon film 72 proceeds with priority from nuclei that are generated in the region where the catalyst element is added, whereby crystal regions 76 are formed in which the crystallization has proceeded approximately parallel with the surface of the crystallized glass substrate 70. The inventors call the crystal regions 76 lateral growth regions. The lateral growth region has an advantage that it has superior crystallinity as a whole because individual crystals are combined together so as to be arranged relatively uniformly.
After the completion of the heat treatment for crystallization, the mask insulating film 73 is removed. Then, a heat treatment for removing the catalyst element (catalyst element gettering step) is performed. In this heat treatment, a halogen element is mixed into a processing atmosphere to utilize the metal element gettering effect of the halogen element.
To fully effectuate the gettering effect of the halogen element, it is preferable to perform the heat treatment at a temperature higher than 700° C. At a temperature lower than 700° C., there is a possibility that a halogen compound in the processing atmosphere is hard to decompose and resultantly the gettering effect is not obtained. It is preferable to set the heat treatment temperature and time at 800°-1,000° C. (typically 950° C.) and 0.1-6 hours (typically 0.5-1 hour), respectively.
Typically, the heat treatment may be performed at 950° C. for 30 minutes in an oxygen atmosphere containing a hydrogen chloride (HCl) gas at 0.5-10 vol % (preferably 3 vol %). A HCl density higher than the above range is not preferable because asperities whose heights are on the order of the film thickness will occur on the silicon surface.
Other than HCl, the compound containing a halogen element may be one or a plurality of compounds selected from HF, NF3, HBr, Cl2, ClF3, BCl3, F2, and Br2.
In this step, the catalyst element in the lateral growth regions 76 are gettered by the action of chlorine and removed into the air in the form of a volatile chloride. After the execution of this step, the concentration of the catalyst element in lateral growth regions 76 is reduced to 5×1017 atoms/cm3 or less (typically 2×1017 atoms/cm3 or less).
Although in this embodiment the catalyst element is gettered by the gettering ability of a halogen element, it is also possible to utilize the gettering ability of the element of phosphorus. In such a case, there may be employed a gettering step in which a layer containing phosphorus at a high concentration is provided adjacent to the lateral growth regions 76 and a heat treatment is performed to cause the phosphorus-containing layer to getter the catalyst element.
The resulting lateral growth regions 76 has a unique crystal structure that is a collected body of rod-like or flat-rod-like crystals. In the nonvolatile memory of this embodiment, a polysilicon thin film constituted of only a lateral growth region 76 is used as the active layer.
Specifically, the unique crystal structure is a structure in which rod-like crystals are arranged approximately parallel with each other and have particular directivity macroscopically. Further, individual crystals are connected to each other with extremely high continuity at their grain boundaries.
Detailed observation results of such a crystal structure are described in Japanese Patent Application Serial Nos. Hei. 9-55633, Hei. 9-165216, and Hei. 9-212428.
A polysilicon thin film formed by the above steps has grain boundaries where individual crystals are connected to each other with extremely high continuity (with a high level of matching), and the grain boundaries cause almost no obstruction to carrier movements. That is, this polysilicon thin film can be regarded as a silicon thin film having substantially no grain boundaries and hence can substantially be regarded as a single crystal (as a matter of fact, this polysilicon thin film exhibits an electron beam diffraction pattern that is very close to that of a single crystal).
The above polysilicon thin film is intrinsic or substantially intrinsic unless no impurity is added intentionally. The term “intrinsic” as used here means a state that impurities (i.e., atoms other than silicon atoms) are eliminated as much as possible and the polarity is almost negligible.
The invention can be applied to all kinds of nonvolatile memories using a semiconductor thin film that can substantially be regarded as a single crystal (i.e., a polycrystalline semiconductor thin film having the crystal structure described in this embodiment).
Embodiment 13
This embodiment is directed to a case where an impurity element for imparting the same conductivity type as the conductivity type of the pinning regions is added to the insulating layer (buried oxide film or the like) that underlies the semiconductor layer in the nonvolatile memory using the single crystal silicon substrate having the buried oxide film that was described in any of the second, third, fifth to eighth, and 10th to 12th embodiments.
In this embodiment, boron is used as an impurity that is added to the pinning regions.
In
The structure of
The energy profiles of
As shown in
On the other hand, as shown in
If the concentration of the impurity added to the pinning regions 84 and 85 and that of the impurity added to the buried oxide film 82 are the same, b is equal to b′. If they are different from each other, b is not equal to b′. The invention may be of either case.
In the invention, it is preferable that the relative energy value b or b′ be three times or more (ever preferably 10 times or more) larger than the relative energy value a. This provides a structure in which carriers (electrons or holes) move through the low-energy region 88 with priority.
Since a high energy barrier is formed at the interfaces between the channel forming region 83 and the buried oxide film 82 and its vicinity and keeps carriers away from itself, carrier scattering can be prevented from occurring in the vicinity of the surface of the underlying film (buried oxide film 82).
The above structure makes it possible to effectively suppress expansion of the depletion layer and to further increase the resistance to the short channel effect. In addition, by reducing the degree of carrier scattering in the vicinity of the surface of the underlying film, the hot electron injection can be made more efficient.
Embodiment 14
A semiconductor circuit (memory circuit) formed by nonvolatile memory cells according to the invention can be incorporated, as a recording medium for data storage and readout, in electronic apparatuses of every field. In this embodiment, examples of those electronic apparatuses will be described with reference to
Examples of electronic apparatuses which can use a nonvolatile memory of this embodiment are a video camera, an electronic still camera, a projector, a head-mounted display, a car navigation apparatus, a personal computer, portable information terminals (a mobile computer, a cellular telephone, a PHS, etc.).
As described above, the application range of the invention is extremely wide and the invention can be applied to electronic apparatuses of every field. In addition to the above examples, a nonvolatile memory of the invention can be used as a storage medium that is indispensable in various control circuits and information processing circuits.
The invention makes it possible to minimize influences of the miniaturization effects as typified by the short channel effect and to further advance the miniaturization of nonvolatile memories.
The invention also makes it possible to realize small-area, large-capacity nonvolatile memories while securing their high reliability.
With reference to
The invention is characterized in that impurity regions 3104 are formed artificially and locally in the channel forming region 3103. Although in this example the impurity regions 3104 are formed in linear patterns, it is possible to form impurity regions in dot patterns.
It is desirable to form the impurity regions 3104 in linear patterns that are generally parallel with the channel direction (i.e., the direction connecting the source and the drain or the carrier movement direction). This is because in such a case the impurity regions 3104 serve as side walls to form energy rails that define movement of carriers, so that the probability of occurrence of scattering due to collision between carriers is reduced, resulting in an advantage of an increase in mobility.
The inventors call the carrier moving paths (i.e., the regions between the impurity regions 3104) potential slit regions or lane regions.
The following description is directed to a case where the linearly patterned impurity regions 3104 are formed generally parallel with the channel direction from one end to the other of the channel forming region 3103 (for instance, from the source region 3101 to the drain region 3102). and boron is employed as an impurity to be added.
As described above, a built-in potential difference that serves as a sufficiently high energy barrier for movement electrons is formed in the impurity regions in which the energy band is shifted by the addition of boron to such a direction that the movement of electrons (majority carriers) is obstructed. Therefore, carriers (in this case, electrons) do not travel through the impurity regions 3104.
In particular, it is desirable that the impurity regions 3104 be disposed at the junction portion between the drain region 3102 and the channel forming region 3103 as shown in
The invention is very effective in forming a very small element that requires microprocessing in a deep submicron range of less than 0.35 um (particularly less than 0.1 um) or even less than 0.01 μm. Since the length of the channel forming region (channel length or source-drain distance) is as short as 0.01-0.35 um, the impurity regions should be patterned to have even smaller dimensions.
For example, where a resist mask is used to form impurity regions in linear patterns, ordinary exposing methods cannot be used to pattern a resist mask, i.e., form openings in a resist film because of their insufficient resolution. In such a case, fine patterns in a deep submicron range may be realized by an exposing method using an excimer laser of KrF, ArF, or the like, an electron beam drawing method, a FIB (focused ion beam) method, or the like.
Since the impurity regions are arranged artificially by patterning, they can be arranged not only in the manner shown in
Next, a description will be made of how the short channel effects can be suppressed when the insulated-gate semiconductor device (IG-FET) having the structure of
The width of an n-th impurity region 3104 in the channel forming region 3103 is represented by Wpi,n and the interval between adjacent impurity regions (i.e. the width of an m-th potential slit region (carrier movement path) in the channel forming region 3103) is represented by Wpa,m.
The above description is merely directed to the structure, and the operation of the IG-FET will be described below.
When a gate voltage and a drain voltage are applied to the semiconductor device having the structure of
Although it is difficult to understand the arrangement of the impurity regions 3204 from
Thus, in the semiconductor device having the structure of the invention, the depletion layers are separated from each other and do not interfere with each other as shown in
That is, in contrast to the conventional energy state shown in
Further, in the invention, as shown in
The S-value is given by a following equation.
S≈d(Vg)(log Id).
It is seen that, as described above, the S-value represents the reciprocal of the slope in range 3501 in the graph of
S≈ln 10(kT/q){1+(Cd+Cit)/Cox}
where k is the Boltzmann constant, T is the absolute temperature, q is the magnitude of electronic charge, Cd is the depletion layer capacitance, Cit is the equivalent capacitance of interface states, and Cox is the gate oxide film capacitance. In the invention, since the depletion layer capacitance Cd is sufficiently smaller than in the conventional case, the S-value can be made as small as less than 85 mV/decade (preferably less than 70 mV/decade), to provide a superior subthreshold characteristic.
The invention aims to make the depletion layer capacitance Cd and the equivalent capacitance of interface states Cit as close to 0 as possible, that is, to make the S-value as close to the value (60 mV/decade) of the ideal state (Cd=Cit=O) as possible.
Further, the fact that the channel forming region has the structure shown in
The narrow channel effect, which was originally observed in a MOSFET formed on bulk silicon, is a phenomenon in which the threshold voltage increases being influenced by a bird's beak of a device isolation field oxide film, impurity diffusion from a channel stopper, and other factors when the channel width is narrowed.
One of the important concepts of the invention is to intentionally cause the narrow channel effect by artificially forming and arranging the impurity regions in the channel forming region. According to this concept, the threshold voltage is controlled by precisely controlling the distance between adjacent impurity regions (Wpa,m in
For example, when attention is paid to a certain cross-section as in the case of
It is considered that the narrow channel effect is obtained in each of the plurality of regions having a narrow channel width Wpa,m. Macroscopically, the regions that exhibit the narrow channel effect exist over the entire channel forming region as shown in
Therefore, threshold voltage control can be effected such that an increase in threshold voltage due to the above-described narrow channel effect compensates for a decrease in threshold voltage (short channel effect) caused by shortening of the channel length. As a result, a variation in threshold voltage can be reduced.
The invention as summarized above will be described in detail in the following embodiments. The following embodiments are merely examples of the invention, and can be modified in various manners in accordance with the needs of semiconductor device manufacturers.
Therefore, the claims should cover any changes and modifications of the following embodiments as long as they are made without departing from the spirit and scope of the invention.
Embodiment 15
In this embodiment, with reference to
First, a single crystal silicon substrate 3701 having weak n-type or p-type conductivity is prepared. A buried oxide film 3702 is formed by implanting oxygen ions at a dose of 1×1018 atoms/cm2 and then performing a heat treatment in a temperature range of 800°-1,300° C. Thus, a buried oxide film 3702 of 0.05-0.5 um in thickness and a single crystal silicon layer 3703 of 100-2,000 Å in thickness (Preferably 200-600 Å) are obtained.
As one of the most remarkable features of the SOI technology, the single crystal silicon layer 3703 has almost no, i.e., only one to several, impurity elements (already contained in the mother substrate 3701), and is therefore extremely pure and intrinsic or substantially intrinsic.
Naturally the thicknesses of the buried oxide film 3702 and the single crystal silicon layer 3703 are not limited to the ranges of this embodiment, and may be adjusted properly when necessary. For a detailed description of the SIMOX substrate, reference is made to, for instance, Fumio Shimura, “Semiconductor Silicon Crystallographic Engineering,” published by Maruzen Co., Ltd. on Sep. 30, 1993, pp. 217 onward.
Thus, a SIMOX substrate is obtained as shown in
In the state of
Then, a device isolation field oxide film 3706 is formed by performing thermal oxidation at a high temperature of 1,000-1,2000° C., to obtain regions 3707 and 3708 to become active layers of the n-channel and p-channel FETs, respectively.
In the state of
The regions for phosphorus implantation and those for boron implantation may be determined by using resist masks. The regions to which no impurity has been added remain intrinsic or substantially intrinsic and constitute channel forming regions 3713 and 3714 of the n-channel and p-channel FETs, respectively (see
Where the channel forming region is an intrinsic or substantially intrinsic region as in the above case, the active layer of a semiconductor device, say, an n-channel FET, has a configuration of n+(source region)/i(channel forming region)/n+(drain region), where n+ means strong n-type conductivity and i means intrinsic or substantially intrinsic.
Example of other possible configurations are n+(source region)/n−−(channel forming region)/n+(drain region) and p+(source region)/p−−(channel forming region)/p+(drain region), where n−− means very weak n-type conductivity and p−− means very weak p-type conductivity.
Conventionally, the above configuration has a problem of a reduction in breakdown voltage though it has an advantage of an increased mobility. According to the invention, which enables formation of a semiconductor device having a high breakdown voltage, requirements of a high mobility and a high breakdown voltage can be satisfied at the same time.
In the state of
Since the impurity regions 3715 and 3716 need to be formed at extremely small dimensions, an accurate lithography technique is required for that purpose. To this end, exposure may be performed in linear patterns by a technique using an electron beam (electron beam drawing method), a technique using an ion beam (FIB method), a technique using an excimer laser, or a like technique. To form the fine impurity regions 3715 and 3716 with high accuracy, it is preferred to add the impurity element by an ion implantation method.
It is preferred to activate the impurity element that is added to the impurity regions 3715 and 3716 by furnace annealing, laser annealing, lamp annealing, or the like. Care should be taken so as to minimize the thermal diffusion. For example, if furnace annealing is conducted at about 500°-800° C. (Preferably 600°-700° C.), sufficient activation can be effected while thermal diffusion of the impurity element is suppressed.
Alternatively, the impurity element may be activated at the same time as its implantation by heating the substrate during the ion implantation. The impurity element activation efficiency at the time of the ion implantation is improved by increasing the RF power of the ion implantation. The impurity element may be activated either by one of the above-mentioned annealing processes or by a combination of those.
In forming the impurity regions 3715 and 3716, the width Wpa,m of each potential slit region is controlled so as to fall within a range of 30-3,000 Å (preferably 30-1,000 Å). All the widths Wpa,m are controlled so as to fall within a variation range of ±20% (preferably ±5%). It is important to precisely control the widths Wpa,m of the potential slit regions because they directly influence the narrow channel effect.
The lower limit width 30 Å of the potential slit regions is determined as a limit value above which no quantum effect occurs. In the invention, care should be taken so that the widths of the potential slit regions are controlled so as to fall within the range where no quantum effect occurs.
Thus, the impurity regions 3715 and 3716, which are arranged as shown in the top view of
To increase the breakdown voltage of the semiconductor device, it is effective to form the impurity regions 3715 and 3716 so that they go into the drain regions 3710 and 3712, respectively, as shown in
Where LDD regions are provided between the channel forming region 3713 or 3714 and the source and drain regions 3709 and 3710 or 3711 and 3712, it is preferred that the impurity regions 3715 or 3716 be formed so as to go into the LDD region or go into the drain region 3710 or 3712 past the LDD region. The above configurations are effective in increasing the breakdown voltage of the semiconductor device.
In the state of
It is preferred that the above thermal oxidation treatment be conducted in a halogen atmosphere. In such a case, heavy metals such as Ni (nickel) and Cu (copper) that segregate at the interfaces between the impurity regions 3715 and 3716 and the potential slit regions can be removed by gettering.
The above heavy metals are ones that are left inside in not a small amount, for instance, in the process of forming single crystal silicon, and act as carrier recombination centers to possibly lower the mobility. By conducting the thermal oxidation treatment in a halogen atmosphere, it is expected that a halogen element (for instance, chlorine or fluorine) exhibits a gettering effect on the metal elements.
Polysilicon films 3719 and 3720 as gate electrodes are further formed on the thermal oxidation films 3717 and 3718 over the channel forming regions 3713 and 3714, respectively. The gate electrodes 3719 and 3720 may be rendered conductive by adding an impurity element during their formation. Thus, the state of
Then, as shown in
In this state, a titanium film (not shown) is formed over the entire surface by sputtering, and then silicified by heating, laser annealing, or lamp annealing. As a result, titanium silicide layers 3723-3725 are formed on the surfaces of the source region 3709, drain region 3710, and gate electrode 3719 of the n-channel FET, and titanium silicide layers 3726-3728 are formed on the surfaces of the source region 3711, drain region 3712, and gate electrode 3720 of the p-channel FET (see
The formation of the titanium silicide layers 3713-3728 is favorable for taking ohmic contact to later formed interconnections because the titanium silicide layers 3713-3728 have extremely low resistivity.
In this state, a silicon nitride film 3729 is formed as an interlayer insulating film. After contact holes are formed through the silicon nitride film 3729, source electrodes 3730 and 3731 for the n-channel and p-channel FETs, respectively, and a drain electrode 3732 for both n-channel and p-channel FETs are formed. Thus, CMOS IG-FETs are completed as shown in
Capable of being miniaturized without causing any problems of the short channel effects by virtue of the invention, the CMOS circuit having the structure of
Although the embodiment is directed to a single gate IG-FET, the invention can also be applied to a case of manufacturing a double gate FET having channels on both top and bottom surface sides of an active layer because of the SOI structure. It goes without saying that the invention can also be applied to a power MOSFET, a MESFET, a MISFET, etc.
This embodiment is characterized in that the impurity regions are formed in linear patterns in the channel forming region of an IG-FET. Certain conditions (in ranges of parameters) need to be satisfied in forming the linear patterns, as described below with reference to
In
Since to realize the invention at least one impurity region needs to be formed at a position excluding both side ends of the channel forming region, N is an integer greater than or equal to 1.
Of the channel width W, the total width of potential slit regions (carrier movement paths) 3903 is represented by Wpa. which is set in a range where the quantum effect does not appear, that is, 30-3,000 Å (preferably 30-1,000 Å). According to the invention, threshold voltages Vth,n and Vth,p can be adjusted so as to fall within a range of 0 to ±0.3 V by making Wpa. about 1/3 to 1/1 of the channel length (0.01-0.35 μm). Let the widths of the respective linear patterns 3902 be represented by Wpa,1, Wpa,2, . . . , Wpa,m, . . . , Wp1,M; then Wpa, is given by is given by
Since as mentioned above at least one impurity region needs to be formed at a position other than both sides of the channel forming region, M is an integer greater than or equal to 2.
Thus, relationships the channel width W=Wpi+Wpa and N+M≧3 hold. It is desirable that the following conditions be satisfied simultaneously with respect to relationships between W and Wpi, between W and Wpa, and Wpi, and Wpa:
Wpi/W=0.1 to 0.9
Wpa/W=0.1 to 0.9
Wpi/Wpa=1/9 to 9
The above equations mean that Wpa/W and Wpi/W should not be 0 or 1. For example, if Wpa/W=0(i.e., Wpi/W=1), the channel forming region is completely filled with the impurity region as shown in
Conversely, Wpa/W=0(i.e., Wp/W=0), there exists no impurity region in the channel forming region and hence the expansion of the drain-side depletion layer cannot be suppressed.
For the above reasons, it is desirable that Wpa/W and Wpi/W fall within the range of 0.1-0.9 (preferably 0.2-0.8) and, at the same time, Wpi/Wpa=1/9 to 9 be satisfied.
In the invention, for the reasons described below, arranging the linearly patterned impurity regions as shown in
The mobility is determined by scattering of carriers in a semiconductor (in this embodiment, a silicon substrate), and scattering in a silicon substrate is generally classified into lattice scattering and impurity scattering. The lattice scattering is dominant when the impurity concentration in a silicon substrate is low and the temperature is relatively high, and the impurity scattering is dominant when the impurity concentration is high and the temperature is relatively low. The total mobility μ, which reflects both factors, is given by
μ=(1/μ1+1/λi)−1. (5)
The above equation means that the total mobility II is in inverse proportion to the sum of reciprocals of mobility μ (suffix “1” is for lattice) that reflects influence of the lattice scattering and mobility μ (suffix “i” is for impurity) that reflects influence of the impurity scattering.
As for the lattice scattering, acoustic phonons play an important role if the drift electric field is not strong and the mobility μ in such a state is in proportion to the (−3/2)th power of the temperature as given by Formula (6). Thus, the mobility μ is determined by only the effective mass m* of carriers and the temperature T.
μ1∝(m*)−5/2T−3/2 (6)
On the other hand, the mobility λi which relates to the impurity scattering is in proportion to the (3/2)th power of the temperature and in inverse proportion to a concentration Ni of ionized impurities as given by Formula (7), and can be varied by adjusting a concentration Ni of ionized impurities.
μi∝(m*)−5/2T−3/2 (7)
Formulae (6) and (7) indicate that the conventional channel doping of adding an impurity to the entire channel forming region cannot improve the mobility because of the influence of the impurity scattering. In contrast, in the invention, the impurity regions are formed locally and therefore no impurity is added to the potential slit regions whose total width is Wpa.
Theoretically, the concentration Ni of ionized impurities in Formula (7) is made infinitely close to 0 and hence the mobility μ approaches infinity. In Equation (5). it is meant that the impurity concentration is reduced to such an extent that the term 1/μi is disregarded, and hence the total mobility μ becomes infinitely close to the mobility μ1.
It is theoretically possible to further increase the mobility 4, by decreasing the carrier effective mass m*. This can be done by utilizing the fact that in a very low temperature range the effective mass of carriers (particularly electrons) varies depending on the crystal axis orientation.
According to the literature, the minimum effective mass is obtained when the channel direction (carrier movement direction) connecting the source and the drain is set coincident with the [100] axis direction of single crystal silicon.
For example, assume that a source region 4002, a channel forming region 4003, and a drain region 4004 are formed on a single crystal silicon substrate 4001 having the [100] plane as shown in
Further, to allow carriers to “slip through” crystal lattices, it is desirable that the channel direction and the longitudinal axis direction of the impurity regions be generally parallel with the crystal lattice axial direction (the deviation be made within ±10°. In the case of a single crystal where silicon atoms are arranged regularly, carriers moving parallel with a crystal lattice arrangement direction are scarcely influenced by the lattice scattering.
For example, if the rotation axis in the above-mentioned direction is defined as 0° in a single crystal silicon substrate, the same effects can be obtained with other rotation axes of 90°, 180°, and 270°.
As described above, in the channel forming regions carriers go through the regions other than the impurity regions. This will be described briefly with reference to schematic drawings of
In
In
Most of carriers move between the source and the drain through the regions between the impurity regions 4102 as indicated by the arrow. The invention naturally includes a case where impurity regions are provided in dot patterns and carriers move in a zigzag so as to avoid the impurity regions.
In a potential slit region that is interposed between linearly patterned impurity regions, it is the energy state (potential state) is believed to have a profile as schematically shown in
In
The inventors recognizes the energy profile of
Although in
For the reasons described above, the probability that a carrier collides with other carriers is very much reduced and hence the mobility is greatly increased. That is, according to the invention, the mobility can be greatly increased not only by reducing the impurity scattering but also by reducing the scattering due to self-collision of carriers.
The concept of the invention is entirely novel in which energy barriers such as grain boundaries, which are conventionally believed to cause only adverse effects, are formed intentionally and utilized.
Embodiment 16
In the invention, impurity regions may be formed in a channel forming region by utilizing segregation of an impurity. In this embodiment, with reference to
This embodiment is a technique which utilizes a phenomenon that an impurity element (boron or phosphorus) that is contained around the impurity regions (i.e., in the potential slit regions) segregates in the impurity regions. Now, referring to
As shown in
m=[C]Si/[C]SiOx.
The segregation of the impurity in the vicinity of the Si/SiOx interface is governed by the value of m. Usually, with an assumption that diffusion coefficient of the impurity in Si is sufficiently large, the impurity in Si is taken into SiOx if m<1 (see
According to the literature, the coefficient m is about 0.3 for boron and about 10 for phosphorus. Therefore, a boron concentration profile after execution of the thermal oxidation treatment of this embodiment. becomes as shown in
Although the phenomenon that boron is taken into a thermal oxidation film was known, the concept of the invention in which this phenomenon is utilized to form energy barriers (impurity regions) is entirely novel.
Where phosphorus is used as an impurity element, it segregates (piles up) at the interface between a thermal oxidation film and silicon as shown in
Next, with reference to
A resist pattern 4403 for formation of impurity regions is formed on a channel forming region by using a fine lithography technique such as an electron beam method, a FIB method, or an excimer laser method.
In the state of
The above ion implantation is performed by using an electrically inactive element because it aims at damaging the single crystal silicon layer 4402. This is because this embodiment utilizes a tendency that when single crystal silicon is thermally oxidized, damaged regions are oxidized with preference given thereto.
Thus, Ar-added regions 4404 in
After the resist pattern 4403 is removed, a heat treatment is performed in a temperature range of 800°-1,200° C. as shown in
The heat treatment in the first 30 minutes is for thermal oxidation and that in the last 30 minutes is for gettering of metal elements. The reason why the last heat treatment is performed in an atmosphere containing a large amount of nitrogen is to prevent excessive oxidation of the single crystal silicon layer 4402.
Thus, a thermal oxidation film 4405 is formed in the single crystal silicon layer 4402 as shown in
Alternatively, the embodiment may be practiced by damaging the single crystal silicon layer 3402 by directly applying, for instance, an electron beam or a focused ion beam to the single crystal silicon layer 3402.
In the process that the impurity regions 3406 are formed by oxidation in the above manner, an impurity element contained in the adjacent potential slit regions is segregated.
Therefore, if an impurity element for imparting one type of conductivity to the channel forming region is added to it, the impurity element segregates in the impurity regions 3406 (in the case of boron) or on the side surfaces of the impurity regions 3406 (in the case of phosphorus). The configuration of the first embodiment of the invention can be obtained by causing boron to segregate in oxide regions to manufacture an n-channel PET and causing phosphorus to segregate on the side surface of oxide regions to manufacture a p-channel PET.
Since this embodiment utilizes both of the metal element gettering effect of a halogen element and the segregation of boron or phosphorus in or on a thermal oxidation film, there exist neither causes of impurity scattering nor impurity elements as recombination centers in the carrier movement regions (particularly in the vicinity of the impurity regions 3406) which are intrinsic or substantially intrinsic.
As described above, this corresponds to increase of μi in Equation (5), in which case the total mobility μ approaches the ideal case of μ=μi. This indicates that an extremely high mobility can be realized which is determined substantially only by the lattice scattering. Thus, this embodiment enables formation of a semiconductor device having an extremely high mobility.
Embodiment 17
This embodiment is directed to a case of forming dot-pattered impurity regions in a channel forming region. This embodiment will be described with reference to
A semiconductor device of
Although this embodiment employs circular impurity regions as the dot-patterned impurity regions, the dot-patterned impurity may have an elliptical shape, a square shape, a rectangular shape, or the like.
The dot-patterned impurity regions do not provide the role of the lane regions of the first embodiment. However, since the effective channel area (carrier movable area) is larger than in the case of the linearly patterned impurity regions, the dot-patterned impurity regions can increase the amount of current that is allowed to flow through a semiconductor device.
Embodiment 18
In the first and third embodiments, the impurity regions have the simplest forms, i.e., linear patterns and dot patterns, respectively. This embodiment is directed to variations of the shape of the impurity regions.
As seen from
It is desirable that as shown in
However, in this structure, it is unavoidable that the movement distance of carriers is increased because they move along a path indicated by a broken line 4604. The increased movement distance would increase the carrier scattering probability, which may in turn reduce the mobility.
However, in very fine semiconductor devices for which the invention is effective, a small increase in movement distance would not much increase the influence of the impurity scattering as long as the channel forming region is intrinsic or substantially intrinsic. Suppressing the influences of the short channel effects (particularly the punch-through phenomenon) due to the miniaturization is more important than the above issue.
As for each impurity region, it is necessary to control the distance (represented by Lpa in
In the structure of
The invention may have variations in the case of the dot-patterned impurity regions as well as the linearly patterned ones. For example, impurity regions 4606 may be arranged alternately as shown in
In this structure, since the dot-shaped impurity regions 4606 on one column are located on lines connecting the gaps of the dot-shaped impurity regions 4606 on the adjacent columns, the effect of preventing the expansion of a depletion layer is enhanced. Although the carrier movement path is increased as indicated by a broken line 4607, it is not a serious problem in fine semiconductor devices as described above.
As described above, the punch-through phenomenon as one of the short channel effects can be prevented effectively by properly shaping the impurity regions. Since the impurity regions are formed artificially, their shape can be designed freely as a manufacturer desires.
In particular, the shapes of this embodiment shown in
Embodiment 19
This embodiment relates to structures of impurity regions that are different from those of Embodiment 4. This embodiment will be described with reference to
With the structure of
This type of structure can also be realized by forming fishbone-shaped impurity regions 4705 such that protrusions and recesses 4706 become longer as the position approaches a drain region 4707 as shown in
To provide a concentration profile shown in
A manufacturer need not stick to the impurity element concentration profile of
The structure of this embodiment are effective in a case where the source and drain regions are fixed. For example, this embodiment is not necessarily effective for a semiconductor device for driving a pixel of a liquid crystal display device in which case the source and the drain are reversed in accordance with a charging/discharging operation. Where the semiconductor device of this embodiment is applied to liquid crystal display device, it should be used in a circuit in which the source and the drain are fixed, such as an invertor circuit that constitutes a peripheral driver circuit.
Although this embodiment is directed to the impurity regions as variations of the linearly patterned impurity regions that are generally parallel with the channel direction, the concept of this embodiment can easily be applied to the dot-pattered impurity regions. As so exemplified, this embodiment is just an example and a manufacturer would employ other various conceivable structures when necessary.
Embodiment 20
The invention is characterized in that the impurity regions are provided in the channel forming region artificially and locally. An impurity element (one or a plurality of elements selected from carbon, nitrogen, and oxygen) locally added to the channel forming region is effective in the case of using a low oxygen concentration silicon substrate that has been subjected to hydrogen annealing.
As described in the background section, semiconductor devices (excluding a thyristor) for constituting ordinary LSI circuits are manufactured by using a silicon substrate that is formed by the CZ method and such a silicon substrate contains a given amount of oxygen for reduction of stress. However, in recent years, as increase in the breakdown voltage of oxide films and reduction of micro detects are required increasingly, substrates in which the oxygen concentration is reduced to less than 1×1017 atoms/cm3 in a surface layer of about 5 μm in thickness by annealing in a hydrogen atmosphere come to be used many cases.
On the other hand, in such silicon substrates that have been subjected to a low oxygen concentration treatment, there is a possibility that the surface layer becomes too weak to withstand stress and a crack and a warp tend to occur more easily in a manufacturing process of semiconductor devices.
In contrast, if a silicon substrate that has been subjected to a low oxygen concentration treatment is used in practicing the invention, stress concentrates at the impurity regions formed in the channel forming region. Thus, the impurity regions serve as buffer regions for buffering stress that occurs in a crystalline semiconductor.
The effect that the impurity regions serve as stress buffering regions is one of the invention's advantages worthy of mention. This effect is particularly remarkable when oxygen is used as an impurity element.
Thus, when semiconductor devices are manufactured by using a silicon substrate that has been subjected to a low oxygen concentration treatment, the influence of stress occurring in the manufacturing process can be reduced, as a result of which the manufacturing yield can be increased greatly.
In addition to increase in the breakdown voltage of an oxide film and reduction of microdefects, reduction in the influence of impurity scattering of carriers is expected in the above type of silicon substrate. That is, reducing the oxygen concentration means that the potential slit regions are made closer to intrinsic or substantially intrinsic regions, and therefore the carrier mobility can be made extremely high.
Embodiment 21
In this embodiment, examples of integrated circuits (covered by the term “semiconductor device” as used in this specification) that use semiconductor devices (or elements) according to the invention. This embodiment will be described with reference to
Referring to
Reference numeral 4807 denotes a gate electrode made of conductive polysilicon. Impurity regions 4808 which is the feature of the invention are formed right under the gate electrode 4807. In the example of
An n-channel FET is formed in the upper layer by using the SOI technology. A single crystal silicon layer as the active layer of the n-channel FET is obtained by using a known wafer bonding technique. Therefore, an interlayer insulating film 4809 is a lamination film of an interlayer insulating film that covers the lower layer FET and a thermal oxidation film of the wafer bonded, and hence includes a bonding surface (indicated by a broken line).
Then, a source region 4810, a channel forming region 4811, and a drain region 4812 are formed by a known TFT technique. Also in this case, low-concentration impurity regions 4813 and 4814 are formed such that a channel forming region 4811 are interposed in between. Impurity regions 4815 according to the invention are formed in the channel forming region 4811.
After an interlayer insulating film 4817 is formed so as to cover a gate electrode 4816, interconnections 4818-4820 are formed. The interconnection 4818 is common to the drain region 4804 of the p-channel FET and the drain region 4812 of the n-channel FET.
The stacked CMOS circuit having the above-described structure of
Since the use of the invention allows pursuit of high-speed operation without lowering the breakdown voltage, it becomes possible to provide a CMOS circuit superior in frequency characteristic.
Next,
Referring to
To form the bipolar transistor in the n-well 4824, a p-type region 4827 as an active base is formed first and then a p+ region 4828 as an external base and an n+ region 4829 as an emitter region are formed.
The CMOS circuit of a SOI structure which has, as the active layer, the single crystal silicon layer obtained by the wafer bonding technique is formed over the above-configured bipolar transistor. An interlayer insulating film 4830 includes the bonding surface (indicated by the broken line). Since the CMOS circuit is not described here in detail because the sufficient description therefor has already been described made in Embodiment 1.
In the configuration of
The upper-layer CMOS circuit and the lower-layer bipolar transistor are connected to each other by interconnections 4837 and 4838, to complete a Bi-CMOS structure.
The circuit configuration of the above Bi-CMOS circuit is intended to effectively utilize the high-speed operation of the bipolar transistor and the low power consumption of the CMOS circuit. By employing, as in this embodiment, a three-dimensional structure in which a CMOS circuit and a bipolar transistor are laminated, the occupation area can greatly be reduced, that is, a prior art problem of a large occupation area can be solved.
Referring to
With the above structure, a capacitor having a large capacitance is formed between the capacitive storage electrode 4903 and the capacitor electrode 4905. The laminate structure of
In this embodiment, an n-channel FET having an LDD region is used as a semiconductor device for data signal control provided in the upper layer. Although in this embodiment a single crystal silicon layer as the active layer is obtained by a wafer bonding technique, it may be obtained by a polysilicon (or amorphous silicon) recrystallization technique that uses laser light or an electron beam. A bonding junction interface is indicated by a broken line in
The active layer, i.e., the single crystal silicon layer, includes a source region 4906 and a drain region 4907. Impurity regions 4908 according to the invention are formed in a channel forming region. The impurity regions 4908 are formed so as to penetrate through an LDD region 4909 and go into the drain region 4907.
A data signal sent via a bit line 4910 is supplied to a drain electrode 4912 by controlling the voltage of a word line 4911. The signal is then stored in the lower-layer capacitor via a buried plug 4913 that connects the drain electrode 4912 in the upper layer and the capacitor electrode 4905 in the lower layer.
The DRAM is suitable for construction of a high integration density, large-scale memory because each memory unit is constituted of a very small number of elements, i.e., an IG-FET and a capacitor. With an additional advantage of a low manufacturing cost, the DRAM is a circuit that is currently used in a largest quantity.
The SRAM is a memory in which a bistable circuit such as a flip-flop is used as a storage element and which stores a binary information value (0 or 1) in accordance with the bistable state (on/off or off/on) of the bistable circuit. The SRAM is advantageous in being capable of holding information as long as it is supplied with a voltage.
The storage circuit is constituted of NMOS circuits or CMOS circuits.
Referring to
Reference numeral 4920 denotes impurity regions according to the invention. In this embodiment, the impurity regions 4920 are formed so as to go into the drain region 4916 but do not go into the source region 4915.
The active layer of the n-channel FET in the intermediate layer is formed by a laser (or electron) beam recrystallization method which is part of the SOI technology. More specifically, a polysilicon or amorphous silicon film is formed on a planarized interlayer insulating film 4921, melted by a laser beam, an electron beam, or the like, and then recrystallized.
Although another technique of the SOI technology, such as the wafer bonding technique, may naturally be used, in this embodiment the recrystallization method allows the drain region 4922 of the intermediate-layer n-channel FET to be directly connected to the drain region 4916 of the p-channel FET.
A source region 4923 and a drain region 4922 are formed in the above-obtained active layer (single crystal silicon layer) by a known TFT technique, and a gate electrode 4925 is formed above it through a gate insulating film 4924. Impurity regions 4926 according to the invention are formed right under the gate electrode 4925 so as to go into only the drain region 4922.
The gate electrode 4925 of the n-channel PET is formed by using polysilicon that is rendered conductive, and an interconnection 4927 is formed at the same time as the gate electrode 4925 by using the same material. The interconnection 4927 serves to supply an output signal of the right-hand CMOS circuit to gate electrodes 4928 and 4929 of the left-hand CMOS circuit. In
An n-channel FET serving as a transfer gate is provided in the uppermost layer. The active layer of this FET is a single crystal silicon layer obtained by the wafer bonding technique.
After a single crystal silicon layer is processed into an island shape, a source region 4930, a drain region 4931, and impurity regions 4932 according to the invention are formed therein to provide the active layer.
The drain region 4931 of the n-channel FET to serve as a transfer gate is electrically connected to the intermediate-layer interconnection 4927 via a connection electrode 4933. By applying a voltage to a word line 4934, a data signal is supplied from a bit line 4935 to the CMOS circuits.
Having advantages of a large operation margin and an extremely small data holding current, the CMOS-type SRAM configured in the above-described manner is widely used for a low-voltage battery backup purpose. The SRAM has further advantages such as high-speed operation, high reliability, and easiness in incorporation into a system.
As described above, by virtue of the invention the semiconductor devices of this embodiment such as the Bi-CMOS circuit and the SRAM circuit can be miniaturized while the short channel effects are avoided, and therefore they allow simultaneous pursuit of both high reliability (such as a high breakdown voltage) and high-speed operation. That is, it can be said that the invention is very effective in realizing ultra-high integration density circuits in view of the system-on-chip concept which will be put into practice in the future.
Embodiment 22
This embodiment is directed to a case where a semiconductor device according to the invention is incorporated into a product (electronic apparatus), specifically an IC circuit incorporated in a notebook-sized personal computer. This embodiment will be described with reference to
Referring to
The computing section 6014 and the memory sections 6015 are constructed by using a CMOS circuit, a Bi-CMOS circuit, a DRAM circuit, a SRAM circuit, and other various types of circuits. The configuration of this embodiment shown in
In the configuration in which the computing section 6014 and the memory sections 6015 are arranged adjacent to each other, exchange of data between the computing section 6014 and the memory sections 6015 can be performed at very high speed. Thus, a circuit that operates at high speed can be constructed.
Further, all the necessary circuits can be integrated on one chip in which case the manufacturing cost can be reduced very much. In addition, a product can be miniaturized by reducing the occupation area. Allowing formation of a three-dimensional integrated circuit as described in the seventh embodiment, the SOI technology will no doubt provide even higher integration densities in the future.
Further, since by utilizing the invention IG-FETs and even integrated circuits can be miniaturized without being affected by the short channel effects, it is expected that application electronic apparatuses as semiconductor devices can further be miniaturized and made more suitable for portable use by realizing the above-mentioned one-chip configuration.
Embodiment 23
This embodiment is directed to examples of electronic apparatuses incorporating IGFETs according to the invention and integrated circuits that are constructed by using such IGFETs.
As described above, although this specification uses the terms “IG-FET,” “integrated circuit” “electronic apparatus,” etc. for convenience of description, all of them are basically constructed by utilizing semiconductors and therefore should be covered by the term “semiconductor device.”
In general, semiconductor devices (electronic apparatuses) to which the invention is applicable include all semiconductor devices that require an IC circuit. Thus, the application range of the invention is extremely wide and include devices that are used in most of human activities.
Specific examples of semiconductor devices are active electro-optical devices such as a liquid crystal display device, an EL display device, and a CL display device, a TV camera, a personal computer, a car navigation apparatus, a TV projection apparatus, a video camera, and a portable information terminal apparatus (personal digital assistant). The portable information terminal apparatus includes such semiconductor devices as a cellular telephone and a mobile computer.
The cellular telephone of
As described above, the application range of the invention is very wide: the invention can be applied to various types of semiconductor devices (including electronic apparatuses) having a semiconductor integrated circuit.
Embodiment 24
A semiconductor device according to the invention exhibits much superior electrical characteristics, and an integrated circuit constructed by using such semiconductor devices is given a frequency characteristic covering a sufficiently high frequency range. In this embodiment, a description will be made of examples of performance of semiconductor devices according to the invention.
A semiconductor element itself formed according to the invention exhibits a much superior device characteristic (current-voltage characteristic of an IG-FET), and the threshold voltage Vth,n of an n-channel FET and the threshold voltage Vth,p of a p-channel FET can be controlled for a necessary drive voltage in ranges of −0.3 to 3.0 V and −3.0 to 0.3 V (typically 0 to ±0.3 V), respectively. A much superior subthreshold characteristic can also be obtained in which the S-value is 60-85 mV/decade, in some cases 60-70 mV/decade.
Further, for the reasons described in the first embodiment, a high mobility (larger than 1,000 cm2/Vs) can be obtained. In calculating a mobility value based on a calculation formula, care should be given to the fact that the mobility is in inverse proportion to the channel width W. In practicing the invention, an actual mobility value cannot be obtained unless a measured channel width Wpa is substituted into a formula because the channel width is narrowed by impurity regions by not a small amount.
A much superior frequency characteristic can be obtained by constructing an integrated circuit by using semiconductor devices according to the invention that can attain the abovementioned superior electrical characteristics. For example, by constructing a 9-stage ring oscillator by using semiconductor devices according to the invention, a frequency characteristic covering 2-10 GHz can be obtained with a drive voltage of 3.3 V.
The invention is also effective for electronic apparatuses that are required to have a frequency characteristic covering a high frequency range, such as a cellular telephone as a high frequency electronic apparatus. An integrated circuit used in an input section, for instance, of a cellular telephone is required to have a frequency characteristic including about 2 GHz (2.4 GHz) as in the case of an I/O circuit and a MUX/DMUX circuit. The invention can sufficiently be applied to such high-frequency integrated circuits.
Embodiment 25
This embodiment is directed to a configuration in which the same element as an impurity element for forming impurity regions for pinning is added to a base insulating layer (or an insulating substrate) of a single crystal silicon layer (active layer). This embodiment can be applied to both configurations of
This embodiment is directed to a case where an n-type semiconductor device is to be formed and the impurity regions are formed by adding boron. (In the case of a p-type semiconductor device, phosphorus (or arsenic) may be added.)
Referring to
This embodiment is characterized in that the insulating layer 3012 contains boron at least in the vicinity of its surface. This structure may be formed in various manners depending on the manufacturing process of a SOI structure. A brief description will be made of a case of a wafer bonding SOI structure.
In the case of a wafer bonding SOI structure, a silicon substrate (first substrate) on which a thermal oxidation film is formed and a silicon substrate (second substrate) for supporting it are prepared. A thermal oxidation process for forming a thermal oxidation film on the first substrate is executed in an atmosphere containing boron. As a result, boron is added to a resulting thermal oxidation film.
Then the first and second substrates are bonded together by a known method, and an etch-back operation (or grinding) is performed from the back side of the first substrate. Thus, a SOI structure is obtained.
Then, boron is locally added by ion implantation, for instance, so that impurity regions for pinning are formed. Thus, the structure shown in
The impurity regions 3014 for pinning and their vicinities correspond to a high energy wall region 3021 (energy barrier region). Reference numeral 3022 denotes an interface between the single crystal silicon layer 3013 and the insulating layer 3012. This embodiment is characterized in that a high energy barrier is intentionally formed in the vicinity of the interface 3022.
As described in the first embodiment, high energy barriers are formed in the impurity regions 3014 and encompass their vicinities because of impurity leakage. The same thing applies to the insulating layer 3012 which contains boron: naturally a high energy barrier is formed at and in the vicinity of the interface 3022 between the single crystal silicon layer 3013 and the insulating layer 3012.
Thus, the high-energy wall region 3021 (energy barrier) is formed as shown in
The energy profile diagrams of
The relative energy is lowest (level a in
In the invention, the relative energy a should be 3 or more times (preferably 10 or more times) larger than the relative energy b. In this case, carriers are allowed to go through the regions 3020 with preference given thereto.
Since a high energy barrier is formed in the vicinity of the interface 3022, no carriers go through the region in the vicinity of the interface 3022. Therefore, surface scattering of carriers which would otherwise occur in the vicinity of the surface of the base insulating layer 3012 can be prevented.
Although this embodiment is directed to the wafer bonding SOI structure, the advantages of this embodiment can be obtained as long as the structure of
Embodiment 26
The configuration of the eleventh embodiment can also be applied to a buried channel type semiconductor device. Further, although the eleventh embodiment is directed to the n-channel semiconductor device, the eleventh embodiment can easily be adapted for a p-type semiconductor device, and can be adapted even for a CMOS structure that is a complementary combination of n-type and p-type semiconductor devices.
In a certain situation, as for a substrate on which n-type semiconductor devices and p-type semiconductor devices are formed in a mixed manner, the configuration of the eleventh embodiment can be applied to only the n-type semiconductor devices.
As described above, since the invention is applied to semiconductor devices having a SOI structure, the invention enables formation of an integrated circuit that operates more than 10% faster and can be driven with more than 30% lower power consumption than a conventional integrated circuit formed on a bulk silicon substrate.
By utilizing the invention, the short channel effects can be prevented which would otherwise occur when the channel length is shortened. Specifically, a drain-side depletion layer is prevented from expanding to the source region and the region under the channel forming region by means of the impurity regions that are locally formed in the channel forming region, to provide a structure in which the drain voltage does not influence the energy (potential) state of the channel forming region. As a result, the punch-through phenomenon and deterioration of the subthreshold characteristic can be prevented, as well as a high drain breakdown voltage can be obtained.
Further, reduction in threshold voltage which is one aspect of the short channel effects can be compensated by increase in threshold voltage that is caused by the narrow channel effect. The narrow channel effect is artificially obtained by locally forming the impurity regions in the channel forming region according to the invention.
As described above, the invention allows even semiconductor devices in the deem submicron range that have extremely short channels to operate properly without causing any short channel effects. Thus, by using semiconductor devices according to the invention, integrated circuits can be constructed that are integrated at a very high density.
Further, according to the invention, it becomes possible to reduce scattering due to self-collision of carriers by defining carrier movement directions by forming slit-like lane regions in terms of energy.
That is, the factors of reducing the carrier mobility, such as the impurity scattering, the lattice scattering, and the scattering due to self-collision of carriers, are greatly reduced in degree, whereby the mobility is increased very much. Thus, the performance of semiconductor devices as typified by an IG-FET can further be improved.
| Number | Date | Country | Kind |
|---|---|---|---|
| 9-333453 | Nov 1997 | JP | national |
| 9-337710 | Nov 1997 | JP | national |
| 9-340754 | Nov 1997 | JP | national |
This application is a continuation application of U.S. application Ser. No. 12/427,140 filed Apr. 21, 2009; which is a continuation application of U.S. application Ser. No. 10/694,477, filed Oct. 27, 2003, now U.S. Pat. No. 7,535,053; which is a continuation application of application Ser. No. 09/192,745, filed Nov. 16, 1998, now U.S. Pat. No. 6,686,623, which claims the benefit of foreign priority applications filed in Japan as Serial No. 9-333453 on Nov. 18, 1997, Serial No. 9-337710 on Nov. 21, 1997 and Serial No. 9-340754 on Nov. 26, 1997, all of which are incorporated by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3890632 | Ham et al. | Jun 1975 | A |
| 3964941 | Wang | Jun 1976 | A |
| 4004159 | Rai et al. | Jan 1977 | A |
| 4217153 | Fukunaga et al. | Aug 1980 | A |
| 4454524 | Spence | Jun 1984 | A |
| 4495693 | Iwahashi et al. | Jan 1985 | A |
| 4549336 | Sheppard | Oct 1985 | A |
| 4583122 | Ohwada et al. | Apr 1986 | A |
| 4665419 | Sasaki | May 1987 | A |
| 4697198 | Komori et al. | Sep 1987 | A |
| 4733947 | Ota et al. | Mar 1988 | A |
| 4753896 | Matloubian | Jun 1988 | A |
| 4768076 | Aoki et al. | Aug 1988 | A |
| 4786955 | Plus et al. | Nov 1988 | A |
| 4822752 | Sugahara et al. | Apr 1989 | A |
| 4857986 | Kinugawa | Aug 1989 | A |
| 4899202 | Blake et al. | Feb 1990 | A |
| 4933298 | Hasegawa | Jun 1990 | A |
| 4943837 | Konishi et al. | Jul 1990 | A |
| 4959697 | Shier et al. | Sep 1990 | A |
| 4999682 | Xu et al. | Mar 1991 | A |
| 5002630 | Kermani et al. | Mar 1991 | A |
| 5059304 | Field | Oct 1991 | A |
| 5130770 | Blanc et al. | Jul 1992 | A |
| 5196367 | Lu et al. | Mar 1993 | A |
| 5198879 | Ohshima | Mar 1993 | A |
| 5210437 | Sawada et al. | May 1993 | A |
| 5215931 | Houston | Jun 1993 | A |
| 5243213 | Miyazawa et al. | Sep 1993 | A |
| 5258323 | Sarma et al. | Nov 1993 | A |
| 5261999 | Pinker et al. | Nov 1993 | A |
| 5262987 | Kojima | Nov 1993 | A |
| 5289030 | Yamazaki et al. | Feb 1994 | A |
| 5317236 | Zavracky et al. | May 1994 | A |
| 5324960 | Pfiester et al. | Jun 1994 | A |
| 5341028 | Yamaguchi et al. | Aug 1994 | A |
| 5343051 | Yamaguchi et al. | Aug 1994 | A |
| 5350940 | Rona | Sep 1994 | A |
| 5371037 | Yonehara | Dec 1994 | A |
| 5374564 | Bruel | Dec 1994 | A |
| 5387555 | Linn et al. | Feb 1995 | A |
| 5403759 | Havemann | Apr 1995 | A |
| 5405802 | Yamagata et al. | Apr 1995 | A |
| 5407837 | Eklund | Apr 1995 | A |
| 5424230 | Wakai | Jun 1995 | A |
| 5426062 | Hwang | Jun 1995 | A |
| 5426325 | Chang et al. | Jun 1995 | A |
| 5428234 | Sumi | Jun 1995 | A |
| 5444282 | Yamaguchi et al. | Aug 1995 | A |
| 5449937 | Arimura et al. | Sep 1995 | A |
| 5455791 | Zaleski et al. | Oct 1995 | A |
| 5488001 | Brotherton | Jan 1996 | A |
| 5506178 | Suzuki et al. | Apr 1996 | A |
| 5508209 | Zhang et al. | Apr 1996 | A |
| 5532175 | Racanelli et al. | Jul 1996 | A |
| 5548143 | Lee | Aug 1996 | A |
| 5550070 | Funai et al. | Aug 1996 | A |
| 5569620 | Linn et al. | Oct 1996 | A |
| 5573961 | Hsu et al. | Nov 1996 | A |
| 5574292 | Takahashi et al. | Nov 1996 | A |
| 5576556 | Takemura et al. | Nov 1996 | A |
| 5581092 | Takemura | Dec 1996 | A |
| 5606191 | Wang | Feb 1997 | A |
| 5608231 | Ugajin et al. | Mar 1997 | A |
| 5612230 | Yuzurihara et al. | Mar 1997 | A |
| 5614752 | Takenaka | Mar 1997 | A |
| 5619053 | Iwamatsu et al. | Apr 1997 | A |
| 5635749 | Hong | Jun 1997 | A |
| 5640033 | Matsuoka | Jun 1997 | A |
| 5643826 | Ohtani et al. | Jul 1997 | A |
| 5644147 | Yamazaki et al. | Jul 1997 | A |
| 5648277 | Zhang et al. | Jul 1997 | A |
| 5661059 | Liu et al. | Aug 1997 | A |
| 5670389 | Huang et al. | Sep 1997 | A |
| 5674788 | Wristers et al. | Oct 1997 | A |
| 5675164 | Brunner et al. | Oct 1997 | A |
| 5693959 | Inoue et al. | Dec 1997 | A |
| 5698869 | Yoshimi et al. | Dec 1997 | A |
| 5698884 | Dennen | Dec 1997 | A |
| 5710057 | Kenney | Jan 1998 | A |
| 5714395 | Bruel | Feb 1998 | A |
| 5719065 | Takemura et al. | Feb 1998 | A |
| 5719427 | Tong et al. | Feb 1998 | A |
| 5729045 | Buynoski | Mar 1998 | A |
| 5750000 | Yonehara et al. | May 1998 | A |
| 5767529 | Kobori et al. | Jun 1998 | A |
| 5778237 | Yamamoto et al. | Jul 1998 | A |
| 5784131 | Kim et al. | Jul 1998 | A |
| 5784132 | Hashimoto | Jul 1998 | A |
| 5786618 | Wen | Jul 1998 | A |
| 5793073 | Kaminishi et al. | Aug 1998 | A |
| 5801416 | Choi et al. | Sep 1998 | A |
| 5807771 | Vu et al. | Sep 1998 | A |
| 5814854 | Liu et al. | Sep 1998 | A |
| 5818076 | Zhang et al. | Oct 1998 | A |
| 5818083 | Ito | Oct 1998 | A |
| 5821138 | Yamazaki et al. | Oct 1998 | A |
| 5831294 | Ugajin | Nov 1998 | A |
| 5837569 | Makita et al. | Nov 1998 | A |
| 5840616 | Sakaguchi et al. | Nov 1998 | A |
| 5841173 | Yamashita | Nov 1998 | A |
| 5849627 | Linn et al. | Dec 1998 | A |
| 5854123 | Sato et al. | Dec 1998 | A |
| 5854505 | Suzuki et al. | Dec 1998 | A |
| 5854509 | Kunikiyo | Dec 1998 | A |
| 5856229 | Sakaguchi et al. | Jan 1999 | A |
| 5869387 | Sato et al. | Feb 1999 | A |
| 5877070 | Goesele et al. | Mar 1999 | A |
| 5882987 | Srikrishnan | Mar 1999 | A |
| 5885872 | Tamaki et al. | Mar 1999 | A |
| 5886385 | Arisumi et al. | Mar 1999 | A |
| 5893730 | Yamazaki et al. | Apr 1999 | A |
| 5893740 | Chang et al. | Apr 1999 | A |
| 5894137 | Yamazaki et al. | Apr 1999 | A |
| 5894151 | Yamazaki et al. | Apr 1999 | A |
| 5899711 | Smith | May 1999 | A |
| 5904528 | Lin et al. | May 1999 | A |
| 5905291 | Utsunomiya et al. | May 1999 | A |
| 5913111 | Kataoka et al. | Jun 1999 | A |
| 5923962 | Ohtani et al. | Jul 1999 | A |
| 5926430 | Noda et al. | Jul 1999 | A |
| 5929479 | Oyama | Jul 1999 | A |
| 5936887 | Choi et al. | Aug 1999 | A |
| 5940722 | Tamura | Aug 1999 | A |
| 5943105 | Fujikawa et al. | Aug 1999 | A |
| 5949107 | Zhang | Sep 1999 | A |
| 5952699 | Yamazaki et al. | Sep 1999 | A |
| 5953622 | Lee et al. | Sep 1999 | A |
| 5962897 | Takemura et al. | Oct 1999 | A |
| 5965918 | Ono | Oct 1999 | A |
| 5966594 | Adachi et al. | Oct 1999 | A |
| 5966620 | Sakaguchi et al. | Oct 1999 | A |
| 5982002 | Takasu et al. | Nov 1999 | A |
| 5985681 | Hamajima et al. | Nov 1999 | A |
| 5985740 | Yamazaki et al. | Nov 1999 | A |
| 5989981 | Nakashima et al. | Nov 1999 | A |
| 6020252 | Aspar et al. | Feb 2000 | A |
| 6027988 | Cheung et al. | Feb 2000 | A |
| 6031249 | Yamazaki et al. | Feb 2000 | A |
| 6034896 | Ranaweera et al. | Mar 2000 | A |
| 6044474 | Klein | Mar 2000 | A |
| 6049092 | Konuma et al. | Apr 2000 | A |
| 6051453 | Takemura | Apr 2000 | A |
| 6054363 | Sakaguchi et al. | Apr 2000 | A |
| 6063706 | Wu | May 2000 | A |
| 6072199 | Iwamuro | Jun 2000 | A |
| 6077731 | Yamazaki et al. | Jun 2000 | A |
| 6087679 | Yamazaki et al. | Jul 2000 | A |
| 6093937 | Yamazaki et al. | Jul 2000 | A |
| 6096582 | Inoue et al. | Aug 2000 | A |
| 6107639 | Yamazaki et al. | Aug 2000 | A |
| 6107654 | Yamazaki | Aug 2000 | A |
| 6111296 | Yamazaki et al. | Aug 2000 | A |
| 6118148 | Yamazaki | Sep 2000 | A |
| 6121117 | Sato et al. | Sep 2000 | A |
| 6124613 | Kokubun | Sep 2000 | A |
| 6127702 | Yamazaki et al. | Oct 2000 | A |
| 6133073 | Yamazaki et al. | Oct 2000 | A |
| 6140667 | Yamazaki et al. | Oct 2000 | A |
| 6157421 | Ishii | Dec 2000 | A |
| 6165880 | Yaung et al. | Dec 2000 | A |
| 6171982 | Sato | Jan 2001 | B1 |
| 6184556 | Yamazaki et al. | Feb 2001 | B1 |
| 6191007 | Matsui et al. | Feb 2001 | B1 |
| 6191476 | Takahashi et al. | Feb 2001 | B1 |
| 6198141 | Yamazaki et al. | Mar 2001 | B1 |
| 6207969 | Yamazaki | Mar 2001 | B1 |
| 6211041 | Ogura | Apr 2001 | B1 |
| 6218678 | Zhang et al. | Apr 2001 | B1 |
| 6232642 | Yamazaki | May 2001 | B1 |
| 6246068 | Sato et al. | Jun 2001 | B1 |
| 6262438 | Yamazaki et al. | Jul 2001 | B1 |
| 6268842 | Yamazaki et al. | Jul 2001 | B1 |
| 6271101 | Fukunaga | Aug 2001 | B1 |
| 6287900 | Yamazaki et al. | Sep 2001 | B1 |
| 6291275 | Yamazaki et al. | Sep 2001 | B1 |
| 6294478 | Sakaguchi et al. | Sep 2001 | B1 |
| 6306709 | Miyagi et al. | Oct 2001 | B1 |
| 6307214 | Ohtani et al. | Oct 2001 | B1 |
| 6307220 | Yamazaki | Oct 2001 | B1 |
| 6326249 | Yamazaki et al. | Dec 2001 | B1 |
| 6329269 | Hamada et al. | Dec 2001 | B1 |
| 6331208 | Nishida et al. | Dec 2001 | B1 |
| 6335231 | Yamazaki et al. | Jan 2002 | B1 |
| 6335716 | Yamazaki et al. | Jan 2002 | B1 |
| 6342433 | Ohmi et al. | Jan 2002 | B1 |
| 6350702 | Sakaguchi et al. | Feb 2002 | B2 |
| 6365933 | Yamazaki et al. | Apr 2002 | B1 |
| 6369410 | Yamazaki et al. | Apr 2002 | B1 |
| 6380046 | Yamazaki | Apr 2002 | B1 |
| 6380560 | Yamazaki et al. | Apr 2002 | B1 |
| 6388291 | Zhang et al. | May 2002 | B1 |
| 6388652 | Yamazaki et al. | May 2002 | B1 |
| 6396105 | Yamazaki et al. | May 2002 | B1 |
| 6420759 | Yamazaki et al. | Jul 2002 | B2 |
| 6421754 | Kau et al. | Jul 2002 | B1 |
| 6424011 | Assaderaghi et al. | Jul 2002 | B1 |
| 6433361 | Zhang et al. | Aug 2002 | B1 |
| 6452211 | Ohtani et al. | Sep 2002 | B1 |
| 6455401 | Zhang et al. | Sep 2002 | B1 |
| 6458637 | Yamazaki et al. | Oct 2002 | B1 |
| 6465287 | Yamazaki et al. | Oct 2002 | B1 |
| 6498376 | Miyagi et al. | Dec 2002 | B1 |
| 6528820 | Yamazaki et al. | Mar 2003 | B1 |
| 6534380 | Yamauchi et al. | Mar 2003 | B1 |
| 6549184 | Koyama et al. | Apr 2003 | B1 |
| 6583474 | Yamazaki et al. | Jun 2003 | B2 |
| 6590230 | Yamazaki et al. | Jul 2003 | B1 |
| 6602761 | Fukunaga | Aug 2003 | B2 |
| 6617612 | Zhang et al. | Sep 2003 | B2 |
| 6653687 | Yamazaki | Nov 2003 | B1 |
| 6667494 | Yamazaki et al. | Dec 2003 | B1 |
| 6686623 | Yamazaki | Feb 2004 | B2 |
| 6730932 | Yamazaki et al. | May 2004 | B2 |
| 6744069 | Yamazaki et al. | Jun 2004 | B1 |
| 6787806 | Yamazaki et al. | Sep 2004 | B1 |
| 6803264 | Yamazaki et al. | Oct 2004 | B2 |
| 6808965 | Miyasaka et al. | Oct 2004 | B1 |
| 6849872 | Yamazaki et al. | Feb 2005 | B1 |
| 6867431 | Konuma et al. | Mar 2005 | B2 |
| 6875628 | Zhang et al. | Apr 2005 | B1 |
| 6875633 | Fukunaga | Apr 2005 | B2 |
| 6882018 | Ohtani et al. | Apr 2005 | B2 |
| 7023052 | Yamazaki et al. | Apr 2006 | B2 |
| 7126102 | Inoue et al. | Oct 2006 | B2 |
| 7138658 | Yamazaki et al. | Nov 2006 | B2 |
| 7148119 | Sakaguchi et al. | Dec 2006 | B1 |
| RE39484 | Bruel | Feb 2007 | E |
| 7172929 | Yamazaki et al. | Feb 2007 | B2 |
| 7176525 | Fukunaga | Feb 2007 | B2 |
| 7199024 | Yamazaki | Apr 2007 | B2 |
| 7223666 | Ohtani et al. | May 2007 | B2 |
| 7381599 | Konuma et al. | Jun 2008 | B2 |
| 7473592 | Yamazaki et al. | Jan 2009 | B2 |
| 7473971 | Yamazaki et al. | Jan 2009 | B2 |
| 7476576 | Yamazaki et al. | Jan 2009 | B2 |
| 7525158 | Konuma et al. | Apr 2009 | B2 |
| 7535053 | Yamazaki | May 2009 | B2 |
| 7569856 | Konuma et al. | Aug 2009 | B2 |
| 7638805 | Yamazaki et al. | Dec 2009 | B2 |
| 7642598 | Yamazaki et al. | Jan 2010 | B2 |
| 8222696 | Yamazaki et al. | Jul 2012 | B2 |
| 20010019153 | Sato et al. | Sep 2001 | A1 |
| 20010053607 | Sakaguchi et al. | Dec 2001 | A1 |
| 20020102820 | Hamada et al. | Aug 2002 | A1 |
| 20020109144 | Yamazaki | Aug 2002 | A1 |
| 20030087503 | Sakaguchi et al. | May 2003 | A1 |
| 20040104435 | Ohtani et al. | Jun 2004 | A1 |
| 20040164300 | Yamazaki et al. | Aug 2004 | A1 |
| 20040256621 | Konuma et al. | Dec 2004 | A1 |
| 20050009252 | Yamazaki et al. | Jan 2005 | A1 |
| 20050142705 | Konuma et al. | Jun 2005 | A1 |
| 20050153489 | Konuma et al. | Jul 2005 | A1 |
| 20070007529 | Takemura et al. | Jan 2007 | A1 |
| 20070020888 | Yamazaki et al. | Jan 2007 | A1 |
| 20070108510 | Fukunaga | May 2007 | A1 |
| 20070173000 | Yamazaki | Jul 2007 | A1 |
| 20070184632 | Yamazaki et al. | Aug 2007 | A1 |
| 20070210451 | Ohtani et al. | Sep 2007 | A1 |
| 20070252206 | Yamazaki et al. | Nov 2007 | A1 |
| 20080054269 | Yamazaki et al. | Mar 2008 | A1 |
| 20080061301 | Yamazaki | Mar 2008 | A1 |
| 20080067529 | Yamazaki | Mar 2008 | A1 |
| 20080067596 | Yamazaki et al. | Mar 2008 | A1 |
| 20080067597 | Yamazaki | Mar 2008 | A1 |
| 20080070335 | Yamazaki et al. | Mar 2008 | A1 |
| 20080083953 | Yamazaki | Apr 2008 | A1 |
| 20080113487 | Yamazaki et al. | May 2008 | A1 |
| 20080113488 | Yamazaki et al. | May 2008 | A1 |
| 20080213953 | Yamazaki | Sep 2008 | A1 |
| 20080286941 | Yamazaki | Nov 2008 | A1 |
| 20080286942 | Yamazaki | Nov 2008 | A1 |
| 20080286956 | Yamazaki | Nov 2008 | A1 |
| 20090236698 | Yamazaki et al. | Sep 2009 | A1 |
| 20090289254 | Konuma et al. | Nov 2009 | A1 |
| Number | Date | Country |
|---|---|---|
| 0 369 676 | May 1990 | EP |
| 0 485 233 | May 1992 | EP |
| 0 553 852 | Aug 1993 | EP |
| 0 645 802 | Mar 1995 | EP |
| 0 723 286 | Jul 1996 | EP |
| 0 767 486 | Apr 1997 | EP |
| 0 793 263 | Sep 1997 | EP |
| 61-256674 | Nov 1986 | JP |
| 62-011277 | Jan 1987 | JP |
| 62-071277 | Apr 1987 | JP |
| 63-300567 | Jul 1988 | JP |
| 63-318779 | Dec 1988 | JP |
| 02-042725 | Feb 1990 | JP |
| 02-260442 | Oct 1990 | JP |
| 03-054869 | Mar 1991 | JP |
| 03-079035 | Apr 1991 | JP |
| 04-079270 | Mar 1992 | JP |
| 04-096278 | Mar 1992 | JP |
| 04-206766 | Jul 1992 | JP |
| 04-242958 | Aug 1992 | JP |
| 04-348532 | Dec 1992 | JP |
| 05-082787 | Apr 1993 | JP |
| 05-136429 | Jun 1993 | JP |
| 05-166689 | Jul 1993 | JP |
| 05-218410 | Aug 1993 | JP |
| 05-226620 | Sep 1993 | JP |
| 05-315355 | Nov 1993 | JP |
| 05-341317 | Dec 1993 | JP |
| 06-060678 | Mar 1994 | JP |
| 07-056189 | Mar 1995 | JP |
| 07-086532 | Mar 1995 | JP |
| 07-130652 | May 1995 | JP |
| 07-249749 | Sep 1995 | JP |
| 08-064788 | Mar 1996 | JP |
| 08-078329 | Mar 1996 | JP |
| 08-274330 | Oct 1996 | JP |
| 08-293598 | Nov 1996 | JP |
| 08-330598 | Dec 1996 | JP |
| 09-008124 | Jan 1997 | JP |
| 09-045882 | Feb 1997 | JP |
| 09-055633 | Feb 1997 | JP |
| 09-107086 | Apr 1997 | JP |
| 09-165216 | Jun 1997 | JP |
| 09-212428 | Aug 1997 | JP |
| 09-213916 | Aug 1997 | JP |
| 09-260682 | Oct 1997 | JP |
| 09-289323 | Nov 1997 | JP |
| 09-293876 | Nov 1997 | JP |
| 10-065163 | Mar 1998 | JP |
| 10-065164 | Mar 1998 | JP |
| 10-093100 | Apr 1998 | JP |
| 10-125879 | May 1998 | JP |
| 10-125881 | May 1998 | JP |
| 11-017169 | Jan 1999 | JP |
| 11-163363 | Jun 1999 | JP |
| WO 8803328 | May 1988 | WO |
| WO 9702605 | Jan 1997 | WO |
| Entry |
|---|
| Koyanagi et al., “Submicron Devices I,” Maruzen Co., Ltd., pp. 88-138, 1987. |
| Ohuchi et al., “A High-Performance 0.05 m SOI MOS FET: Possibility of Velocity Overshoot,” Japanese Journal of Applied Physics, vol. 35, Part 1, No. 2B, Feb. 1996, pp. 960-964. |
| Izumi, K., et al., “C.M.O.S. Devices Fabricated on Buried SiO2 Layers Formed by Oxygen Implantation Into Silicon,” Electronic Letters, Aug. 31, 1978, vol. 14, No. 18, pp. 593-594. |
| Wolf, S., “Silicon Processing for the VLSI Era,” Jan. 1, 1990, vol. 2, Process Integration, pp. 238-239. |
| Bruel, M., Silicon on Insulator Material Technology, Electronics Letter, Jul. 6, 1995, vol. 31, No. 14, pp. 1201-1202. |
| Sakaguchi, K., et al., “Current Progress in Epitaxial Layer Transfer (ELTRAN®),” IECE Trans. Electron, Mar. 1, 1997, vol. E80C, No. 3, pp. 378-387. |
| Auberton-Herve, A.J., et al., “Smart-Cut®: The Basic Fabrication Process for UNIBOND® SOI Wafers,” IEICE Trans. Electron, Mar. 3, 1997, vol. E80C, No. 3, pp. 358-363. |
| Auberton-Herve, A.J., et al., “Unibond SOI Wafer by Smart Cut,” Electronic Material, Aug. 1, 1997, vol. 36, No. 8, pp. 83-87. |
| Ishiyama, T., et al., “Application of Reversed Silicon Wafer Direct Bonding to Thin-Film SOI Power Ics,” Extended Abstracts of the 1997 International Conference on Solid State Devices and Materials, Sep. 16, 1997, pp. 162-163. |
| Chau, R., et al., “Scalability of Partially Depleted SOI Technology for Sub- 0.25 μm Logic Applications,” IEDM 97: Technical Digest of International Electron Devices Meeting, Dec. 7, 1997, pp. 591-594. |
| Assaderaghi, F., et al., “A 7.9/5.5 psec Room/Low Temperature SOI CMOS,” IEDM Technical Digest of International Electron Devices Meeting, Dec. 7, 1997, pp. 415-418. |
| Bell, T. et al., “A Dissolved Wafer Process Using a Porous Silicon Sacrificial Layer and a Lightly-Doped Bulk Silicon Etch-Stop,” Micro Electro Mechanical Systems, Jan. 25, 1998, pp. 251-256. |
| Nandakumar, M., et al., Shallow Trench Isolation for Advanced ULSI CMOS Technologies, IEDM 98: Technical Digest of International Electron Devices Meeting, Dec. 6, 1998, pp. 133-136. |
| Office Action (U.S. Appl. No. 12/469,978) dated Nov. 8, 2011. |
| Pending Claims (U.S. Appl. No. 12/469,978) as of May 21, 2009. |
| Okazawa et al., “Nikkei Microdevices,” pp. 47-48, May 1992. |
| Number | Date | Country | |
|---|---|---|---|
| 20130037884 A1 | Feb 2013 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12427140 | Apr 2009 | US |
| Child | 13549914 | US | |
| Parent | 10694477 | Oct 2003 | US |
| Child | 12427140 | US | |
| Parent | 09192745 | Nov 1998 | US |
| Child | 10694477 | US |
