Claims
- 1. A method of programming a nonvolatile memory cell, the nonvolatile memory cell having a control gate, a floating gate, a program/select gate, a drain, a source, and a channel region between the drain and the source, the method comprising the steps of:
applying a first voltage to the control gate, applying a second voltage to the program/select gate, applying a third voltage to the drain, and applying a fourth voltage to the source, for varying an amount of charges in the floating gate so that the channel region is turned-off at an initial stage of programming a threshold voltage level and thereafter, turned-on as the amount of charges in the floating gate changes; and monitoring a conductivity of the channel region during the programming for forcing application of at least one of the first and second voltages to the control gate and the program/select gate respectively to stop when the monitored conductivity is measured to be a predetermined reference value.
- 2. The method of claim 1, wherein the reference value is a threshold voltage value of the nonvolatile memory cell.
- 3. The method of claim 1, wherein the first voltage is a negative value, the second voltage is a positive value, the third voltage is a positive value, and the fourth voltage is a positive value lower than the third voltage.
- 4. The method of claim 1, wherein the fourth voltage is a ground voltage.
- 5. The method of claim 1, wherein the step of monitoring a conductivity of the channel region includes a step of monitoring a current flowing through the drain.
- 6. The method of claim 1, wherein the step of monitoring a conductivity of the channel region includes a step of monitoring a variation of a charge carrier amount in the floating gate.
- 7. A method of programming a nonvolatile memory cell, the nonvolatile memory cell having a control gate, a floating gate, a program/select gate, a drain, a source, and a channel region between the drain and the source, the method comprising the steps of:
applying a first voltage to the control gate, and applying a second voltage to the program/select gate in a multi-level programming, for varying an amount of charges in the floating gate so that the channel region is turned-off at an initial stage of each threshold voltage level programming and thereafter is turned-on, the first voltage varying according to each threshold voltage level programming; and monitoring a conductivity of the channel region during each threshold voltage level programming for forcing application of at least one of the first and second voltages to the control gate and the program/select gate respectively to stop when the monitored conductivity is measured to be a predetermined reference value.
- 8. The method of claim 7, wherein the reference value is a fixed value regardless of each threshold voltage level programming.
- 9. The method of claim 8, wherein the reference value is a threshold voltage value of the nonvolatile memory cell.
- 10. The method of claim 7, wherein the first voltage is a negative value varying with every threshold voltage level programming, and the second voltage is an always fixed positive value.
- 11. The method of claim 7, wherein the step of monitoring a conductivity of the channel region includes a step of detecting a current flowing through the drain.
- 12. The method of claim 7, wherein the step of monitoring a conductivity of the channel region includes a step of monitoring a variation of a charge carrier amount in the floating gate.
- 13. A nonvolatile memory cell comprising:
a semiconductor substrate including a source, a drain and a channel region between the source and the drain in a surface thereof; a program/select gate formed on a source side on a surface of the channel region; a floating gate formed on a drain side on a surface of the channel region, the floating gate including a side formed adjacent to one side of the program/select gate for tunneling of electrons; a control gate formed over the floating gate; and, a dielectric layer formed between the program/select gate, the floating gate and the control gate with a thickness of the dielectric layer between the one side of the floating gate and the one side of the program/select gate formed thin enough to allow tunneling.
- 14. The method of claim 13, further comprising a gate insulating layer formed thin enough to allow tunneling of electrons among the channel region, the floating gate and the program/select gate.
- 15. A nonvolatile memory cell comprising:
a semiconductor substrate including a source, a drain and a channel region between the source and the drain in a surface thereof; a floating gate formed on a surface of the channel region on a drain side; a program/select gate formed extended from a part on a surface of the channel region on a source side to a part over a surface of the floating gate, the program/select gate having an edge opposite to an edge of the floating gate; a control gate formed over the floating gate; and a dielectric layer formed between the program/select gate, the floating gate and the control gate with a thickness of the dielectric layer between the edge of the floating gate and the edge of the program/select gate formed thin enough to allow tunneling.
- 16. The nonvolatile memory cell of claim 15, further comprising a gate insulating layer formed thin enough to allow tunneling of electrons among the channel region, the floating gate and the program/select gate.
- 17. A nonvolatile memory cell comprising:
a semiconductor substrate including a source, a drain and a channel region between the source and the drain in a surface thereof; a floating gate formed on a surface of the channel region on a drain side; a control gate formed over the floating gate; a program/select gate formed extended from a part on a surface of the channel region on a source side to a part on a surface of the drain on a drain side to have one side of the program/select gate to be adjacent to one side of the floating gate for tunneling of electrons; and a dielectric layer formed between the program/select gate, the floating gate and the control gate with a thickness of the dielectric layer between the one side of the floating gate and the one side of the program/select gate formed thin enough to allow tunneling.
- 18. The nonvolatile memory cell of claim 17, further comprising a gate insulating layer formed thin enough to allow tunneling of electrons among the channel region, the floating gate and the program/select gate.
- 19. A nonvolatile memory cell comprising:
a semiconductor substrate including a source, a drain and a channel region between the source and the drain in a surface thereof; a floating gate formed on a surface of the channel region on a drain side; a control gate formed over the floating gate; a program/select gate formed extended from a part on a surface of the channel region on a source side to a part on the drain to cover all exposed surfaces of the floating gate and the control gate, the program/select gate having an edge opposite to an edge of the floating gate on a drain side; and a dielectric layer formed between the program/select gate, the floating gate and the control gate with a thickness of the dielectric layer between the edge of the floating gate and the edge of the program/select gate formed thin enough to allow tunneling.
- 20. The nonvolatile memory cell of claim 19, further comprising a gate insulating layer formed thin enough to allow tunneling of electrons among the channel region, the floating gate and the program/select gate.
- 21. A method of at least one of programming and verifying a memory cell to a threshold voltage level, the memory cell having a transistor with a control gate, a first gate, a second gate and first and second electrode regions and a channel region between the first and second electrode regions, comprising the steps of:
accumulating charge carriers in the first gate to a first charge amount level; transferring the charge carriers through a first current path formed between the first gate and the second gate; and monitoring one of (a) a current flow through a second current path between the first and second electrodes and (b) a potential at one of said first and second electrodes, wherein charge carriers are transferred through the first current path until one of (a) the current flow through the second current path equals a reference current and (b) the potential at one of said first and second electrodes equals a reference voltage, respectively, such that the threshold voltage level is programmed.
- 22. The method of claim 21, wherein the charge carriers are electrons.
- 23. The method of claim 21, wherein the charge carriers are accumulated in the first gate induces a highest threshold voltage on the control gate.
- 24. The method of claim 21, wherein the charge carriers are accumulated by at least one of hot carrier injection and tunneling of charge carriers between one of the first and second electrodes and the first gate.
- 25. The method of claim 21, wherein the charge carriers are transferred by at least one of hot carrier injection and tunneling of charge carriers from the first gate to the second gate.
- 26. The method of claim 21, wherein
the step of transferring the charge carriers comprises the steps of applying a control gate voltage and first voltage to the control gate and second gate, respectively.
- 27. The method of claim 26, wherein the monitoring step comprises
applying second and third voltages to the first and second electrodes, respectively; and discontinuing the application of at least one of the control gate voltage, first voltage, second voltage and third voltage when at least one of the current and the potential equals the reference current and the reference voltage, respectively.
- 28. The method of claim 26, wherein the control gate voltage varies in accordance with a threshold voltage to be programmed in the nonvolatile memory cell.
- 29. The method of claim 28, wherein the control gate voltage applied and the threshold voltage to be programmed vary linearly.
- 30. The method of claim 21, wherein the reference current is constant for every threshold voltage to be programmed in the memory cell.
- 31. The method of claim 21, wherein the reference voltage is constant for every threshold voltage to be programmed in the memory cell.
- 32. The method of claim 26, wherein the control voltage is a constant voltage during at least one of programming and verifying.
- 33. The method of claim 21, wherein a time period for one of the current and potential to equal one of the reference current and reference voltage, respectively, is the same for every threshold voltage level to be programmed in the memory cell.
- 34. The method of claim 21, wherein one of the reference voltage and the reference current is at least equal to one of a threshold voltage and a threshold current of the transistor.
Priority Claims (1)
Number |
Date |
Country |
Kind |
29695/1996 |
Jul 1996 |
KR |
|
Parent Case Info
[0001] This application is a Divisional of application No. 08/898,689 filed Jul. 22, 1997.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09416271 |
Oct 1999 |
US |
Child |
09776928 |
Feb 2001 |
US |
Parent |
08898689 |
Jul 1997 |
US |
Child |
09416271 |
Oct 1999 |
US |