Claims
- 1. A nonvolatile memory cell comprising:
a floating gate; a gate oxide, beneath the floating gate, wherein the gate oxide is on a substrate; a source region in the substrate; a drain region in the substrate; and a low doping region, beneath the floating gate and between the source and drain regions, wherein the low doping region has a lower net carrier concentration than in the substrate, both the substrate and the low doping region have the same type of majority carriers, and the low doping region suppresses hot carrier injection into the floating gate.
- 2. The method of claim 1 wherein the doping concentration of the substrate is from about 2×1016 cm−3 to about 1×1017 cm−3.
- 3. The method of claim 1 wherein a junction depth of the source region is from about 0.1 microns to about 0.3 microns.
- 4. The method of claim 1 wherein a depth of the low doping region is about 0.5 microns.
- 5. The method of claim 1 wherein a thickness of the gate oxide is about 125 Angstroms.
- 6. The method of claim 1 wherein the low doping region is a p-type region.
- 7. A programmable logic integrated circuit comprising the nonvolatile memory cell as recited in claim 1.
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a divisional application of U.S. patent application Ser. No. 09/349,533 filed Jul. 8, 1999, which is a divisional application of U.S. patent application Ser. No. 08/741,082 filed Oct. 30, 1996, now U.S. Pat. No. 5,949,710, which claims the benefit of U.S. Provisional Patent Application No. 60/015,120, filed Apr. 10, 1996, and U.S. Provisional Patent Application No. 60/016,881, filed May 6, 1996, all of which are incorporated by reference herein.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60015120 |
Apr 1996 |
US |
|
60016881 |
May 1996 |
US |
Divisions (2)
|
Number |
Date |
Country |
Parent |
09349533 |
Jul 1999 |
US |
Child |
10436644 |
May 2003 |
US |
Parent |
08741082 |
Oct 1996 |
US |
Child |
09349533 |
Jul 1999 |
US |