BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
FIG. 1 illustrates a cross-sectional view of a memory device according to an embodiment of the present invention;
FIG. 2 illustrates a cross-sectional view of a memory device according to a second embodiment of the present invention;
FIGS. 3 through 8 illustrate cross-sectional views of stages in a method of forming the memory device illustrated in FIG. 1;
FIGS. 9 through 14 illustrate cross-sectional views of stages in a method of forming the memory device illustrated in FIG. 2; and
FIGS. 15A and 15B illustrate graphs of a change in work function of TiN according to the content of nitrogen (N) and heat treatment.
DETAILED DESCRIPTION OF THE INVENTION
Korean Patent Application No. 2006-102374, filed on Oct. 20, 2006, in the Korean Intellectual Property Office, and entitled: “Nonvolatile Memory Device and Method for Forming the Same,” is incorporated by reference herein in its entirety.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements are not to be limited by these terms. Rather, these terms are only used to distinguish one element from another element. In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
Structure of a Memory Device
FIG. 1 illustrates a cross-sectional view of a memory device according to an embodiment of the present invention. The memory device may be, e.g., a non-volatile memory device. Referring to FIG. 1, a semiconductor substrate 10 may include a peripheral region and a cell region. The peripheral region may include, e.g., peripheral circuit transistors such as a high-voltage transistor and a low-voltage transistor. The cell region may include, e.g., memory cell transistors. A device isolation layer (not shown) may define active regions in the peripheral region and the cell region.
In the peripheral region, a first insulating pattern 21a may be on the substrate 10, and a peripheral gate pattern 30 may be on the first insulating pattern 21a. The peripheral gate pattern 30 may include, e.g., a polysilicon pattern 24a, a first barrier metal pattern 41a, and a first conductive pattern 44a. Impurity regions 61 may be formed in the substrate 10 at opposite sides of the peripheral gate pattern 30. The peripheral gate pattern 30 and the impurity regions 61 may form a peripheral circuit transistor, and the first insulating pattern 21a may be used as a gate insulating layer of the peripheral circuit transistor.
In the cell region, a cell gate insulating pattern 40 may be on the substrate 10, and a cell gate pattern 50 may be on the cell gate insulating pattern 40. The cell gate insulating pattern 40 may include, e.g., a second insulating pattern 31a, a charge storage pattern 34a, and a third insulating pattern 37a. The second insulating pattern 31a may be a tunneling insulating layer, and may include, e.g., silicon oxide. The charge storage pattern 34a may be a material layer for charge storage, and may include, e.g., one or more of silicon nitride and silicon oxide nitride. The charge storage pattern 34a may have an energy band structure that can trap and confine electrons or holes. The third insulating pattern 37a may be a blocking insulating layer having an energy band structure that can confine the trapped charges in the charge storage pattern 34a, and may include metal oxide, e.g., aluminum oxide. Also, the third insulating pattern 37a may include a material that can increase a coupling ratio so as to improve the performance of the memory device. The third insulating pattern 37a may be resistant to etching damage.
The cell gate pattern 50 may include a second barrier metal pattern 41b and a second conductive pattern 44b. Impurity regions 64 may be formed in the substrate 10 at opposite sides of the cell gate pattern 50. The cell gate insulating pattern 40, the cell gate pattern 50, and the impurity regions 64 may form a memory cell transistor. The cell gate insulating pattern 40 may be formed to correspond to the cell gate pattern 50, to correspond to an active region within the cell region, and/or to correspond to the cell region.
The first barrier metal pattern 41a in the peripheral region and the second barrier metal pattern 41b in the cell region may be formed of a same material, and the first conductive pattern 44a in the peripheral region and the second conductive pattern 44b in the cell region may be formed of a same material. The first and second barrier metal patterns 41a and 41b may include, e.g., a material having a work function of about 4.5 eV to about 5.0 eV, such as a metal nitride. The metal nitride may include, e.g., one or more of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), hafnium nitride (HfN), and zirconium nitride (ZrN). The first and second conductive patterns 44a and 44b may include a metal material, e.g., tungsten.
The first and second barrier metal patterns 41a and 41b may prevent a material in the first and second conductive patterns 44a and 44b, which are formed respectively thereon, from being diffused downwards. Also, the second barrier metal pattern 41b in the cell region may serve as a gate electrode because of its high work function. Thus, the first and second barrier metal patterns 41a and 41b of the same material may perform different functions according to their locations.
FIGS. 15A and 15B illustrate graphs of a change in work function of TiN according to the content of nitrogen (N) and heat treatment. In particular, FIG. 15A illustrates a graph showing a change in work function of TiN according to a content of nitrogen (N), and FIG. 15B illustrates a graph showing a change in work function of TiN according to heat treatment. In FIGS. 15A and 15B, the horizontal axis represents nitrogen gas flow injected in a process chamber when TiN is deposited on a semiconductor substrate, and the vertical axis represents the work function of TiN.
Referring to FIG. 15A, it is apparent that, as the flow of nitrogen gas increases, the work function of TiN also increases. For example, TiN deposited with a nitrogen gas flow of about 15 sccm has a work function of about 4.5 eV, and TiN deposited with a nitrogen gas flow of about 17 sccm has a work function of about 4.9 eV.
Referring to FIG. 15B, it is apparent that the work function increases when rapid heat treatment is performed at about 600° C. after TiN is deposited. For example, TiN deposited with a nitrogen gas flow of about 13 sccm and then processed with rapid heat treatment at about 600° C. has a work function of about 4.6 eV, and TiN deposited with a nitrogen gas flow of about 14 sccm and then processed with rapid heat treatment at about 600° C. has a work function of about 5.0 eV. Accordingly, TiN with a desired work function may be obtained by properly controlling the nitrogen gas flow during deposition of TiN, and by performing a heat treatment after the deposition of TiN. Referring again to FIG. 1, in an implementation, the second barrier metal pattern 41b may be formed of a material having a work function of about 4.5 eV to about 5.0 eV. The second barrier metal pattern 41b may serve as a gate electrode.
FIG. 2 illustrates a cross-sectional view of a memory device according to a second embodiment of the present invention. In the following description of the second embodiment, those features that are different from the first embodiment will be mainly described. For clarity, a detailed description of features that are substantially the same in the second embodiment as those described in the first embodiment will not be repeated.
Referring to FIG. 2, an ohmic pattern 27a may be disposed between a polysilicon pattern 24a and a first barrier metal pattern 41a in a peripheral gate pattern 70 in the peripheral region of the substrate 10. The ohmic pattern 27a may include, e.g., a metal silicide such as one or more of tungsten silicide and titanium silicide. The ohmic pattern 27a may help reduce contact resistance between the polysilicon pattern 24a and the first barrier metal pattern 41a. Thus, signal delay in a peripheral circuit, which may be caused by an increased contact resistance, and defective operation of the memory device caused by the signal delay, may be reduced or eliminated.
Method for Forming a Memory Device
FIGS. 3 through 8 illustrate cross-sectional views of stages in a method of forming the memory device illustrated in FIG. 1. Referring to FIG. 3, a semiconductor substrate 10 may have a peripheral region and a cell region. A device isolation layer (not shown) defining active regions may be formed in the semiconductor substrate 10. The device isolation layer may be formed using, e.g., a general trench technology, a self-aligned trench technology, etc. A first insulating layer 21 may be formed on the substrate 10, and a polysilicon layer 24 may be formed on the first insulating layer 21. The first insulating layer 21 may be formed of, e.g., silicon oxide, and may be formed by, e.g., a thermal oxidation process, a chemical vapor deposition (CVD) process, etc.
The first insulating layer 21 may be used to form a gate insulating layer of peripheral circuit transistors formed in the peripheral region. The first insulating layer 21 may be formed to have a thickness that varies according to a location where the peripheral circuit transistors are formed. For example, the first insulating layer 21 may be relatively thick in a high-voltage region where a high-voltage transistor is formed, and may be relatively thin in a low-voltage region where a low-voltage transistor is formed. A mask pattern 29 may be formed on the polysilicon layer 24 in the peripheral region. The mask pattern 29 may be formed of, e.g., middle temperature oxide (MTO).
Referring to FIG. 4, an etching process may be performed using the mask pattern 29 as an etch mask to form a first insulating pattern 21a and a polysilicon pattern 24a in the peripheral region. The first insulating layer 21 and the polysilicon layer 24 in the cell region may be removed to expose the semiconductor substrate 10.
Referring to FIG. 5, a second insulating layer 31, a charge storage layer 34, and a third insulating layer 37 may be formed on the substrate 10. The second insulating layer 31 may be formed of, e.g., silicon oxide, and may be formed by, e.g., a thermal oxidation process, a CVD process, etc. The charge storage layer 34 may be formed of, e.g., one or more of silicon nitride and silicon oxide nitride, and may be formed by, e.g., a CVD process, an atomic layer deposition (ALD) process, etc. The third insulating layer 37 may be formed of, e.g., a metal oxide such as aluminum oxide.
Referring to FIG. 6, the second insulating layer 31, the charge storage layer 34, and the third insulating layer 37 may be patterned to form a second insulating pattern 31a, a charge storage pattern 34a, and a third insulating pattern 37a in the cell region. The mask pattern 29, the second insulating layer 31, the charge storage layer 34, and the third insulating layer 37 in the peripheral region may be removed to expose the polysilicon pattern 24a.
Referring to FIG. 7, a barrier metal layer 41 may be formed on the substrate on the polysilicon pattern 24a and on the third insulating pattern 37a. The barrier metal layer 44a may be formed of, e.g., metal nitride, and may have a work function of about 4.5 eV to about 5.0 eV. For example, the barrier metal layer 41 may be formed of one or more of TaN, TiN, WN, HfN, and ZrN, and may be formed by, e.g., a CVD process, a physical vapor deposition (PVD) process, an ALD process, etc. As described above, the barrier metal layer 41 having a desired work function may be formed by properly controlling the flow of nitrogen gas supplied to a process chamber in which a deposition process is performed, and by a heat treatment performed thereafter.
A conductive layer 44 may be formed on the barrier metal layer 41, and a mask pattern 47 may be formed on the conductive layer 44. The conductive layer 44 may be formed of, e.g., a metal material such as tungsten, and the mask pattern 47 may be formed of, e.g., a plasma enhanced oxide (PEOX).
Referring to FIG. 8, an etching process may be performed using the mask pattern 47 as an etch mask to pattern the barrier metal layer 41 and the conductive layer 44 to form a first barrier metal pattern 41a and a first conductive pattern 44a on the polysilicon pattern 24a in the peripheral region, and to form a second barrier metal pattern 41b and a second conductive pattern 44b on the third insulating pattern 37a in the cell region. As illustrated in FIG. 8, the mask pattern 47 may be etched while the barrier metal layer 41 and the conductive layer 44 are being etched in the etching process, and thus the thickness thereof may be decreased.
The polysilicon pattern 24a and the first insulating pattern 21a along sides of the mask pattern 47 in the peripheral region may be etched and removed by the etching process. However, in an implementation, the second insulating pattern 31a, the charge storage pattern 34a, and the third insulating pattern 37a along sides of the mask pattern 47 in the cell region may not be etched. It will be appreciated that whether the layers are etched or not may be suitably varied in other implementations (not shown).
Impurity regions 61 and 64 may be formed in the substrate 10, e.g., by an ion implantation process.
In this embodiment, the first barrier metal pattern 41a in the peripheral region and the second barrier metal pattern 41b in the cell region may be formed at the same time, and the first conductive pattern 44a in the peripheral region and the second conductive pattern 44b in the cell region may be formed at the same time. Thus, the manufacturing process of the memory device may be simplified.
FIGS. 9 through 14 illustrate cross-sectional views of stages in a method of forming the memory device illustrated in FIG. 2. In the following description of the second embodiment, only those features that are different from the first embodiment will be mainly described. For clarity, a detailed description of features that are substantially the same in the second embodiment as those described in the first embodiment will not be repeated.
Referring to FIG. 9, a first insulating layer 21 may be formed on the substrate 10, a polysilicon layer 24 may be formed on the first insulating layer 21, and an ohmic layer 27 may be formed on the polysilicon layer 24. The first insulating layer 21 may be formed of, e.g., silicon oxide, and may be formed by, e.g., a thermal oxidation process, a CVD process, etc. The ohmic layer 27 may be formed of, e.g., metal silicide such as one or more of tungsten silicide and titanium silicide, and may be formed by, e.g., a CVD process, a PVD process, an ALD process, etc. A mask pattern 29 may be formed on the ohmic layer 27 in a peripheral region. The mask pattern 29 may be formed of, e.g., MTO.
Referring to FIG. 10, an etching process may be performed using the mask pattern 29 as an etch mask to form a first insulating pattern 21a, a polysilicon pattern 24a, and an ohmic pattern 27a in the peripheral region. Here, the first insulating layer 21, the polysilicon layer 24, and the ohmic layer 27 in the cell region may be removed to expose the semiconductor substrate 10.
Referring to FIG. 11, a second insulating layer 31, a charge storage layer 34, and a third insulating layer 37 may be formed on the substrate 10. The second insulating layer 31 may be formed of, e.g., silicon oxide, and may be formed by, e.g., a thermal oxidation process, a CVD process, etc. The charge storage layer 34 may be formed of, e.g., one or more of silicon nitride and silicon oxide nitride, and may be formed by, e.g., a CVD process, an ALD process, etc. The third insulating layer 37 may be formed of, e.g., metal oxide such as aluminum oxide.
Referring to FIG. 12, the second insulating layer 31, the charge storage layer 34, and the third insulating layer 37 may be patterned to form a second insulating pattern 31a, a charge storage pattern 34a, and a third insulating pattern 37a on the cell region. The mask pattern 29, the second insulating layer 31, the charge storage layer 34 and the third insulating layer 37 in the peripheral region may be removed to expose the ohmic pattern 27a.
Referring to FIG. 13, a barrier metal layer 41 may be formed on the ohmic pattern 27a and on the third insulating pattern 37a. The barrier metal layer 41 may be formed of, e.g., metal nitride, and may have a work function of about 4.5 eV to about 5.0 eV. The barrier metal layer 41 may be formed of, e.g., one or more of TaN, TiN, WN, HfN and ZrN, and may be formed by, e.g., a CVD process, a PVD process, an ALD process, etc.
A conductive layer 44 may be formed on the barrier metal layer 41, and a mask pattern 47 may be formed on the conductive layer 44. The conductive layer 44 may be formed of a metal material, e.g., tungsten, and the mask pattern 47 may be formed of, e.g., PEOX.
Referring to FIG. 14, an etching process may be performed using the mask pattern 47 as an etch mask to pattern the barrier metal layer 41 and the conductive layer 44 so as to form a first barrier metal pattern 41a and a first conductive pattern 44a on the ohmic pattern 27a in the peripheral region, and to form a second barrier metal pattern 41b and a second conductive pattern 44b on the third insulating pattern 37a in the cell region. As illustrated in FIG. 14, the thickness of the mask pattern 47 may be reduced as it is etched while the barrier metal layer 41 and the conductive layer 44 are being etched in the etching process. During the etching process, the polysilicon pattern 24a and the first insulating pattern 21a at both sides of the mask pattern 47 in the peripheral region may be etched and removed. Thereafter, an ion implantation process may be performed to form impurity regions 61 and 64 in the substrate 10.
As in the first embodiment, in the second embodiment, the first barrier metal pattern 41a in the peripheral region and the second barrier metal pattern 41b in the cell region may be formed at the same time. Similarly, the first conductive pattern 44a in the peripheral region and the second conductive pattern 44b in the cell region may be formed at the same time. Thus, the manufacturing process of the memory device may be simplified.
According to embodiments of the present invention, a barrier metal layer having a high work function may be formed, and, since a cell gate electrode may be formed from the barrier metal layer, the manufacturing process may be simplified.
Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Patent Application
20080093663
