NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Abstract

A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be elecrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the attached drawings, in which:

FIG. 1A is a layout view of a nonvolatile memory device according to an exemplary embodiment of the present invention;

FIG. 1B is a cross sectional view taken along a line A-A′ of FIG. 1A;

FIG. 2 is a view illustrating the effects of a nonvolatile memory device according to an exemplary embodiment of the present invention;

FIG. 3 is an equivalent circuit diagram of a nonvolatile memory device according to an exemplary embodiment of the present invention;

FIG. 4 is a view illustrating an operation of a nonvolatile memory device according to an exemplary embodiment of the present invention; and

FIGS. 5A to 12B are views illustrating a method of fabricating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Claims

1. A nonvolatile memory device comprising: a semiconductor substrate;a source region that is formed in the semiconductor substrate;a gate insulating film that is formed so as to prtially overlap the source region on the semiconductor substrate;a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region;a control gate that is formed so as to be electrically isolated along one side of the floating gate from an pper part of the floating gate;an inter-gate insulating film that is interposed between the floating gate and the control gate; anda drain region that is formed so as to be adjacent the other side of hte control gate.

2. The nonvolatile memory device of claim 1, wherein the floating gate has a curvature of the other side thereof that is larger than a curvature of one side of the floating gate adjacent the source region.

3. The nonvolatile memory device of claim 2, wherein the curvature of one side of the floating gate adjacent to the source region is zero.

4. The nonvolatile memory device of claim 1, wherein a width of the overlap portion between the floating gate and the source region is uniform.

5. The nonvolatile memory device of claim 1, wherein a thickness of the inter-gate insulating film gradually becomes thinner from a center toward both ends.

6. A nonvolatile memory device comprising: a semiconductor substrate;a common source region that is formed in the semiconductor substrate;first and aecond gate insulating films that are formed on both sides of the common source region so as to partially overlap the common source region.first and second floating gates that are formed on the first and second gate insulating films, respectively, such that curvatures of hte other side thereof are larger than curvatures of one side adjacent the common source region;first and second control gates that are formed so as to be electrically isolated along the other side of the floating gate from an upper part of the first and second floating gates toward a direction opposite to the common source region, respectively;first and second inter-gate insulating films that are formed on the first and second floating gates and interposed between the first and second floating gates and the first and second control gates; andfirst and second drain regions that are formed so as to be adjacent the other side of the first and second control gates, respectively.

7. The nonvolatile memory device of claim 6, wherein the curvatures of one side of the first and second floating gates adjacent the source region are zero.

8. The nonvolatile memory device of claim 6, wherein a width of each of the overlap portion s between the first and second floating gates and the source region is uniform.

9. The nonvolatile memory device of claim 6, wherein a thickness of each of the first and second inter-gate insulating films gradually becomes thinner from a center toward both ends.

10. A method of fabricating a nonvolatile memory device, the method comprising: forming a poly-silicon pattern in which a first opening is formed so as to extend in one direction, on a semiconductor substrate;forming a common source region in the semiconductor substrate by a first ion injection process using the poly-silicon pattern as a mask;forming a blocking film on the poly-silicon pattern so as to bury the first opening;forming a second opening that exposes a portion of an upper surface of the poly-silicon pattern and the blocking film buried in the first opening by etching a portion of the blocking film;forming first and second inter-gate insulating films on the poly-silicon pattern divided into two sides by the blocking film buried in the first opening so as to be exposed by the second opening;removing the blocking film;forming first and second floating gates by etching the poly-silicon pattern by using the first and second inter-gate insulating films as an etching mask;forming first and second control gates on the first and second floating gates; andforming first and second drain regions at the other side of the first and second control gates.

11. The method of claim 10, wherein, in the forming of the second opening, the second opening is formed by over-etching the blocking film burying the first opening and a portion of the poly-silicon pattern.

12. The method of claim 10, wherein a thickness of each of the first and second inter-gate insulating films gradually becomes thinnre from a center toward both ends.

13. The method of claim 10, further comprising forming first and second tunneling films at a lateral-side of the first and second floating gates and on the semiconductor substrate by performing an oxidation process, after forming the first and second inter-gate insulating films.

14. The method of claim 10, further comprising performing a second ion injection process before forming the first and second inter-gate insulating films on the semiconductor substrate.

15. The method of claim 14, wherein a threshold voltage of the memory device is controlled through the second ion injection process.

16. The method of claim 14, wherein ions are doped into the poly-silicon pattern through the second ion injection process such that the first and second inter-gate insulating films are formed.

17. The mehtod of claim 10, further comprising performing a thermal process, after forming of the first and second control gates on the first and second floating gates.

18. The method of claim 10, wherein the blocking film is a nitride film.