Claims
- 1. In a nonvolatile semiconductor memory device comprising:
- a plurality of memory cells each of which has a threshold voltage corresponding to data of one of a write state and an erase state;
- a plurality of word lines each of which is coupled with corresponding memory cells of said plurality of memory cells; and
- a controller controlling a predetermined operation in response to a command supplied thereto,
- wherein said controller controls an erase operation to erase data of selected memory cells coupled to a word line when an erase command is supplied to said controller,
- wherein said controller controls a write operation to write data to a memory cell of said memory cells coupled to said word line when a write command is supplied to said controller,
- wherein said controller controls an additional write operation to write data to a memory cell which is a memory cells of said erase state in a word line coupled with memory cells being said write and said erase state when an additional write command is supplied to said controller,
- wherein, in said erase operation, threshold voltages of memory cells coupled to a word line are allocated to said erase state by using a tunnel phenomenon, and
- wherein, in said write and said additional write operation, a threshold voltage of a memory cell is allocated to said write state by using a tunnel phenomenon.
- 2. A nonvolatile semiconductor memory device according to claim 1, further comprising a circuit which forms a write expected value data based on data read from memory cells coupled to a selected word line and additional write data supplied from outside.
- 3. A nonvolatile semiconductor memory device according to claim 2, further comprising a data register which stores data to be written to a memory cell coupled to a selected word line,
- wherein, in said additional write operation, said data register stores said write expected value data.
- 4. A nonvolatile semiconductor memory device according to claim 3, further comprising a plurality of data lines each of which coupled with corresponding memory cells,
- wherein said data register is coupled to said plurality of data lines.
- 5. A nonvolatile semiconductor memory device according to claim 4, wherein each of said plurality of memory cells has a floating gate.
Priority Claims (2)
Number |
Date |
Country |
Kind |
8-178965 |
Jul 1996 |
JPX |
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9-126793 |
May 1997 |
JPX |
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Parent Case Info
This is a continuation application of U.S. Ser. No. 09/135,175, filed Aug. 18, 1998; which is a continuation application of U.S. Ser. No. 08/889,191, filed Jul. 8, 1997, now U.S. Pat. No. 5,867,428.
US Referenced Citations (3)
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Date |
Kind |
5327383 |
Merchant et al. |
Jul 1994 |
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5347489 |
Merchant et al. |
Sep 1994 |
|
5509134 |
Fandrich et al. |
Apr 1996 |
|
Continuations (2)
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Number |
Date |
Country |
Parent |
135175 |
Aug 1998 |
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Parent |
889191 |
Jul 1997 |
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