Patent Application
20070128815
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2005-348371 filed on Dec. 1, 2005; the entire contents of which are incorporated by reference herein.
1. FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory using silicon-on-insulator (SOI) substrate. In particular, it relates to the nonvolatile semiconductor memory and fabrication method for the same characterized by a higher-speed performance and a fabrication process miniaturization of fine patterns.
2. DESCRIPTION OF THE RELATED ART
A NAND flash EEPROM is known as an electrically erasable/programmable and highly integrated nonvolatile semiconductor memory. Each of memory cell transistors in the NAND flash EEPROM has a ‘stacked gate structure’ constructed by stacking a floating gate electrode layer for charge accumulation via an insulating film on a semiconductor substrate, and a control gate electrode layer disposed on the floating gate electrode layer via an inter-gate insulating film.
A NAND cell unit is constructed by serially connecting a plurality of memory cell transistors along the column direction with a source or drain region shared by adjacent memory cell transistors, and further disposing a select gate transistor at either end of the serially connected memory cell transistors.
A memory cell array has a plurality of NAND memory cell units aligned in a matrix. Furthermore, the plurality of NAND cell units aligned in parallel to the row direction is called a NAND cell block. The gate electrodes of a plurality of select gate transistors aligned in the same row direction are connected to the same select gate line, and the control gate electrodes of a plurality of memory cell transistors aligned in the same row direction are connected to the same control gate line.
As the process miniaturization of fine patterns of memory cell transistors develops, influences of capacitive-coupling effects between adjacent memory cell transistors, short-channel effects in the conductive channel of the memory cell transistors and the select gate transistors, influences of the parasitic capacitance in the STI region, and influences of the parasitic capacitance between each channel regions of the memory cell transistors and the semiconductor substrate are very much increasing. Therefore, the influences of the capacitive-coupling, the parasitic capacitances and short-channel effects should be much reduced. Furthermore, as memory cell transistors are miniaturized, the aspect ratio of gate contact holes for gate processing increases, resulting in increase in difficulty of the fabrication processing.
The stacked gate structure is formed through collective processing after formation of a two-layer gate structure made up of a floating gate and a control gate.
A NAND EEPROM having active areas for forming element regions, isolated from each other through shallow trench isolations (STIs), formed in a lattice structure in a SOI layer on a SOI substrate, and memory cells established in the active areas has already been disclosed (for example, see Japanese Patent Application Laid-open No. Hei 11-163303).
Meanwhile, a fabrication method of an insulating gate transistor by depositing an insulating film on the SOI layer surface via a silicon oxide film, forming an opening in a gate electrode formation region of the insulating film, implanting ions therein, forming a source and a drain through annealing process, and then embedding a metal gate, has also already been disclosed (for example, see Japanese Patent Application Laid-open No. 2001-185731).
An aspect of the present invention inheres in a nonvolatile semiconductor memory which includes: a semiconductor layer disposed on an insulating layer; a plurality of active regions extending along the column direction disposed in the semiconductor layer and isolated from each other by element isolating regions; a plurality of word lines extending along the row direction perpendicular to the plurality of active regions; and a plurality of memory cell transistors arranged in a matrix on the semiconductor layer. Each of the memory cell transistors includes source/drain regions provided on the plurality of active regions; a floating gate polysilicon electrode layer sandwiched between the source/drain regions via a tunneling insulating film provided on the semiconductor layer; an inter-gate insulating film disposed on the floating gate polysilicon electrode layer; and a control gate metallic electrode layer disposed on the floating gate polysilicon electrode layer via the inter-gate insulating film.
Another aspect of the present invention inheres in a nonvolatile semiconductor memory which includes a semiconductor layer disposed on an insulating layer; a plurality of active regions extending along the column direction disposed in the semiconductor layer and isolated from each other by element isolating regions; a plurality of control gate lines extending along the row direction perpendicular to the plurality of active regions; and a plurality of memory cell transistors arranged in a matrix on the semiconductor layer. Each of the memory cell transistors includes source/drain regions provided on the plurality of active regions; a floating gate electrode layer sandwiched between the source/drain regions and disposed via a tunneling insulating film provided on the semiconductor layer; an inter-gate insulating film disposed on sidewalls of the floating gate electrode layer and on the tunneling insulating film on the source/drain regions; and a control gate metallic electrode layer disposed facing the source/drain regions via the tunneling insulating film and the inter-gate insulating film and touching the sidewalls of the floating gate electrode layer via the inter-gate insulating film.
Another aspect of the present invention inheres in a fabrication method for a nonvolatile semiconductor memory, which includes forming a tunneling insulating film on a semiconductor layer, which is formed on an insulating layer; forming a floating gate polysilicon electrode layer on the tunneling insulating film; etching and removing the floating gate polysilicon electrode layer, the tunneling insulating film, the semiconductor layer, and the insulating layer; forming an element isolating region; depositing an inter-gate insulating film on the floating gate polysilicon electrode layer and the element isolating region, and a nitride film on the inter-gate insulating film consecutively; etching and removing the nitride film, the inter-gate insulating film, and the floating gate polysilicon electrode layer, exposing the tunneling insulating film; forming source/drain regions in the semiconductor layer; depositing an interlayer insulating film across the entire device surface; planarizing the entire device surface, and exposing the nitride film and the interlayer insulating film; removing the nitride film; depositing a control gate metallic electrode layer across the entire device surface; planarizing the entire device surface until the interlayer insulating film is exposed, and filling in and forming the control gate metallic electrode layers through a metal damascene process.
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
Referring to the drawings, embodiments of the present invention are described below. The embodiments shown below exemplify an apparatus and a method that are used to implement the technical ideas according to the present invention, and do not limit the technical ideas according to the present invention to those that appear below. These technical ideas, according to the present invention, may receive a variety of modifications that fall within the claims.
Next, a first to a third embodiment of the present invention are described while referencing drawings. Note that those drawings are merely schematics and thus relationship between thickness of respective parts and two-dimensional size thereof and ratio of respective parts in thickness may be inconsistent with reality according to the present invention. Moreover, it is natural that there are parts differing in relationship and ratio of dimensions among the drawings.
The technical ideas according to the present invention may be modified into a variety of modifications within the scope of the claimed invention.
Nonvolatile semiconductor memory and a fabrication method for the same according to the present invention allows reduction in the aspect ratio, implementation of simpler processing and reduction in the value of the parasitic capacitance between adjacent cells, miniaturization, higher integration, and simpler processing of a memory cell array, and low power consumption and higher speed operability.
(Basic Structure)
The basic structure of a memory cell transistor in a nonvolatile semiconductor memory according to the first embodiment of the present invention is, as shown in
(NAND Circuit Structure)
As schematically shown in
Each of a plurality of NAND cell units 32 is constituted by memory cell transistors MO through M15 and select gate transistors SG1 and SG2, as shown in detail in
A plurality of memory cell transistors M0 through M15 are serially connected extending along the column direction of a plurality of bit lines BLj−1, BLj, BLj+1 via n+ source/drain regions of the respective memory cell transistors, the select gate transistors SG1 and SG2 are disposed on either end the memory cell transistors M0 through M15, and the bit line contacts CB and the source line contacts CS are connected via these select gate transistors SG1 and SG2. As a result, this constitutes each of NAND cell units 32, which are arranged in parallel extending along the row direction of the plurality of word lines WL0, WL1, WL2, WL3, . . . , WL14, and WL15 perpendicular to the plurality of bit lines . . . , BLj−1, BLj, BLj+1, . . . .
Note that the memory cell transistors M0 through M15 may include channel regions with the same conductivity as the n+ source/drain regions 16, configuring a depletion mode MIS transistor. Similarly, the memory cell transistors M0 through M15 may include channel regions with the opposite conductivity to that of the n+ source/drain regions 16, configuring an enhancement mode MIS transistor. A ‘MIS transistor’ is defined as a field-effect transistor (FET) or a static induction transistor (SIT) configured to control a conduction of the channel current by an application of a gate voltage via an insulating film (gate insulating film) disposed between a gate electrode and a channel region. It is called a metal-oxide semiconductor field-effect transistor (MOSFET) when a silicon oxide film (SiO2) is used as the gate insulating film.
(Plan View Pattern Structure)
As shown in
(Device Structure)
The stacked gate memory cell transistors in the nonvolatile semiconductor memory according to the first embodiment of the present invention are disposed on the intersections of the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . , which extend along the column direction and are isolated from each other by element isolating regions STI, and the plurality of word lines WL0, WL1, WL2, . . . , WL15, which extend along the row direction perpendicular to the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . ; and each of the memory cell transistors is constructed by a semiconductor substrate 10; a SOI insulating layer 12 disposed in the semiconductor substrate 10; a SOI semiconductor layer 14 disposed on the SOI insulating layer 12; n+ source/drain regions 16 disposed facing each other in the SOI semiconductor layer; a tunneling insulating film 18 disposed on the SOI semiconductor layer 14; a floating gate polysilicon electrode layer 4 disposed on the tunneling insulating film 18; an inter-gate insulating film 25 disposed on the floating gate polysilicon electrode layer 4; and a control gate metallic electrode layer 70 disposed on the inter-gate insulating film 25, as shown in
Furthermore, as is apparent from
Memory cell transistors in nonvolatile semiconductor memory according to a modified example of the first embodiment of the present invention are disposed on the intersections of the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . , which extend along the column direction and are isolated from each other by STIs, and the plurality of word lines WL0, WL1, WL2,. . . , WL15, which extend along the row direction perpendicular to the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . ; and each of the memory cell transistors is constituted by the semiconductor substrate 10; the SOI insulating layer 12 disposed in the semiconductor substrate 10; the SOI semiconductor layer 14 disposed on the SOI insulating layer 12; the n+ source/drain regions disposed facing each other in the SOI semiconductor layer 14; the tunneling insulating film 18 disposed on the SOI semiconductor layer 14; the floating gate polysilicon electrode layer 4 disposed on the tunneling insulating film 18; the inter-gate insulating film 25 disposed on the floating gate polysilicon electrode layer 4; a buffer layer 26 disposed on the inter-gate insulating film 25; and the control gate metallic electrode layer 70 disposed on the buffer layer 26, as shown in
Furthermore, as is apparent from
(Select Gate Transistor)
Select gate transistors SG1, SG2 formed adjacent to the memory cell transistors M0 through M15 in the nonvolatile semiconductor memory according to the first embodiment of the present invention are constituted by the semiconductor substrate 10; the SOI insulating layer 12 formed in the semiconductor substrate 10; the SOI semiconductor layer 14 formed on the SOI insulating layer 12; the n+ source/drain regions 16 disposed facing each other in the SOI semiconductor layer 14; the tunneling insulating film 18 disposed on the SOI semiconductor layer 14; the floating gate polysilicon electrode layer 4 disposed on the tunneling insulating film 18; the inter-gate insulating film 25 having an opening disposed on the floating gate polysilicon electrode layer 4; and the control gate metallic electrode layer 70 disposed on the inter-gate insulating film 25 having the opening. The select gate transistors formed as such correspond to transistors SG1, SG2 having gate electrodes connected to the select gate lines SGD and SGS, as shown in
The select gate lines SGD and SGS becoming gate electrodes of the select gate transistors SG1, SG2 and arranged in parallel to the plurality of word lines WL0, WL1, WL2, . . . , WL15 may be formed in the same manner as the control gate metallic electrode layer 70.
(Fabrication Method)
(a) First, a SOI substrate made up of a semiconductor substrate 10, a SOI insulating layer 12 formed in the semiconductor substrate 10, and a SOI semiconductor layer 14 formed on the SOI insulating layer 12 is prepared, a tunneling insulating film 18 is formed on the SOI semiconductor layer 14, and a floating gate polysilicon electrode layer 4 is then formed on the tunneling insulating film 18.
Here, SiO2, sapphire (Al2O3), or the like is available as the materials for the SOI insulating layer 12 that allows achievement of the SOI structure. Monocrystalline silicon, silicon germanium (SiGe), or the like is available as the materials for the SOI semiconductor layer 14 provided on the SOI insulating layer 12. Furthermore, the SIMOX (Separation by implanted oxygen) method, a bonding method, or the like is available as a method for providing the SOI semiconductor layer 14 on the SOI insulating layer 12. With the SIMOX method, implanting oxygen ions into the semiconductor substrate 10 and then applying an annealing processing, forms the SOI insulating layer 12 in the semiconductor substrate 10 and the SOI semiconductor layer 14 on the SOI insulating layer 12. On the other hand, with the bonding method, the SOI insulating layer 12 is formed in one of two wafers, bonded together through an annealing process, and then one of the wafers is planarized and polished into a thin film, forming the SOI semiconductor layer 14 on the SOI insulating layer 12.
Although a silicon oxide film (SiO2) is the typical material for the tunneling insulating film 18, silicon nitride (Si3N4), tantalum oxide (Ta2O5), titanium oxide (TiO2), alumina (Al2O3), zirconium oxide (ZrO2), or the like is also available.
(b) Next, the floating gate polysilicon electrode layer 4 is patterned, the floating gate polysilicon electrode layer 4, the tunneling insulating film 18, the SOI semiconductor layer 14, and the SOI insulating layer 12 are etched and removed through reactive ion etching (RIE) or the like, and a tetraethoxysilane (TEOS) insulating film or the like is filled in and then planarized through chemical mechanical polishing (CMP), thereby forming STIs 30.
(c) Next, an inter-gate insulating film 25 is deposited on the floating gate polysilicon electrode layer 4 and the STIs 30, and a nitride film 11 is then deposited on the inter-gate insulating film 25.
As for the materials for the inter-gate insulating film 25, Si3N4, Ta2O5, TiO2, Al2O3, ZrO2, oxide-nitride-oxide (ONO), phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), silicon oxinitride (SiON), barium titanium oxide (BaTiO3), acid silicon fluoride (SiOxFy), an organic resin such as a polyimide or the like is available.
(d) Next, as shown in
(e) Next, as shown in
(f) An interlayer insulating film 28 is then deposited across the entire semiconductor device surface.
(g) Next, as shown in
As a result, stacked structures, each made up of the floating gate polysilicon electrode layer 4 on the tunneling insulating film 18, the inter-gate insulating film 25 on the floating gate polysilicon electrode layer 4, and the nitride film 11 on the inter-gate insulating film 25, are isolated by the interlayer insulating films 28, as shown in
(h) After the nitride films 11 are removed, a control gate metallic electrode layer 70 is deposited across the entire semiconductor device surface.
(i) Next, as shown in
As a result, the control gate metallic electrode layer 70 extending along the row direction are filled in and formed in a stripe form along the row direction, resulting in formation of a plurality of word lines WL0 through WL15.
In other words, as shown in
The control gate metallic electrode layer 70 corresponds to word lines and thus may be constituted using a metallic silicide film. Silicide material such as Cobalt (Co), Nickel (Ni), Titanium (Ti), Tantalum (Ta), Platinum (Pt), Molybdenum (Mo), Tungsten (W), or Palladium (Pd), for example, may be applied as the material for the metallic silicide film.
The fabrication method for the nonvolatile semiconductor memory according to the modified example of the first embodiment of the present invention is basically the same as that of the first embodiment. As shown in
Alternatively, in the process step (h), after the nitride films 11 are removed, the buffer layer 26 may be formed on the exposed inter-gate insulating films 25. Subsequent process steps are the same as with the first embodiment.
The fabrication method for the nonvolatile semiconductor memory having a stacked gate structure according to the first embodiment of the present invention, using which the floating gates are formed with polysilicon and which the control gates are formed with metallic electrode layers, has been described. Descriptions for the subsequent process steps are omitted, since a plurality of bit lines and peripheral circuit interconnect wirings are formed through a typical interconnect wirings/contacts formation processes.
According to the first embodiment of the nonvolatile semiconductor memory and the fabrication method for the same, using a metal damascene process in the formation of the control gate electrode layer allows reduction in the aspect ratio of the stacked structure, implementation of simpler processing and reduction in the value of parasitic capacitances between adjacent memory cells, miniaturization, higher integration, and simpler processing of a memory cell array, and low power consumption and higher speed operability of the nonvolatile semiconductor memory.
(Basic Structure)
The basic structure of a memory cell transistor in a nonvolatile semiconductor memory according to the second embodiment of the present invention is, as shown in
According to the sidewall control gate structure, parasitic capacitances around the floating gate polysilicon electrode layer 4 can be reduced, and an amount of increase in the value of the capacitance between the control gate metallic electrode layer 70 and the floating gate polysilicon electrode layer 4 allows an amount of decrease in the value of write-in voltage Vpgm. As a result, a highly integrated nonvolatile semiconductor memory which is capable of operating at high speed, can be realized.
Meanwhile, the number of control gate lines must be two for one memory cell transistor of the sidewall control gate structure, while only one control gate line is necessary for one memory cell transistor of the stacked gate structure; thus the memory cell array with the stacked gate structure has a simpler circuit structure. However, actually, as is evident through comparison of
(Plan View Pattern Structure)
The nonvolatile semiconductor memory according to the second embodiment of the present invention has a plurality of memory cell transistors arranged in a matrix on a SOI insulating layer, as shown in
(NAND Circuit Structure)
The matrix circuit structure of the nonvolatile semiconductor memory according to the second embodiment of the present invention is constituted by six NAND memory cell units 29a through 29f, a plurality of control gate lines CG1 through CG17, a plurality of select gate lines SG01 through SG03, a plurality of bit lines . . . , BLk−1, BLk, and BLk+1, . . . , a source line SL, a plurality of bit line driver circuits 21, a plurality of control gate line driver circuits 20, a plurality of select gate line driver circuits 23, and a source line driver circuit 24, as shown in
Note that as with the first embodiment, each of the memory cell transistors may be a depletion mode MIS transistor by including a channel region with the same conductivity as the n+ source/drain regions 16. Alternatively, each of the memory cell transistors may be an enhancement mode MIS transistor by including a channel region with the opposite conductivity to that of the n+ source/drain regions 16.
(Device Structure)
The memory cell transistors with the sidewall control gate structure in the nonvolatile semiconductor memory according to the second embodiment of the present invention are disposed adjacent to respective intersections of the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . , which extend along the column direction and are isolated from each other by STIs, and the plurality of control gate lines CG0, CG1, CG2, . . . , CG9, . . . , which extend along the row direction perpendicular to the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . .
Each of the memory cell transistors is constituted by a semiconductor substrate 10, a SOI insulating layer 12 disposed in the semiconductor substrate 10, a SOI semiconductor layer 14 disposed on the SOI insulating layer 12, n+ source/drain regions 16 disposed facing each other in the SOI semiconductor layer 14, a tunneling insulating film 18 disposed on the SOI semiconductor layer 14, a floating gate polysilicon electrode layer 4 disposed on the tunneling insulating film 18, an inter-gate insulating film 25 disposed on the sidewalls of the floating gate polysilicon electrode layer 4 and the tunneling insulating film 18 on the source/drain regions, and a control gate metallic electrode layer 70 disposed facing the sidewalls of the floating gate polysilicon electrode layer 4 via the inter-gate insulating film 25, and disposed facing the n+ source/drain regions 16 via the tunneling insulating film 18 and the inter-gate insulating film 25, as shown in
In
Furthermore, the control gate metallic electrode layer 70 is arranged on the n+ source/drain regions 16 via the tunneling insulating films 18 and the inter-gate insulating film 25, extending along the row direction, as shown in
In the structures shown in
Furthermore, as is apparent from
An arrangement of the buffer layer 26 on the inter-gate insulating film 25 and the control gate metallic electrode layer 70 on the buffer layer 26 can be realized even with the nonvolatile semiconductor memory according to the second embodiment of the present invention, as with the nonvolatile semiconductor memory according to the modified example of the first embodiment of the present invention. Providing the buffer layer 26 between the control gate metallic electrode layer 70 and the inter-gate insulating film 25 allows improvements in the adhesive characteristics between the control gate metallic electrode layer 70 and the inter-gate insulating film 25, and improvements in the reliability of the MIS structure made up of the control gate metallic electrode layer 70, the inter-gate insulating film 25, and the floating gate polysilicon electrode layer 4 or the n+ source/drain regions 16 in the sidewall control gate structure of the memory cell transistor, as shown in
(Select Gate Transistor)
Select gate transistors SG1, SG2, and SG3 formed adjacent to the end of the series-connected sidewall control gate memory cell transistors disposed along the column direction, in the nonvolatile semiconductor memory according to the second embodiment of the present invention, are constituted by the semiconductor substrate 10; the SOI insulating layer 12 formed in the semiconductor substrate 10; the SOI semiconductor layer 14 formed on the SOI insulating layer 12; the n+ source/drain regions 16 disposed in the SOI semiconductor layer 14; the tunneling insulating film 18 disposed on the SOI semiconductor layer 14; the floating gate polysilicon electrode layer 4 disposed on the tunneling insulating film 18; the inter-gate insulating film 25 having openings on sidewalls of the floating gate polysilicon electrode layer 4 and disposed on sidewalls of the floating gate polysilicon electrode layer 4 and also disposed on the tunneling insulating film 18 on the n+ source/drain regions 16; and the control gate metallic electrode layer 70 disposed facing the n+ source/drain regions 16 and connected to the floating gate polysilicon electrode layer 4 via the inter-gate insulating film 25 having the openings on the sidewalls of the floating gate polysilicon electrode layer 4.
The select gate transistors formed as such correspond to transistors SG1, SG2, and SG3 having gate electrodes connected to the select gate lines SG01, SG02, and SG03, as shown in
The select gate lines SG01, SG02, and SG03 becoming gate electrodes of the select gate transistors SG1, SG2, and SG3 and arranged in parallel to the plurality of control gate lines CG1, CG2, . . . , CG17, as shown in
Note that the gate structure of the select gate transistors is not limited to the above-described sidewall control gate structure. In order to secure the gate contacts of the select gate transistors, a contact electrode may be formed for the floating gate polysilicon electrode layer 4. The easiest method to secure the gate contacts of the select gate transistors is to form the gate electrode of the select gate transistors by short-circuiting the floating gate polysilicon electrode layer 4 with the control gate metallic electrode layer 70.
As described above, the structure connected at the sidewalls of the floating gate polysilicon electrode layers 4 can be easily and simply fabricated. Aside from this structure, a structure short-circuiting with the control gate metallic electrode layer 70 in the upper surface of the floating gate polysilicon electrode layers 4, for example, may be provided. Furthermore, instead of using the control gate metallic electrode layer 70, via hole contacts may be formed in the upper surface of the floating gate polysilicon electrode layers 4, connecting to other metallic electrodes for wirings than the control gate metallic electrode layer 70.
(Fabrication Method)
(a) First, as shown in
Here, SiO2, sapphire (Al2O3), or the like is available as the materials for the SOI insulating layer 12 that allows achievement of the SOI structure. Monocrystalline silicon, silicon germanium (SiGe), or the like is available as the materials for the SOI semiconductor layer 14 provided on the SOI insulating layer 12.
Although a silicon oxide film (SiO2) is the typical material for the tunneling insulating film 18, silicon nitride (Si3N4), tantalum oxide (Ta2O5), titanium oxide (TiO2), alumina (Al2O3), zirconium oxide (ZrO2), or the like is also available.
(b) Next, as shown in
(c) Next, as shown in
(d) Next, as shown in
(e) Next, as shown in
(f) Next, an inter-gate insulating film 25 is deposited across the entire semiconductor device surface.
As for the materials for the inter-gate insulating film 25, Si3N4, Ta2O5, TiO2, Al2O3, ZrO2, oxide-nitride-oxide (ONO), phosphorous Silicate glass (PSG), boron phosphorous silicate glass (BPSG), silicon oxinitride (SiON), barium titanium oxide (BaTiO3), acid silicon fluoride (SiOxFy), an organic resin such as a polyimide, or the like is available.
(g) A control gate metallic electrode layer 70 is then deposited across the entire semiconductor device surface.
(h) Next, as shown in
As a result, the control gate metallic electrode layer 70 extending along the row direction are filled in and formed in a stripe form along the row direction, forming a plurality of control gate lines CG0, CG1, CG2, . . . , CG17.
The control gate metallic electrode layer 70 corresponds to control gate lines and thus may be constituted using a metallic silicide film. Silicide material such as Cobalt (Co), Nickel (Ni), Titanium (Ti), Tantalum (Ta), Platinum (Pt), Molybdenum (Mo), Tungsten (W), Palladium (Pd), or the like, for example, may be applied as the material for the metallic silicide film.
The fabrication method for the nonvolatile semiconductor memory, according to the second embodiment of the present invention, having the sidewall control gate structure, which is fabricated by forming the floating gates with polysilicon and then forming the control gates with metallic electrode layers, has been described. Descriptions for the subsequent process steps are omitted since a plurality of bit lines and peripheral circuit interconnect wirings are formed through a typical interconnect wirings/contacts formation process.
According to the second embodiment of the nonvolatile semiconductor memory and the fabrication method for the same, using a metal damascene process in the formation of the control gate electrode layer in a memory cell transistor having the sidewall control gate structure allows reduction in the aspect ratio of the sidewall control gate structure, implementation of simpler processing and reduction in the value of parasitic capacitances between adjacent cells, miniaturization, higher integration, and simpler processing of a memory cell array, and low power consumption and higher speed operability of the nonvolatile semiconductor memory.
(Basic Structure)
The basic structure of a memory cell transistor in a nonvolatile semiconductor memory according to the third embodiment of the present invention is, as shown in
According to the sidewall control gate structure, as with the second embodiment, the parasitic capacitances around the floating gate metallic electrode layer 40 can be reduced, and an amount of increase in the value of the capacitance between the control gate metallic electrode layer 70 and the floating gate metallic electrode layer 40 allows an amount of decrease in the value of write-in voltage Vpgm. As a result, a highly integrated nonvolatile semiconductor memory, which is capable of operating at high speed, can be realized.
Furthermore, according to the nonvolatile semiconductor memory of the third embodiment of the present invention, miniaturization of fine patterns of memory cell transistors and a thin gate structure realizing a low aspect ratio can be further facilitated using metal damascene processes for both the floating gate metallic electrode layer 40 and the control gate metallic electrode layer 70, as shown in
(NAND Circuit Structure)
The matrix circuit structure of the nonvolatile semiconductor memory according to the third embodiment of the present invention is presented as with the second embodiment, for example. In other words, as shown in
The sixteen serially connected memory cell transistors in the NAND memory cell units 29a through 29f are connected to the respective bit lines . . . , BLk−1, BLk, and BLk+1, . . . via the select gate transistors SG1 or SG2 and a source line SL via the select gate transistors SG3. Furthermore, in
Note that as with the first and the second embodiment, the memory cell transistors may be a depletion mode MIS transistor by including a channel region with the same conductivity as the n+ source/drain regions 16. Alternatively, each of the memory cell transistors may be an enhancement mode MIS transistor by including a channel region with the opposite conductivity to that of the n+source/drain regions 16.
(Plan View Pattern Structure)
A plan view pattern structure of the nonvolatile semiconductor memory according to the third embodiment of the present invention is presented in
The nonvolatile semiconductor memory according to the third embodiment of the present invention has a plurality of memory cell transistors arranged in a matrix on a SOI insulating layer 12, as shown in
Moreover, the nonvolatile semiconductor memory according to the third embodiment of the present invention includes, as shown in
(Device Structure)
The memory cell transistors with the sidewall control gate structure in the nonvolatile semiconductor memory, according to the third embodiment of the present invention, are disposed adjacent to respective intersections of the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . , which extend along the column direction and are isolated from each other by STIs, and the plurality of control gate lines CG0, CG1, CG2, . . . , CG9, . . . , which extend along the row direction perpendicular to the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . .
Each of the memory cell transistors with the sidewall control gate structure includes: a semiconductor substrate 10; a SOI insulating layer 12 disposed in the semiconductor substrate 10; a SOI semiconductor layer 14 disposed on the SOI insulating layer 12; n+ source/drain regions 16 disposed facing each other in the SOI semiconductor layer 14; a tunneling insulating film 38 disposed on the SOI semiconductor layer 14 sandwiched between the n+ source/drain regions 16; a floating gate metallic electrode layer 40 disposed on the tunneling insulating film 38; an inter-gate insulating film 25 disposed on the sidewalls of the floating gate metallic electrode layer 40 and the source/drain regions 16; and a control gate metallic electrode layer 70 disposed facing the n+ source/drain regions 16 via the inter-gate insulating film 25 and facing the sidewalls of the floating gate metallic electrode layer 40 via the inter-gate insulating film 25, as shown in
In
Furthermore, the control gate metallic electrode layer 70 is arranged extending along the row direction on the n+ source/drain regions 16 via the inter-gate insulating film 25, as shown in
In the structures shown in
Furthermore, as is apparent from
An arrangement of the buffer layer 26 on the inter-gate insulating film 25 and the control gate metallic electrode layer 70 on the buffer layer 26 can be realized even with the nonvolatile semiconductor memory according to the third embodiment of the present invention, as with the nonvolatile semiconductor memory according to the modified example of the first embodiment of the present invention. Providing the buffer layer 26 between the control gate metallic electrode layer 70 and the inter-gate insulating film 25 allows improvements in the adhesive characteristics between the control gate metallic electrode layer 70 and the inter-gate insulating film 25, and improvements in reliability of the MIS structure made up of the control gate metallic electrode layer 70, the inter-gate insulating film 25, and the floating gate metallic electrode layers 40 or the n+ source/drain regions 16 in the sidewall control gate structure of the memory cell transistor, as shown in
(Select Gate Transistor)
The select gate transistors SG1, SG2, and SG3 formed adjacent to the end of the series-connected sidewall control gate memory cell transistors disposed along the column direction, in the nonvolatile semiconductor memory according to the third embodiment of the present invention, can be formed in the same way as in the second embodiment. For example, the select gate transistors SG1, SG2, and SG3 are constituted by the semiconductor substrate 10; the SOI insulating layer 12 formed in the semiconductor substrate 10; the SOI semiconductor layers 14 formed on the SOI insulating layer 12; the n+ source/drain regions 16 disposed facing each other in the SOI semiconductor layers 14; the tunneling insulating films 38, each disposed on the SOI semiconductor layers 14 sandwiched between the n+ source/drain regions 16; the floating gate metallic electrode layer 40 disposed on the tunneling insulating films 38; the inter-gate insulating film 25 having openings disposed on the sidewalls of the floating gate metallic electrode layer 40 and disposed on the n+ source/drain regions 16; and the control gate metallic electrode layer 70 formed facing the n+ source/drain regions 16 via the inter-gate insulating film 25 and connected to the floating gate metallic electrode layers 40 via the inter-gate insulating film 25 having the openings on the sidewalls of the floating gate metallic electrode layer 40.
The select gate transistors formed as such correspond to transistors SG1, SG2, and SG3 having gate electrodes connected to the select gate lines SG01, SG02, and SG03, as shown in
The select gate lines SG01, SG02, and SG03 becoming gate electrodes of the select gate transistors and arranged in parallel to the plurality of control gate lines CG1, CG2, . . . , CG17, as shown in
Note that the gate structure of the select gate transistors is not limited to the above-described sidewall control gate structure. In order to secure the gate contacts of the select gate transistors, a contact electrode may be formed for the floating gate metallic electrode layer 40. The easiest method to secure the gate contacts of the select gate transistors is to form the gate electrode of the select gate transistors by short-circuiting the floating gate metallic electrode layers 40 with the control gate metallic electrode layer 70.
As described above, the structure connected at the sidewalls of the floating gate metallic electrode layers 40 can be easily and simply fabricated. Aside from this structure, a structure short-circuiting with the control gate metallic electrode layer 70 in the upper surface of the floating gate metallic electrode layers 40, for example, may be provided. Furthermore, instead of using the control gate metallic electrode layer 70, via hole contacts may be formed in the upper surface of the floating gate metallic electrode layers 40, connecting to other metallic electrodes for wirings than the control gate metallic electrode layer 70.
(Fabrication Method)
(a) First, a SOI substrate made up of a semiconductor substrate 10, a SOI insulating layer 12 formed in the semiconductor substrate 10, and a SOI semiconductor layer 14 formed on the SOI insulating layer 12 are prepared, and a nitride film 22 is formed on the SOI semiconductor layer 14.
Here, SiO2, sapphire (Al2O3), or the like is available as the materials for the SOI insulating layer 12 achieving the SOI structure. Monocrystalline silicon, silicon germanium (SiGe), or the like is available as the materials for the SOI semiconductor layer 14 provided on the SOI insulating layer 12.
(b) Next, the nitride film 22 is patterned, the nitride film 22, the SOI semiconductor layer 14, and the SOI insulating layer 12 are etched and removed through the RIE techniques or the like, a TEOS insulating film or the like is filled in and then planarized through the CMP techniques, thereby forming STIs 30. As a result, the STIs 30 are formed in other areas than the plurality of active regions AA1, AA2, AA3, AA4, . . . , AA8, . . . , as shown in
(c) Next, the nitride film 22 is patterned, etched, and removed through the RIE techniques, exposing the SOI semiconductor layer 14.
(d) Next, the STIs 30 in which control gate lines are to be disposed are etched, providing a low surface height of STIs 30. The surface height of the STIs 30 may be formed higher than the surface height of the SOI semiconductor layer 14. The surface height of the STIs 30 may alternatively be formed to be approximately the same surface height as the SOI semiconductor layer 14.
(e) Next, as shown in
(f) Next, an inter-gate insulating film 25 is deposited across the entire semiconductor device surface.
As for the materials for the inter-gate insulating film 25, Si3N4, Ta2O5, TiO2, Al203, ZrO2, oxide-nitride-oxide (ONO), phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), silicon oxinitride (SiON), barium titanium oxide (BaTiO3), acid silicon fluoride (SiOxFy), an organic resin such as a polyimide, or the like is available.
(g) A control gate metallic electrode layer 70 is then deposited across the entire semiconductor device surface, as shown in
(h) Next, as shown in
As a result, the control gate metallic electrode layer 70 extending along the row direction are filled in and formed in a stripe form along the row direction, forming a plurality of control gate lines CG0, CG1, CG2, . . . , CG17.
The control gate metallic electrode layer 70 corresponds to control gate lines and thus may be constituted using a metallic silicide film. Silicide material such as Cobalt (Co), Nickel (Ni), Titanium (Ti), Tantalum (Ta), Platinum (Pt), Molybdenum (Mo), Tungsten (W), Palladium (Pd), or the like may be applied as the material to form the metallic silicide film.
(i) Next, the nitride film 22 is patterned, etched, and removed through the RIE techniques, exposing the surface of the SOI semiconductor layer 14.
(j) Next, as shown in
Although a silicon oxide film (SiO2) such as a thermal-oxidation film or an insulating film formed at a low temperature CVD is the typical material for the tunneling insulating film 38, silicon nitride (Si3N4), tantalum oxide (Ta2O5), titanium oxide (TiO2), alumina (Al2O3), zirconium oxide (ZrO2), or the like is also available.
(k) A floating gate metallic electrode layer 40 is then deposited across the entire semiconductor device surface.
(l) Next, as shown in
While the floating gate metallic electrode layers 40 correspond to charge accumulating layers of the memory cell transistors constituting the nonvolatile semiconductor memory, the floating gate metallic electrode layers 40 may be constituted using a metallic silicide film. Silicide material such as Cobalt (Co), Nickel (Ni), Titanium (Ti), Tantalum (Ta), Platinum (Pt), Molybdenum (Mo), Tungsten (W), Palladium (Pd), or the like may be applied as the material to form the metallic silicide film.
The fabrication method for the nonvolatile semiconductor memory, according to the third embodiment of the present invention, having the sidewall control gate structure, which is fabricated by forming the floating gates and the control gates using metallic electrode layers, has been described. Descriptions for the subsequent process steps are omitted since a plurality of bit lines and peripheral circuit interconnect wirings are formed through a typical interconnect wirings/contacts formation process.
According to the third embodiment of the nonvolatile semiconductor memory of the present invention and the fabrication method for the same, using the metal damascene processes in the formation of the metallic electrode layers of both control gates and floating gates in the memory cell transistor with the sidewall control gate structure allows reduction in the aspect ratio, implementation of simpler processing and reduction in the value of parasitic capacitances between adjacent cells, miniaturization, higher integration, and simpler processing of a memory cell array, and low power consumption and higher speed operability of the nonvolatile semiconductor memory.
Applications
The nonvolatile semiconductor memory according to the first through the third embodiment of the present invention may be applied in various ways. Some of these applications are shown in
In the application examples of the nonvolatile semiconductor memory according to the first through the third embodiment of the present invention and the fabrication method for the same, using of a metal damascene process in the formation of the metallic electrode layers of either or both control gates and floating gates in the memory cell transistor allows reduction in the aspect ratio, implementation of simpler processing and reduction in the value of parasitic capacitances between adjacent cells, miniaturization, higher integration, and simpler processing of a memory cell array, and low power consumption and higher speed operability of not only the nonvolatile semiconductor memory but of the apparatus according to the application examples including peripheral circuits.
(Application 1)
The host platform 144 is connected to the USB flash unit 146 via a USB cable 148. The host platform 144 is connected to the USB cable 148 via a USB host connector 150, and the USB flash unit 146 is connected to the USB cable 148 via a USB flash unit connector 152. The host platform 144 has a USB host controller 154, which controls packet transmission through a USB bus.
The USB flash unit 146 includes a USB flash unit controller 156, which controls other elements in the USB flash unit 146 as well as controls the interface to the USB bus of the USB flash unit 146; the USB flash unit connector 152; and at least one flash memory module 158 configured with the nonvolatile semiconductor memory according to the first through the third embodiment of the present invention.
When the USB flash unit 146 is connected to the host platform 144, standard USB enumeration processing begins. In this processing, the host platform 144 recognizes the USB flash unit 146, selects the mode for transmission therewith, and performs reception/transmission of data from/to the USB flash unit 146 via a FIFO buffer called an end point, which stores transfer data. The host platform 144 recognizes changes in the physical and electrical states such as removal/attachment of the USB flash unit 146 via another end point, and receives any existing to-be-received packets.
The host platform 144 requests services from the USB flash unit 146 by sending a request packet to the USB host controller 154. The USB host controller 154 transmits the packet to the USB cable 148. If the USB flash unit 146 is a unit including the end point that has received this request packet, this request will be accepted by the USB flash unit controller 156.
Next, the USB flash unit controller 156 performs various operations such as read-out, write-in or erasure of data from or to the flash memory module 158. In addition, it supports basic USB functions such as acquiring a USB address and the like. The USB flash unit controller 156 controls the flash memory module 158 via either a control line 160, which is used to control output of the flash memory module 158, or, for example, other various signals such as a chip enable signal CE, a read-out signal, or a write-in signal. Furthermore, the flash memory module 158 is also connected to the USB flash unit controller 156 via an address data bus 162. The address data bus 162 transfers a read-out, a write-in or an erasure command for the flash memory module 158, and the address and data for the flash memory module 158.
In order to notify the host platform 144 of the results and status of the various operations requested by the host platform 144, the USB flash unit 146 transmits a status packet using a status end point (end point 0). In this processing, the host platform 144 checks (polls) for the existence of a status packet, and the USB flash unit 146 returns an empty packet or a status packet when there is no packet for a new status message.
As described thus far, various functions of the USB flash unit 146 maybe implemented. Directly connecting the connectors is also possible by omitting the USB cable 148 described above.
(Memory Card)
(Application 2)
As an example, a memory card 260 including a semiconductor memory device 250 is configured as shown in
A signal line DAT, a command line enable signal line CLE, an address line enable signal line ALE, and a ready/busy signal line R/B are connected to the memory card 260 housing the semiconductor memory device 250. The signal line DAT transfers a data signal, an address signal, or a command signal. The command line enable signal line CLE transmits a signal indicating that a command signal is being transferred over the signal line DAT. The address line enable signal line ALE transmits a signal indicating that an address signal is being transferred over the signal line DAT. The ready/busy signal line R/B transmits a signal indicating whether or not the semiconductor memory device 250 is ready to operate.
(Application 3)
Another specific example of the memory card 260 differs from the exemplary memory card of
The interface unit (I/F) 271 transmits and receives a predetermined signal to and from the external device, and the interface unit (I/F) 272 transmits and receives a predetermined signal to and from the semiconductor memory device 250. The microprocessor unit (MPU) 273 converts a logical address to a physical address. The buffer RAM 274 temporarily stores data. The error-correction code unit (ECC) 275 generates an error-correction code.
A command signal line CMD, a clock signal line CLK, and the signal line DAT are connected to the memory card 260. The number of control signal lines, the bit width of the signal line DAT, and the circuit structure of the controller 276 may be modified as needed.
(Application 4)
Yet another exemplary configuration of the memory card 260 implements a system LSI chip 507 that integrates the interface units (I/F) 271 and 272, the microprocessor unit (MPU) 273, the buffer RAM 274, the error-correction code unit (ECC) 275 included in the interface unit (I/F) 272, and a semiconductor memory device area 501, as shown in
(IC Card)
(Application 5)
Yet another application of the nonvolatile semiconductor memory according to the first through the third embodiment of the present invention is constituted by an interface circuit (IC) card 500, which includes a MPU 400, which is constituted by the semiconductor memory device 250, ROM 410, RAM 420, and a CPU 430, and a plane terminal 600, as shown in
The nonvolatile semiconductor memory described in detail in the first through the third embodiment of the present invention may be applied to the semiconductor memory device 250 or the ROM 410 in
(Application 6)
Yet another exemplary configuration of the IC card 500 includes a system LSI chip 508, which integrates the ROM 410, the ROM 420, the CPU 430, and the semiconductor memory device area 501, as shown in
As described above, the present invention is described according to the first through the third embodiment; however, it should not be perceived that descriptions and drawings forming a part of this disclosure are not intended to limit the spirit and scope of the present invention. Various alternative embodiments, working examples, and operational techniques will become apparent from this disclosure for those skills in the art.
Various variations and modifications are naturally possible in the fabrication process for the memory cell transistor in the nonvolatile semiconductor memory according to the first through the third embodiment of the present invention.
Moreover, the memory cell transistor of the nonvolatile semiconductor memory according to the first through the third embodiment is not limited to binary logic memory. For example, multi-valued logic memory, more specifically three or more valued memory is also applicable. For example, four-valued nonvolatile semiconductor memory can have a memory capacity twice that of the two-valued nonvolatile semiconductor memory. In addition, the present invention is applicable to m or more valued nonvolatile semiconductor memory (m>3).
While NAND flash EEPROM has been described thus far, the configuration of the memory cell transistor in the nonvolatile semiconductor memory according to the first through the third embodiment and the fabrication method for the same hold true for memory according to other operating methods such as an AND type, a NOR type, a two-transistor/cell type, a three-transistor/cell type, or the like.
As such, the present invention naturally includes various embodiments not described herein. Accordingly, the technical scope of the present invention is determined only by specified features of the invention according to the following claims that can be regarded appropriate from the above-mentioned descriptions.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-348371 | Dec 2005 | JP | national |
