NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS FABRICATION METHOD

Abstract

A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of principal parts of a MONOS nonvolatile memory according to one embodiment of the present invention;

FIG. 2 is a cross-sectional view of principal parts of the MONOS nonvolatile memory according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view of principal parts showing a method of fabricating the MONOS nonvolatile memory according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 3;

FIG. 5 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 4;

FIG. 6 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 5;

FIG. 7 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 6;

FIG. 8 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 7;

FIG. 9 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 8;

FIG. 10 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 9;

FIG. 11 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 10;

FIG. 12 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 11;

FIG. 13 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 12;

FIG. 14 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 13;

FIG. 15 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 14;

FIG. 16 is a cross-sectional view of principal parts showing a method of fabricating a MONOS nonvolatile memory according to another embodiment of the present invention.

FIG. 17 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 16;

FIG. 18 is a cross-sectional view of principal parts showing a method of fabricating a MONOS nonvolatile memory according to another embodiment of the present invention;

FIG. 19 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 18;

FIG. 20 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 19;

FIG. 21 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 20;

FIG. 22 is a cross-sectional view of principal parts showing a method of fabricating a MONOS nonvolatile memory according to another embodiment of the present invention.

FIG. 23 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 22;

FIG. 24 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 23;

FIG. 25 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 24;

FIG. 26 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 25;

FIG. 27 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 26;

FIG. 28 is a cross-sectional view of principal parts showing a method of fabricating a MONOS nonvolatile memory according to another embodiment of the present invention.

FIG. 29 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 28;

FIG. 30 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 29;

FIG. 31 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 30;

FIG. 32 is a cross-sectional view of principal parts showing a method of fabricating a MONOS nonvolatile memory according to another embodiment of the present invention.

FIG. 33 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 32;

FIG. 34 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 33;

FIG. 35 is an equivalent circuit diagram showing a conventional MONOS nonvolatile memory;

FIG. 36 is an equivalent circuit diagram of a memory array using the MONOS nonvolatile memory shown in FIG. 35;

FIG. 37 is a pattern diagram for schematically explaining a write operation performed by the MONOS nonvolatile memory shown in FIG. 35;

FIG. 38 is a pattern diagram for schematically explaining an erasing operation performed by the MONOS nonvolatile memory shown in FIG. 35;

FIG. 39 is a plan view of the MONOS nonvolatile memory shown in FIG. 35;

FIG. 40 is a cross-sectional view taken along a line A-A of FIG. 39;

FIG. 41 is a cross-sectional view of principal parts showing a method of fabricating the MONOS nonvolatile memory shown in FIG. 35.

FIG. 42 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 41;

FIG. 43 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 42;

FIG. 44 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 43; and

FIG. 45 is a cross-sectional view of principal parts showing the method of fabricating the MONOS nonvolatile memory subsequent to FIG. 44.

Claims

1. A semiconductor device comprising a split-gate memory cell, the memory cell including: a selective gate formed on a principal surface of a semiconductor substrate through a gate insulating layer;a memory gate formed on one side surface of the selective gate, the memory gate being in a form of a sidewall; andan ONO layer with a generally L-shaped cross section, includes one part formed between one side surface of the selective gate and one side surface of the memory gate, and an other part formed below the memory gate,wherein a second insulating layer is formed on an other side surface of the memory gate through a first insulating layer, the first insulating layer being in the form of the sidewall, the second insulating layer being in the form of the sidewall,the second insulating layer in the form of the sidewall is formed on an other side surface of the selective gate, andone end of the ONO layer formed on the semiconductor substrate is terminated below the first insulating layer.

2. The semiconductor memory device according to claim 1, wherein hot electrons generated in the semiconductor substrate are injected into the ONO layer by applying a first voltage to the semiconductor substrate near the memory gate and a second voltage higher than the first voltage to the memory gate during a write operation.

3. The semiconductor memory device according to claim 2, wherein an erasing operation is performed by injecting holes into the ONO layer into which the hot electrons have been injected.

4-10. (canceled)