Nonvolatile semiconductor memory device provided with data register for temporally holding data in memory array

Abstract

A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking the signal including the pulse every access cycle with respect to the data register when access to a memory cell other than a predetermined memory cell in the data register is designated in a second mode. A first precharge circuit precharges a bit line pair in response to activation of the precharge signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a constitution of a nonvolatile semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a view showing a constitution of a data register and a peripheral circuit group;

FIG. 3 is a view showing a mat in a data register and a constitution of a circuit connected to the mat;

FIG. 4 is a view showing a constitution of a memory cell and a first precharge circuit;

FIG. 5 is a view for explaining an operation of data register and peripheral circuit group when data in a flash memory cell array is transferred to memory cells in the sub-mats for a high-order bit of all mats in data register;

FIG. 6 is a schematic view showing a timing chart at a SLSRAM transfer in a first mode;

FIG. 7 is a schematic view showing a timing chart at the SLSRAM transfer in a second mode;

FIG. 8 is a view for explaining an operation of the data register and peripheral circuit group when the data from outside is transferred to memory cells in the sub-mat for a high-order bit and the sub-mat for a low-order bit in a mat in data register;

FIG. 9 is a schematic view showing a timing chart at an IOSRAM transfer in a first mode;

FIG. 10 is a schematic view showing a timing chart at the IOSRAM transfer in a second mode;

FIG. 11 is a schematic view showing a constitution of a precharge signal generation circuit;

FIG. 12 is a detailed view showing a timing chart at the SLSRAM transfer in the second mode;

FIG. 13 is a detailed view showing a timing chart at the IOSRAM transfer in the second mode;

FIGS. 14A and 14B are views for explaining an operation of randomly outputting data in a page of flash memory cell array;

FIGS. 15A, 15B and 15C are views for explaining an operation of randomly updating the data in the page of flash memory cell array;

FIG. 16 is a view showing a precharge signal generation circuit according to a variation; and

FIG. 17 is a view showing a second precharge circuit.

Claims

1. A nonvolatile semiconductor memory device comprising: a nonvolatile memory cell array including a plurality of memory cells;a data register including a plurality of memory cells, for temporally holding read data from said nonvolatile memory cell array and written data to said nonvolatile memory cell array;a signal generation circuit for outputting a first signal including a pulse every reading or writing cycle with respect to said data register in a first mode, and generating a first signal by masking the signal including the pulse every reading or writing cycle with respect to said data register when reading or writing with respect to a memory cell other than a predetermined memory cell in said data register is designated in a second mode; anda first precharge circuit for precharging a bit line pair connected to the memory cell in said data register in response to activation of said first signal, whereinsaid signal generation circuit cancels said masking when reading or writing with respect to said predetermined memory cell in said data register is designated in said second mode.

2. The nonvolatile semiconductor memory device according to claim 1, wherein a position of the memory cell in said data register in a column direction is designated by a column address, andsaid predetermined memory cell has a maximum column address.

3. The nonvolatile semiconductor memory device according to claim 2, further comprising: a sense amplifier connected to a common wiring pair connected to a common connection node of the plurality of bit line pairs in said data register, anda Y gate connecting the bit line pair corresponding to the designated column address to said sense amplifier.

4. The nonvolatile semiconductor memory device according to claim 3, further comprising a second precharge circuit for precharging the common wiring pair connected to said sense amplifier, wherein said signal generation circuit further outputs a second signal including a pulse every reading cycle with respect to said data register in the fist and second modes, andsaid second precharge circuit precharges the common wiring pair connected to said sense amplifier in response to the activation of said second signal.

5. The nonvolatile semiconductor memory device according to claim 2, wherein in said second mode, said signal generation circuit outputs the activated first signal at standby, and cancels said masking when said designated column address reaches the maximum even when reading or writing access is started from a column having an column address other than a minimum column address in said data register.

6. The nonvolatile semiconductor memory device according to claim 1, further comprising a word line driver for controlling the activation of a word line connected to the memory cell in said data register, wherein said word line driver deactivates said word line in response to the activation of said first signal.

7. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell included in said data register is a SRAM cell.

8. The nonvolatile semiconductor memory device according to claim 1, further comprising a sense latch for holding read data from said nonvolatile memory array, wherein the memory cell in said nonvolatile memory array holds N-bit (N is an integer not less than 1) data,said data register is divided into M (M is an integer not less than 2) mats,said each mat includes N sub-mats in accordance with said N bits,positions of the memory cells in said each sub-mat in a column direction are designated by a first to K-th (K is an integer not less than 2) column addresses,said sense latch simultaneously transfers said read data to the memory cells having the designated column addresses in the sub-mat having a designated order in each of M mats, andsaid predetermined memory cell has the K-th column address.

9. The nonvolatile semiconductor memory device according to claim 1, further comprising an input control circuit for controlling transfer of N-bit (N is an integer not less than 1) written data from outside to said data register, wherein said nonvolatile memory array holds the N-bit data,said data register is divided into M (M is an integer not less than 2) mats,said each mat includes N sub-mats in accordance with said N bits,positions of the memory cells in said each sub-mat in a column direction are designated by a first to K-th (K is an integer not less than) column addresses,said input control circuit simultaneously transfers said written data to the memory cells having the designated column addresses in N pairs of sub-mats in the mat having a designated order, andsaid predetermined memory cell has the K-th column address of the M-th mat.