Patent Application
20100309721
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2009-136338, filed Jun. 5, 2009; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to an electrically programmable nonvolatile semiconductor memory device, and relates to, e.g., a NAND flash memory.
In a NAND flash memory, a structure in which a plurality of memory cells are connected in series is determined as a basic unit (NAND unit), and one end of this NAND unit is connected to a bit line via a select gate (SGD) whilst the other end is connected with a source line via a select gate (SGS).
Reading and writing in the NAND flash memory are collectively performed in units called one page that achieves connection with one word line. Further, a page aggregate sandwiched between the select gate (SGD) on the bit line side and the select gate (SGS) on the source line side constitutes a block.
To cancel out a Yupin effect in the bit line and word line directions, there is a method of dividing a write method into “rough writing” and “actual writing” to be performed. Furthermore, there is a method of performing N writes after a given threshold voltage is exceeded and then terminating writing when a read operation in rough writing is not required. N is a value which differs depending on a threshold voltage of each value in a multilevel product in which memory cells store multiple values. This method has the merit that verification at a threshold voltage of each value is not required and hence the time per write loop is shortened, which leads to a reduction in write time. It should be noted that the Yupin effect means that, if the gap between memory cells adjacent to each other is narrow, the influence of parasitic capacitance between adjacent elements increases to deviate a threshold value.
In this method, if one of the latches that save data during writing is not required, an operation of, e.g., inputting next write data to this latch (a cache operation), may be performed (see, e.g., JP-A 2006-134558 [KOKAI]).
However, in the method of performing N writes after a given threshold voltage is exceeded and then terminating writing, and in the cache operation, a data transfer operation must be performed many times to set or change write data that is to be latched or to set or change the number of writes, which obstructs a reduction in write time.
In general, according to one embodiment, a nonvolatile semiconductor memory device includes a memory cells, a bit line, a sense amplifier, a memory circuit and an arithmetic circuit. The memory cells store multiple values in one memory cell. The bit line connected with the memory cells. The sense amplifier supplies a write voltage to the bit line. The memory circuit stores one of write data that is to be written in the memory cell and the number of writes. The arithmetic circuit changes the write data stored in the memory circuit to the number of writes and updates the number of writes. The arithmetic circuit controls the write voltage supplied from the sense amplifier based on the write data, and sets the number of writes in accordance with the write data stored in the memory circuit upon confirmation that each memory cell has reached a predetermined threshold voltage.
A nonvolatile semiconductor memory device according to an embodiment will now be described hereinafter with reference to the drawings. Here, a NAND flash memory will be taken as an example of a nonvolatile semiconductor memory device. Throughout the drawings, like reference numbers denote like parts for the explanation.
A NAND flash memory according to a first embodiment will be first described.
As depicted in the drawing, the NAND flash memory includes a memory cell array 11, a bit line control circuit 12, a column decoder 13, a row decoder 14, a source line control circuit 15, a well control circuit 16, a data input/output buffer 17, a data input/output terminal 18, a control circuit 19, and a control signal input terminal 20.
The memory cell array 11 has the following configuration. A structure in which a plurality of memory cells MC are connected in series is determined as a basic unit (NAND unit). One end of the NAND unit is connected with a bit line BL via a select gate SGD, and the other end of the NAND unit is connected with a source line SL via a select gate SGS.
Data reading and writing are collectively performed in units called one page that achieves connection with one word line WL. Moreover, a page aggregate sandwiched between the select gate SGD on the bit line side and the select gate SGS on the source line side constitutes a block.
The bit line control circuit 12 is arranged in accordance with each bit line BL, and it supplies a write voltage to a bit line at the time of a write operation and reads data stored in the memory cell MC from a bit line BL at the time of a read operation. During the read operation, data read to the bit line control circuit 12 from the memory cell MC is output to the data input/output terminal 18 via the data input/output buffer 17. The column decoder 13 selects a bit line BL connected with the memory cell MC in the memory cell array 11.
The row decoder 14 includes a word line driving circuit, and it selects and drives a word line WL connected with the memory cell in the memory cell array 11. The source line control circuit 15 and the well control circuit 16 supply predetermined write voltages to a source line and a well region at the time of a write operation, respectively.
Additionally, to the control circuit 19 are supplied external control signals such as a chip enable signal/CE, a write enable signal/WE, a read enable signal/RE, an address latch enable signal ALE, a command latch enable signal CLE and others from the control signal input terminal 20. The control circuit 19 controls operations of the bit line control circuit 12, the column decoder 13, the row decoder 14, the source line control circuit 15, the well control circuit 16 and the data input/output buffer 17 based on external control signals and commands supplied in accordance with operation modes, thereby effecting data write and erase sequence control and data read control.
A configuration of the bit line control circuit 12 arranged in accordance with each bit line will now be described.
When the memory cell stores four values, the bit line control circuit 12 arranged in accordance with each bit line has three latches, i.e., latch A 21, a latch B 22 and latch C 23 as memory circuits, an arithmetic circuit 24 and a sense amplifier 25. The data input/output buffer 17 is connected with latch A 21, and latch A 21 is connected with latch B 22 and latch C 23. Latch A 21, latch B 22 and latch C 23 are connected with the arithmetic circuit 24, and the sense amplifier 25 is connected with the arithmetic circuit 24. Additionally, a bit line is connected with the sense amplifier 25.
The memory circuit stores either write data which is to be written into the memory cell or the number of writes. In accordance with write data stored in the memory circuit, the arithmetic circuit 24 transfers to the sense amplifier 25 the write data or non-write data if writing is terminated. The sense amplifier 25 supplies a write voltage to a bit line. Further, the arithmetic circuit 24 changes the write data stored in the memory circuit to the number of writes and updates the number of writes. Moreover, the arithmetic circuit 24 controls a write voltage supplied from the sense amplifier 25 based on the write data stored in the memory circuit and sets the number of writes in accordance with the write data stored in the memory circuit upon confirmation that the memory cell has reached a predetermined threshold voltage.
A write operation in the NAND flash memory according to the first embodiment will now be described.
In the write operation, the write operation is usually terminated by first performing “rough writing” and then “actual writing”. In rough writing, writing is performed until a predetermined threshold voltage is reached, and then a predetermined number of writes are performed in accordance with write data to set a desired threshold voltage. The actual writing is effected after the rough writing, and a threshold voltage of each memory cell is accurately adjusted to fall within a threshold voltage distribution of each value.
In the embodiment, a description will now be given of rough writing as the write operation.
An outline of the write operation in the first embodiment will be first explained.
Writing is repeatedly performed with respect to a write target memory cell until a threshold voltage “1” is reached, and writing is terminated after reaching the threshold voltage “1” when writing “1”. Furthermore, when writing “2”, after the threshold voltage “1” is reached, X writes are performed, and then writing is terminated. When writing “3”, after the threshold voltage “1” is reached, Y writes are performed, and then writing is completed. At this time, write data which is to be stored in each latch and a bit pattern corresponding to the number of writes are optimized to reduce the number of data transfer operations in each latch. In this example, each of X and Y is a natural number less than or equal to 4 on the basis of the number of latches.
The write operation in the first embodiment will now be described in detail with reference to
As shown in the drawing, write data is first input to latch A 21 from the data input/output buffer 17 (step S1). Subsequently, the write data is transferred to latch B 22 or latch C 23 from latch A 21 (step S2).
Then, when latch A 21, latch B 22 and latch C 23 are all high, the arithmetic circuit 24 determines that writing is terminated and transfers non-write data to the sense amplifier 25. On the other hand, if even one of latch A 21, latch B 22 and latch C 23 is low, the arithmetic circuit 24 transfers write data to the sense amplifier 25 (step S3).
Subsequently, writing (a program) is effected with respect to the memory cell MC. During this writing, data in each of latch A 21, latch B 22 and latch C 23 is confirmed (detection). If latch A 21 is low or latch A 21, latch B 22 and latch C 23 are all high (detection success), a circuit that counts the number of write loops starts to operate (step S4).
Then, if the detection fails in step S4, i.e., if latch A 21 is low or none of latch A 21, latch B 22 and latch C 23 is high, the control advances to step S6 to perform a confirmation (verification) operation of checking whether the write target memory cell MC has reached the threshold voltage “1”.
Here, if the write target memory cell has not reached the threshold voltage “1”, the control returns to step S3 to repeat the operations in steps S3, S4 and S6 until the threshold voltage “1” is reached.
On the other hand, if the write target memory cell MC has reached the threshold voltage “1” in step S6, the bit pattern in latches A, B and C is changed to all-high as represented by (a) in
Further, if the write target memory cell is a memory cell in which “2” is written, the bit pattern in each of latches A, B and C is changed to a bit pattern corresponding to X writes which correspond to two writes in this example. That is, bit pattern high-low-low in latches A, B and C indicated by (c) in
Further, if the write target memory cell is a memory cell in which “3” is written, the bit pattern in each of latches A, B and C is changed to a bit pattern corresponding to Y writes which correspond to four writes in this example. That is, bit pattern high-low-high in latches A, B and C indicated by (c) in
Then, the control returns to step S3 to repeat the operations in step S3 and the subsequent steps. If verification succeeds in step S6, a calculation that subtracts one from each of the numbers of writes set in the latches, i.e., one to four in step S5 is performed. That is, an operation of changing the remaining number of writes N (N=1, 2, 3, 4) to a remaining number of writes N−1 is performed. Thereafter, the control returns to step S3 to repeat the operations in steps S3 to S5.
Further, when two writes are terminated with respect to the memory cell in which “2” is written and four writes are terminated with respect to the memory cell in which “3” is written, the bit pattern in latches A, B and C is changed to all-high to complete the writing. The above-described writing is executed with respect to all the write target memory cells, whereby writing is completed.
Feature (a) of
When changing the bit pattern in the latch in step S6, the arithmetic circuit 24 provided between the sense amplifier 25 and the latches 21, 22 and 23 is utilized. High-low-low is stored in latches A, B and C corresponding to the memory cells in which “2” is written, respectively, as indicated by (c) in
Likewise, high-low-high is stored in latches A, B and C corresponding to memory cells in which “3” is written as indicated by (c) in
As described above, in the first embodiment, when changing write data in the plurality of latches to a number of writes, since just changing the data in one latch can suffice, the data transfer operations for the latches can be reduced, and the time required for setting the number of writes can be decreased. As a result, the write time can be decreased.
It should noted that, in the rough writing depicted in
In the second embodiment, if the write target memory cell is a memory cell in which “2” or “3” is written after reaching the threshold voltage “1” in step S6 in
In the second embodiment, one latch in three latches storing the numbers of writes can be opened, and the next write data can be stored in the opened latch. To open one of the latches, bit patterns corresponding to the numbers of writes must be created by using the remaining two latches. Therefore, the two latches can store four types of bit patterns alone, i.e., the end of writing and the remaining one, two and three writes.
After successfully confirming whether a write target memory cell has reached a threshold voltage “1”, a total of five bit patterns, i.e., the end of writing and the remaining one to four writes are required as bit patterns in the latches. However, when writing is performed once, the number of required bit patterns is a total of four, i.e., the end of writing and the remaining one to three writes, and hence the two latches can suffice. Therefore, one latch can be opened.
A write operation in the second embodiment will now be described with reference to
As shown in the drawing, operations from the beginning to step S6 are equal to those in the first embodiment. When a write target memory cell has reached the threshold voltage “1”, the bit pattern in latches A, B and C is changed to all-high to terminate writing if the write target memory cell is a memory cell in which “1” is written.
Furthermore, when the write target memory cell is a memory cell in which “2” is written, the bit patterns in the latches are written X times, and they are changed to bit patterns corresponding to two writes. That is, the bit pattern in latches A, B and C is changed to all-low.
Moreover, when the write target memory cell is a memory cell in which “3” is written, the bit pattern in the latches are changed to bit patterns corresponding to Y writes which correspond to four writes in this example. That is, the bit pattern in latches A, B and C is changed to low-low-high.
Thereafter, the control returns to step S3 to effect the operation in step S3 and then advances to step S4 where writing (a program) is performed with respect to the memory cell. At this step S4, if verification has been successful in step S6, the data in latch A 21, latch B 22 and latch C 23 is not confirmed, and a circuit that counts the number of write loops starts to operate. Thereafter, control jumps to step S7.
In step S7, a calculation of subtracting one from the number of writes, i.e., each of one to three set with respect to latch A 21, latch B 22 and latch C 23 is executed. That is, the bit pattern indicated by (b) in
Subsequently, if latch B 22 and latch C 23 are both high, an arithmetic circuit 24 determines that the writing is completed and transfers non-write data to a sense amplifier 25. On the other hand, if latch B 22 or latch C 23 is low, the arithmetic circuit 24 transfers the write data to the sense amplifier 25 (step S8).
Then, the control advances to step S9 where the writing (a program) is effected with respect to the memory cell. Subsequently, a calculation of subtracting one from each of the numbers of writes, i.e., one and two set with respect to latch B 22 and latch C 23 is performed.
Additionally, when the number of loops has reached four, writing is terminated. At this time, latch A has the next write data, latch B can be low or high, and latch C is high. Latch B is low only when the cell whose data indicative of the remaining number of writes is four is latched at a stage where verification has succeeded.
Further, as described above, since the writing is effected only when each of latches B and C is low, latch A is no longer necessary and can be opened. Furthermore, since the number of writes is used for recognizing the end of writing, the change of the bit patterns from the remaining three writes to the remaining two writes is no longer required, and the number of subsequent data transfer operations in the latches can be reduced to two in accordance with each loop.
As described above, in the embodiment, optimization of the data transfer operations, i.e., a reduction in the number of data transfer operations can be achieved based on setting bit patterns in the latches and changing the bit patterns, and optimizing an opening timing for each latch enables decreasing a write time.
Moreover, according to the embodiment, in the method of verification at a threshold voltage of one value in the rough writing of a four-value product of the NAND flash memory in which one memory cell can store four values and then setting the remaining number of writes associated with a write level with respect to a memory cell that has exceeded this threshold voltage, the relationship between the remaining number of writes and bit patterns in the latches is optimized to open a data cache (the latch), and unnecessary data transfer is reduced. Additionally, in a cache operation of storing the next write data in an opened data cache, a timing for opening the data cache is optimized, and an unnecessary detection or data transfer operation is omitted by changing determination of the end of writing after opening the data cache from the number of write loops from confirmation of the bit patterns. As a result, the write time in the NAND flash memory can be reduced.
In the embodiment, it is possible to provide the nonvolatile semiconductor memory device that can reduce the number of data transfer operations performed to set or change the write data or the number of writes stored in each latch and can decrease the write time by optimizing the opening timing of each latch.
It should be noted that the respective foregoing embodiments can be not only solely performed but can be appropriately combined to be performed.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-136338 | Jun 2009 | JP | national |
