Patent Application
20060170444
The present claimed invention relates to the field of semiconductor device fabrication and processing. More particularly, the present claimed invention relates to a method and apparatus for failure analysis of integrated circuits.
Photoemission microscopy (PEM) has been widely used in modern integrated circuit (IC) failure analysis. Due to physical limitations of the camera/detector of a conventional PEM system, such prior art systems normally only detect optical emissions with wavelengths ranging approximately from visible to near infrared. Therefore, conventional PEM systems are more sensitive to non-heat-related integrated circuit failures such as, for example, junction related defects, gate oxide related defects, etc.
As a complimentary technique, infrared photoemission microscopy (IRPEM) was developed by different companies and/or failure analysis laboratories to deal with heat-related defect isolation. However, the spatial resolution of IRPEM is limited by the wavelength of the infrared light IRPEM uses. More specifically, because the infrared array of a conventional IRPEM system has a 1.5 micron to 12 micron spectral response, the spatial resolution for long wavelengths is poor. Such a limitation is especially disadvantageous as the critical dimensions of integrated circuit (IC) features shrink toward to 1 micron and smaller.
In yet another prior art approach, liquid crystal (LC) analysis has been employed as an economical failure analysis technique. LC analysis has been used with great success for hot spot detection during IC failure analysis since the 1980's. However, due to its binary thermal response, LC analysis does not provide crucial information related to the thermal distribution generated by the defect. Moreover, the thermal sensitivity of LC analysis is also limited by the reduction in device operating voltage associated with deep submicron technology ICs.
Due to the respective limitations (e.g. insufficient spatial and thermal resolution) of various prior art systems, IC failure analysis is sometimes performed using multiple separate conventional systems. As an example, failure analysis is first performed on an IC using a conventional PEM system in order to detect a non-heat-related IC failure such as, for example, a junction related defect, a gate oxide related defect, etc. Next, the same IC is then subjected to further failure analysis using a conventional LC analysis system to scan, for example, for hot spots. The use of multiple discrete systems (e.g. at least two separate failure analysis systems) has significant disadvantages including inconvenience, substantial cost, reduced throughput, and the like, associated therewith.
Thus, a need exists for a method and apparatus for performing failure analysis on an integrated circuit with submicron critical dimensions more efficiently. A further need exists for a method and apparatus which meet the above need and which can perform failure analysis for both heat-related and non-heat-related defects on an integrated circuit without requiring the use of multiple separate failure analysis systems. Still another need exists for a method and apparatus for performing failure analysis on an integrated circuit wherein the method and apparatus meet the above needs and do not result in the reduced throughput and accuracy associated with prior art approaches employing multiple separate conventional failure analysis systems.
The present invention provides a method and apparatus for performing failure analysis on an integrated circuit with submicron critical dimensions more efficiently. The present invention also provides a method and apparatus which achieve the above accomplishment and which can perform failure analysis for both heat-related and non-heat-related defects on an integrated circuit without requiring the use of multiple separate failure analysis systems. The present invention further provides a method and apparatus for performing failure analysis on an integrated circuit wherein the method and apparatus achieve the above accomplishments and do not result in the reduced throughput and accuracy associated with prior art approaches employing multiple separate conventional failure analysis systems.
In one embodiment, the present invention is an apparatus comprising a first portion for detecting non-heat-related integrated circuit defects. In this embodiment, the present invention further comprises a second portion for detecting heat-related integrated circuit defects. In the present embodiment, the second portion is integrated with the first portion to provide a single integrated fault detection apparatus such that the heat-related and the non-heat-related integrated circuit defects are detectable using only a single integrated fault detection apparatus without sacrificing the accuracy of each portion comparing the separate approaches.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrates embodiments of the invention and, together with the description, serve to explain the principles of the invention:
The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
With reference now to
Physical Structure of the Present FPEM System
The present FPEM system 100 is well suited for submicron and deep submicron ULSI (Ultra Large Structure Integrated Circuit) and VLSI (Very Large Structure Integrated Circuit) failure analysis. Unlike conventional approaches which employ multiple systems such as, for example, a PEM system to detect non-heat-related defects and a separate LC system or IRPEM system to detect heat-related defects independently, the present FPEM system 100 is able to perform multiple kinds of fault isolations (e.g. heat-related and non-heat-related) for failure analysis with one common hardware setup. Hence, the present FPEM system 100 eliminates the need for multiple separate failure analysis systems. Hence, the present FPEM system 100 does not suffer from the reduced throughput associated with prior art approaches employing multiple separate conventional failure analysis systems.
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In Operation
In this system, the principle and method of PEM is used to analyze non-heat related failures/defects. For the heat-related defeats, the present FPEM system 100 uses a chemical film which is applied to sample 104 to detect the heat related defect using a fluorescent microthermal imaging technique. In one embodiment, the chemical film is a mixture of EuTTA, PMMA (polymethylmethacrylate) and MEK (methylethylketone). When subjected to UV light excitation from UV source 108 (as regulated by UV shutter 114 and source switch 112, and as filtered by IR filter 116 and excitation filter 118), the chemical film converts the heat generated by the defects on sample 104 to the fluorescent light of a peak at about 612 nanometers. In the present embodiment, the UV light is direct towards sample 104 by dichroic beam splitter 105. This kind of film is transparent inherently and is coated onto the surface of sample 104 using a photoresist spinner. A thinner and more uniform layer typically generates better results. As photoemission can penetrate such a transparent film without attenuation, it is suggested that sample 104 be coated with film before analysis is both isolation are performed. It is noted that attention should be paid to overdrive a bit in order to achieve reliable contact between probe tips and bondpads during probing on wafer level sample.
With reference still to
More specifically, during operation of the present FPEM system 100, both PEM and FMI processes are employed in a single integrated system (i.e. FPEM system 100) to detect both heat-related and non-heat-related defects. As mentioned above, during operation, UV source 108 is used for fluorescent excitation. Computer 130 in conjunction with motor controller 128 and camera controller 126 controls the movements of thermal chuck stage 101 and also optical microscope 120, respectively. That is, during PEM mode, source switch 112 blocks the UV light from UV source 108 (e.g. prevents transmission thereof) and allows the visible light from visible source 110 to pass therethrough for normal imaging. Both interference filter 122 and excitation filter 118 are pulled out for normal visible light imaging such an ensure the full range of optical emissions reach CCD camera 124. Furthermore, during the PEM mode, dichroic beam splitter 105 is replaced by a normal optical mirror (not shown) to reflect the visible light from visible source 110 onto sample 104 (for normal imaging), and to also allow the photoemission to pass through and reach CCD camera 124 (for photoemission detection).
Continuing with the discussion of the operation of FPEM system 100, during the FMI mode, visible light source 110 is utilized to get the normal image for overlay purpose. After obtaining the image for overlay purposes, the present embodiment, adjusts source switch 112 such that it passes only UV light and blocks visible light. When in FMI mode, FPEM system 100 inserts IR filter 116, excitation filter 118, interference filter 122, and dichroic beam splitter 105 into the optical path to ensure that sufficient UV excitation and to ensure that only the fluorescence of 612 nanometers reaches CCD camera 124. More specifically, IR filter 116 is used to block heat from UV source 108. Excitation filter 118 allows only UV light (cut off at 390 nanometers) to pass through. Interference filter 122 is used to ensure that CCD camera 124 receives only the fluorescent light of approximately 612 nanometer wavelength. As to dichroic beam splitter 105, it reflects as much UV light as possible onto the surface of sample 104 and meanwhile allows as much fluorescence as is possible to be transmitted to CCD camera 124. Furthermore, during FMI mode, UV shutter 114 of FPEM system 100 is synchronized with the shutter (not shown) of CCD camera 124 to avoid extended exposure of the fluorescent film (not shown) of sample 104 to UV light. As a result, FPEM system 100 of the present embodiment prevents potential film “bleaching”.
Referring still to the operation of FPEM system 100, the final photoemission and/or fluorescent microthermal images are processed by computer 130 and are then available to be displayed on monitor 132 in real time. After such images are obtained, those images can then be overlaid onto a normal optical image for defect localization. Additionally, FPEM system 100 allows all of the images to be saved into, for example, the hard disk (not shown) of computer 130 or onto various other storage media in any of various formats. Also, in FPEM system 100, temperature controller 102 is used to maintain sample 104, via thermal chuck stage 101, at a desired temperature. In one embodiment, FPEM system 100 includes electrical test instrument 106 which is used to bias sample 104 (device) electrically upon the applicable bench test setup. This is to analyze the device at its failing condition.
With reference now to
At step 204, the present embodiment analyzes the sample for non-heat-related defects using a PEM processing method employed by single integrated FPEM system 100 of
At step 206, the present embodiment analyzes the sample for heat-related defects using an FMI processing method employed by single integrated FPEM system 100 of
Thus, the present invention provides a method and apparatus for performing failure analysis on an integrated circuit with submicron critical dimensions more efficiently. The present invention also provides a method and apparatus which achieve the above accomplishment and which can perform failure analysis for both heat-related and non-heat-related defects on an integrated circuit without requiring the use of multiple separate failure analysis systems. The present invention further provides a method and apparatus for performing failure analysis on an integrated circuit wherein the method and apparatus achieve the above accomplishments and do not result in the reduced throughput and accuracy associated with prior art approaches employing multiple separate conventional failure analysis systems.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.
