Patent Application
20050170625
(1) Field of the Invention
The present invention teaches a method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation.
(2) Description of Related Art
Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 6,603,204 B2 Patent entitled “Low-K Interconnect Structure Comprised of a Multilayer of Spin-On Porous Dielectrics” granted Aug. 5, 2003 to Gates et al. describes a two layer hard mask structure, but lacks processing details for forming a low-k dielectric metal conductor interconnect structure having no micro-trenches present therein. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions.
U.S. Pat. No. 6,309,962 B1 Patent entitled “Film Stack and Etching Sequence for Dual Damascene” granted Oct. 30, 2001 to Chen et al. teaches that two or three layers of hard mask are not needed in this process using an etch stop layer. A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.
U.S. Pat. No. 6,605,874 B2 Patent entitled “Method of Making Semiconductor Device Using an Interconnect” granted Aug. 12, 2003 to Leu et al. discloses a multiple hard mask layer process with no etch stop layer. The invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
U.S. Pat. No. 6,472,306 B1 Patent entitled “Method of Forming a Dual Damascene Opening Using CVD Low-K Material and Spin-On-Polymer” granted Oct. 29, 2002 to Lee et al. describes a single hard mask layer and no etch stop layer. Specifically, a method of forming a dual damascene opening, consisting of the following steps: a semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.
The present invention teaches a method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. A via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. A via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. A key point, is that the dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without severe fencing or faceting. The present invention solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
The solution to the above processing problems is the following list of two component hard masks, termed bi-layer hard masks. Processing details of the trench etch are as follows. The film stack is comprised of a bi-layer hard mask termed, Top HM1, Bottom HM2, and IMD. The combination of HM1/HM2/IMD stack, inter-metal dielectric consists of, which can be any one of these schemes:
The etch considerations for the above bi-layer hard mask are as following:
The final etch process is comprised of a 1:1 selectivity etch chemistry for HM2 and IMD film, intermetal dielectric, can be used since HM2, bottom hard mask layer etch properties are not much different from the IMD film. This 1:1 selectivity chemistry can be used for etching HM2, as well as, the IMD film.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.
The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include:
FIGS. 1A-B, which in cross-sectional representation, illustrates Prior Art methods, as background to the present invention, forming a defective dual damascene structure of via and trench over a copper interconnect.
FIGS. 2A-F, which illustrated in cross-sectional drawing, are the key process steps for forming a dual damascene structure of via and trench over a copper interconnect, using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, forming metal contacts and interconnect wiring.
The present invention describes a method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Defining a “via first” pattern in dual damascene processing, is one of the major integration schemes for copper backend of line (BEOL) integration. A via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. A key point is that the dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without severe fencing or faceting. The present invention solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
The solution to the above processing problems is the following list of two component hard masks, termed bi-layer hard masks. The film stack is comprised of a bi-layer hard mask termed, Top HM1, Bottom HM2, and IMD. The combination of HM1/HM2/IMD stack, inter-metal dielectric consists of, which can be any one of these schemes:
The etch considerations for the above bi-layer hard masks are as following:
The final etch process is comprised of a 1:1 selectivity etch chemistry for HM2 and IMD film, intermetal dielectric, can be used since HM2, bottom hard mask layer etch properties are not much different from the IMD film. This 1:1 selectivity chemistry can be used for etching HM2, as well as, the IMD film.
Referring to
Referring to
Referring to FIGS. 2A-F which illustrated in cross-sectional drawing, are the key process steps for forming a dual damascene structure of via and trench over a copper interconnect, using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, forming metal contacts and interconnect wiring. The processing is similar to conventional dual damascene build with the key exception that a two component hard mask is used. In
Processing details of the trench etch are as follows. The film stack is comprised of a bi-layer hard mask termed, Top HM1, Bottom HM2, and IMD. The combination of HM1/HM2/IMD stack, inter-metal dielectric consists of, which can be any one of these schemes:
(Note: where USG, undoped silicate glass for HM1 layer, hard mask top layer, also can be a conventional Si02 film of thickness in the range from 1000 to 2000 Angstroms)
Referring to FIGS. 2B-D which illustrated in cross-sectional drawing, are the profiles after different trench etch steps. In
The etch considerations for the above bi-layer hard masks are as following:
The HM1 layer, hard mask top layer, can be a conventional SiO2 film of thickness in the range from 1000 to 2000 Angstroms, and HM2, hard mask bottom layer, is a selective dielectric layer (Selectivity of ˜3-5) for HM1 etch, with etch stop on HM2. The HM2 can be very thin, between approximately 300 to 600 Angstroms. The advantage of this bi-layer hard mask is to reduce etch defects and trench depth non-uniformity. Both hard mask layers, HM1 and HM2, can be removed by the subsequent copper chemical mechanical polish if necessary. The IMD, inter-metal dielectric, film thickness is in a range approximately from 0.2 to 2 microns.
More details on various etch approaches are the following:
Selective BARC opening Etch to stop on HM1 (3-5x Selectivity)—With the appropriate chemistry selection, etch front stops on HM1 layer among different structures across the whole wafer.
Selective HM1 Etch to stop on HM2
With the appropriate chemistry selection, etch front stops on HM2 layer among different structures across the whole wafer. Because of selective HM2 layer, trench depth as well as corner chopping is well controlled after this step.
Another etch approach is to process and etch the via-fill material, so as to recess this material, to minimize fence or sub-trench profiles. The timing of this step is adjusted to coincide with different Hard Mask etch and IMD etch chemistries. As this step uses photoresist strip gases, which have good selectivity to the bulk material, it only recesses the BARC inside the via, with minimum impact on the trench profile. After this step, BARC height inside the via recesses to about the same level of trench etch front. However, note that an accurate control of this step is critical. If this etch step is not sufficient, fencing will result, and if this etch step too much, sub-trenching will occur.
Key to the etch process is to utilize a 1:1 selectivity chemistry for the HM2, bottom hard mask, and IMD, inter-metal dielectric, film. Since the chemical properties of the HM2 materials are not much different from IMD film, a 1:1 selectivity chemistry can be used for etching HM2, as well as, for the IMD film. With this above methods, no fences or sub-trenches were observed in dense Trench & Via, Isolated Trench & Via, Open trench & dense via patterns.
For completeness, the following is a detailed reactive ion etch, RIE, processing scheme for trench etch making use of the advantages of the bi-layer hard mask. This serves as just one example that was developed and reduced to practice, for RIE gas mixtures:
Referring to FIGS. 2E-F, which illustrated in cross-sectional drawings, are the final processing steps in building of the dual damascene structure. In
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
