NROM NON-VOLATILE MODE OF OPERATION

Abstract

Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using a combination of only HHI, followed by CHE without any Erase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will be made in detail to embodiments of the disclosure, examples of which may be illustrated in the accompanying drawing figures. The figures are intended to be illustrative, not limiting. Although the disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the disclosure to these particular embodiments.

Certain elements in selected ones of the figures may be illustrated not-to-scale, for illustrative clarity. The cross-sectional views, if any, presented herein may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a true cross-sectional view, for illustrative clarity.

Elements of the figures may (or may not) be numbered as follows. The most significant digits (hundreds) of the reference number correspond to the figure number. For example, elements of FIG. 1 are typically numbered in the range of 100-199, and elements of FIG. 2 are typically numbered in the range of 200-299. Similar elements throughout the figures may be referred to by similar reference numerals. For example, the element 199 in FIG. 1 may be similar (and possibly identical) to the element 299 in FIG. 2. Throughout the figures, each of a plurality of elements 199 may be referred to individually as 199a, 199b, 199c, etc. Such relationships, if any, between similar elements in the same or different figures will become apparent throughout the specification, including, if applicable, in the claims and abstract.

FIG. 1 is a stylized cross-sectional view of a field effect transistor (FET), according to the prior art. To the left of the figure is a schematic symbol for the FET.

FIG. 2 is a stylized cross-sectional view of a floating gate memory cell, according to the prior art. To the left of the figure is a schematic symbol for the floating gate memory cell.

FIGS. 2A and 2B are diagrams illustrating programming and erase mechanisms for a floating gate memory cell, according to the prior art.

FIG. 3 is a stylized cross-sectional view of a two bit NROM memory cell of the prior art. To the left of the figure is a schematic symbol for the NROM memory cell.

FIGS. 3A-3D are diagrams illustrating programming and erase mechanisms for a NROM memory cell, according to the prior art.

FIGS. 3E-3G are diagrams illustrating programming and erase mechanisms for a NROM memory cell, according to the prior art.

FIG. 4 is a diagram of a memory cell array with NROM memory cells, according to the prior art.

FIGS. 5A-5D are diagrams illustrating a mode of operation, according to this disclosure.

FIGS. 6A-6B are diagrams illustrating another mode of operation, according to this disclosure.

Claims

1. A method for operating a plurality of NVM memory cells comprising: performing a first programming step using hot hole injection (HHI) to reduce the threshold voltage (Vt) of selected ones of the memory cells; andperforming a second programming step using channel hot electron (CHE) injection to increase the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in first programming step.

2. The method of claim 1, wherein the NVM cells are NROM cells.

3. The method of claim 1, wherein: each memory cell has two charge-trapping areas; andeach charge-trapping area of a memory cell is capable of storing at least one bit.

4. The method of claim 1, wherein, for operating on a given bit of an NROM cell comprising a first (source) terminal, a gate, and a second (drain) terminal: in the first programming step: the first terminal is set to approximately 2 volts;the gate is set to approximately −8 volts;the second terminal is set to approximately 4 volts;in the second programming step: the first terminal is set to ground (0 v).the gate is set to approximately 9.5 volts; andthe second terminal is set to approximately 4.5 volts.

5. The method of claim 4, wherein, in all of the three (erase, first programming, second programming) steps: a substrate voltage (Vb) is maintained at 0 volts (0 v).

6. The method of claim 1, wherein: the HHI programming step is performed using pulses, separated by reads; andthe CHE programming step is performed with pulses, separated by reads.

7. The method of claim 1, wherein: the plurality of memory cells comprise a sector; andthe sector size is 128 kilobytes (KB) to 1 megabyte (MB).

8. A method for programming a plurality of memory cells, each cell having a characteristic program voltage (PV) and a characteristic erase voltage (EV), the method comprising the steps of: (a) programming first selected ones of the cells by decreasing the threshold voltage of the first selected ones of the cells to less than the program voltage (Vt<PV); and(b) refreshing second selected ones of the cells by increasing the threshold voltage (Vt) of the cells to greater than the erase voltage (Vt>EV).

9. The method of claim 7, wherein: the step (a) is performed using Hot Hole Injection (HHI); andthe step (b) is performed using Channel Hot Electron (CHE) injection.

10. A method of programming a NVM memory cell comprising: using a combination of hot hole injection (HHI), followed by channel hot electron (CHE).

11. The method of claim 10, wherein: the memory cell is an NROM memory cell.

12. The method of claim 10, wherein: the memory cell has two charge-trapping areas; andeach charge-trapping area is capable of storing at least one bit.

13. The method of claim 10, wherein: the method comprises comprise Page Write only with HHI and CHE for programming, without any erase.