Filters are commonly used in electronic systems such as signal processing and data processing circuits to remove noise from a data signal. A digital finite impulse response (DFIR) filter applies a mathematical operation to a digital data stream to achieve any of a wide range of desired frequency responses. As illustrated in
In a data processing circuit, an analog to digital converter (ADC) is often used upstream of a DFIR filter to convert an analog signal to a digital signal that may be filtered in the DFIR filter and otherwise processed in other circuits. The sampling phase of the ADC may be selected or varied to meet any of a number of objectives in the data processing circuit, for example to minimize bit errors. However, DFIR filters may be sensitive to the selection of the ADC sampling phase, yielding various frequency responses to different ADC sampling phases. Adjusting the ADC sampling phase based on the frequency response of the DFIR filter may further complicate the meeting of other objectives of the data processing circuit related to the ADC sampling phase, as well as being time consuming.
Thus, for at least the aforementioned reason, there exists a need in the art for reducing DFIR filter sensitivity to ADC sampling phase.
Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range. In some cases, the Nyquist response is calculated as the sum of the tap weights for the even taps minus the tap weights for the odd taps.
In some cases, the tap weight controller is operable to calculate a tap weight offset to adjust the tap weight for each of the subset of the plurality of taps, whether the subset includes all taps for the digital finite impulse response filter or excludes some taps, such as the tap with the largest tap weight. In various cases, when the magnitude of the Nyquist response is less than a lower boundary of the range, the tap weight offset is calculated as the sign of the Nyquist response multiplied by a difference between the lower boundary of the range and the Nyquist response, divided by a number of taps in the subset of the plurality of taps, and when the magnitude of the Nyquist response is greater than an upper boundary of the range, the tap weight offset is calculated as the sign of the Nyquist response multiplied by a difference between the upper boundary of the range and the Nyquist response, divided by the number of taps in the subset of the plurality of taps. In some cases, the tap weight offset is added to the tap weight of even taps and subtracted from the tap weight of odd taps.
In some instances of the aforementioned embodiments, the apparatus includes an analog to digital converter with a variable sampling phase connected to an input of the digital finite impulse response filter. The frequency response sensitivity of the digital finite impulse response filter to the variable sampling phase of the analog to digital converter is reduced by adjusting the tap weights.
Other embodiments of the present invention provide methods for filtering a signal. The methods include providing a digital finite impulse response filter having a plurality of tap weight inputs and a tap weight controller connected to the digital finite impulse response filter. The methods also include using the tap weight controller to calculate the Nyquist response of the digital finite impulse response filter based on at least some of the plurality of tap weight inputs, determining whether the magnitude of the Nyquist response of the digital finite impulse response filter is outside of a Nyquist constraint range, and if so, calculating a tap weight offset and applying the tap weight offset to the at least some of the tap weight inputs.
This summary provides only a general outline of some embodiments according to the present invention. Many other objects, features, advantages and other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals may be used throughout several drawings to refer to similar components.
Various embodiments of the present invention are related to apparatuses and methods for filtering a digital signal, and more particularly to a Nyquist constrained DFIR filter. Various embodiments of the present invention constrain the magnitude of the Nyquist response of a DFIR filter to remain within a Nyquist constraint range. When the magnitude of the Nyquist response remains within the range, the sensitivity of the DFIR filter to an upstream ADC sampling phase is greatly reduced. The Nyquist response and the magnitude of the Nyquist response of the DFIR filter at time k are represented by S and by |S|, respectively, and are defined herein by Equations 1 and 2:
where S is the sum of the even tap weights minus the odd tap weights and |S| is the absolute value of S, where f2i,k represents the even tap weights (e.g., 112, 116) and f2i+1,k represents the odd tap weights (e.g., 114, 120). The tap weights may originally be determined in any suitable manner to set the filtering characteristics of the DFIR filter, whether now known or developed in the future. For example, a DFIR adaptation process may be used in a data processing circuit during which known inputs are provided while adjusting the tap weights to achieve the desired filtered output corresponding to the known inputs, either using calculations, searching algorithms or any other technique to find the tap weights that yield the desired filtering characteristics. In some embodiments, the tap weights may be calculated by determining the desired frequency response that stops unwanted frequencies and passes the wanted frequencies, then calculating the inverse Fourier transform of the desired frequency response, and using the results as the tap weights.
The magnitude of the Nyquist response for the resulting tap weights is then checked to ensure that it falls within the desired range, and if not, they are adjusted as will be disclosed in more detail below. By ensuring that the magnitude of the Nyquist response remains within the range, the sensitivity of the DFIR filter to the sampling phase of an upstream ADC is considerably reduced. This renders the data processing circuit more stable and robust and precludes time consuming adjustments to the ADC sampling phase to maintain the desired DFIR filter frequency response.
Turning to
The Nyquist constraint applied to the tap weights 216 is given by Equation 3:
Each time new tap weights are calculated for the DFIR filter 206, for example during or after DFIR adaptation iterations in a data processing circuit, the Nyquist constraint controller 212 again processes the initial tap weights to determine whether the associated Nyquist response magnitude |S| given by Equation 2 falls within a particular range. If not, the Nyquist constraint controller 212 applies the Nyquist constraint to them to move them into the range, before the resulting tap weights 216 are provided to the DFIR filter 206. The Nyquist constraint is applied by calculating a tap weight offset A that adjusts the initial tap weights if the associated Nyquist response magnitude |S| would otherwise fall outside the range as indicated by Equation 3. The tap weight offset Δ is calculated in some embodiments according to Equation 4:
The tap weight offset Δ is applied in some embodiments according to Equations 5 and 6:
f2i,k=f2i,k+Δ
Equation 5
f2i+i,k=f2i+1,k−Δ
Equation 6
The tap weight offset Δ is added to each even tap and is subtracted from each odd tap. If L is even, the number of even taps and odd taps is the same, so the even and odd taps will receive a balanced offset due to the tap weight offset Δ. If L is odd, there will either be more even taps or odd taps, and the tap weight offset Δ will therefore be applied to more of either the even taps or odd taps. If the DFIR filter 206 is adapted to use integer tap weights, the Nyquist constrained tap weights may be rounded, truncated or otherwise converted to integers from floating point numbers if the application of the tap weight offset Δ results in floating point numbers.
As an example illustration using arbitrary numbers, given a FIR filter with four taps as in
Turning to
The read channel circuit 300 may be used, for example, to process data from a storage system or wireless communication system. Read channel circuit 300 includes an analog to digital converter (ADC) 302 that converts the analog input signal 304 into a series of digital samples that are provided to DFIR filter 306. DFIR filter 306 acts as an equalizer on the digital samples from the ADC 302, compensating for inter-symbol interference (ISI) resulting from data being transmitted at high speed through band-limited channels and filtering the received input to provide a corresponding filtered output 310 to a detector circuit 312, such as a Viterbi decoder. Detector circuit 312 performs a data detection process on the received input resulting in a detected output 314. In performing the detection process, detector circuit 312 attempts to correct any errors in the received data input.
Detected output 314 is provided to a partial response (PR) target circuit 316 that is operable to convolve the detected output 314 with a partial response target 320 to create a partial response output 322 as the derivative of the detected output 314. An error generator 324 generates an error signal 326 based at least in part on the partial response output 322. The error signal 326 is used by a tap adaptation circuit 330 to adjust the tap weights provided to the DFIR filter 306. Other inputs may also be used by the tap adaptation circuit 330 to adjust tap weights, such as a tap adaptation signal 332 from the ADC 302 to provide information to the tap adaptation circuit 330 during tap adaptation processes. In some embodiments, tap values are initially calculated, for example during an adaptation iteration based on the tap adaptation signal 332, and are then adjusted during run time in the tap adaptation circuit 330 based on quantities such as the error signal 326.
A Nyquist constraint controller 340 reads the tap weights 342 applied to the DFIR filter 306 by the tap adaptation circuit 330, determining whether Nyquist response magnitude |S| established by tap weights 342 falls outside the range as indicated by Equation 3. A Nyq_low signal 344 and Nyq_high signal 436 may be provided to the Nyquist constraint controller 340 as external parameters to establish and variably control the range of Equation 3. In other embodiments, the values for Nyq_low and Nyq_high may be fixed in the design of the Nyquist constraint controller 340. If Nyquist constraint controller 340 determines that Nyquist response magnitude |S| falls outside the range in Equation 3, a tap weight offset Δ 350 is provided by the Nyquist constraint controller 340 to the tap adaptation circuit 330 to constrain the tap weights 342. With the tap weights 342 constrained by the Nyquist constraint controller 340 to remain within the range established in Equation 3, the DFIR filter 306 is less sensitive to the sampling phase of the ADC 302.
Turning to
The resulting frequency responses in a DFIR filter (e.g., 206 and 306) for these ADC sampling phases 402 are illustrated in
Notably, while at first glance it appears there may be some correlation between a low bit error rate 400 and flat frequency response 424, the selection of an ADC sampling phase 402 that yields a relatively low bit error rate 400 does not necessarily result in a flat frequency response 424. For example, selecting ADC sampling phase 0 420 yields a bit error rate 422 that is relatively close to the best available bit error rate 406 at sampling phase −0.3 404, and substantially better than the bit error rate 412 at sampling phase 0.4 410, and yet the suppressed frequency response 434 produced by ADC sampling phase 0 420 is much worse than that 436 produced by ADC sampling phase 0.4 410. Thus, although it may appear that there is some correlation between ADC sampling phases that yield the best bit error rate and those that provide the best Nyquist response in the DFIR filter (e.g., 206 and 306), there is no guarantee that an ADC sampling phase will not be selected based on various selection criteria that will result in a suppressed Nyquist response in the DFIR filter (e.g., 206 and 306) given the sensitivity of the
DFIR filter (e.g., 206 and 306) to the ADC sampling phase when the Nyquist constraint on the tap weights is disabled or otherwise not used.
Turning to
Turning to
Turning to
Turning to
In a typical read operation, read/write head assembly 720 is accurately positioned by motor controller 712 over a desired data track on disk platter 716. Motor controller 712 both positions read/write head assembly 720 in relation to disk platter 716 and drives spindle motor 714 by moving read/write head assembly 720 to the proper data track on disk platter 716 under the direction of hard disk controller 710. Spindle motor 714 spins disk platter 716 at a determined spin rate (RPMs). Once read/write head assembly 720 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 716 are sensed by read/write head assembly 720 as disk platter 716 is rotated by spindle motor 714. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 716. This minute analog signal is transferred from read/write head assembly 720 to read channel circuit 702 via preamplifier 704. Preamplifier 704 is operable to amplify the minute analog signals accessed from disk platter 716. In turn, read channel circuit 702 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 716. This data is provided as read data 722 to a receiving circuit. As part of decoding the received information, read channel circuit 702 processes the received signal using a Nyquist constrained DFIR filter. Such a Nyquist constrained DFIR filter may be implemented consistent with that disclosed above in relation to
It should be noted that storage system 700 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system 700 may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.
Turning to
It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit.
It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
In conclusion, the present invention provides novel apparatuses and methods for a Nyquist constrained DFIR filter. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5278703 | Rub et al. | Jan 1994 | A |
5278846 | Okayama | Jan 1994 | A |
5317472 | Schweitzer, III | May 1994 | A |
5325402 | Ushirokawa | Jun 1994 | A |
5353306 | Yamamoto | Oct 1994 | A |
5392299 | Rhines | Feb 1995 | A |
5417500 | Martinie | May 1995 | A |
5513192 | Janku | Apr 1996 | A |
5523903 | Hetzler | Jun 1996 | A |
5550810 | Monogioudis et al. | Aug 1996 | A |
5550870 | Blaker | Aug 1996 | A |
5612964 | Haraszti | Mar 1997 | A |
5710784 | Kindred | Jan 1998 | A |
5717706 | Ikeda | Feb 1998 | A |
5802118 | Bliss | Sep 1998 | A |
5805241 | Limberg | Sep 1998 | A |
5844945 | Nam | Dec 1998 | A |
5898710 | Amrany | Apr 1999 | A |
5923713 | Hatakeyama | Jul 1999 | A |
5978414 | Nara | Nov 1999 | A |
5983383 | Wolf | Nov 1999 | A |
6005897 | McCallister | Dec 1999 | A |
6023783 | Divsalar | Feb 2000 | A |
6029264 | Kobayashi | Feb 2000 | A |
6065149 | Yamanaka | May 2000 | A |
6097764 | McCallister | Aug 2000 | A |
6145110 | Khayrallah | Nov 2000 | A |
6178056 | Cloke et al. | Jan 2001 | B1 |
6216249 | Bliss | Apr 2001 | B1 |
6216251 | McGinn | Apr 2001 | B1 |
6266795 | Wei | Jul 2001 | B1 |
6317472 | Choi | Nov 2001 | B1 |
6351832 | Wei | Feb 2002 | B1 |
6377610 | Hagenauer | Apr 2002 | B1 |
6381726 | Weng | Apr 2002 | B1 |
6473878 | Wei | Oct 2002 | B1 |
6535553 | Limberg et al. | Mar 2003 | B1 |
6625775 | Kim | Sep 2003 | B1 |
6748034 | Hattori | Jun 2004 | B2 |
6757862 | Marianetti, II | Jun 2004 | B1 |
6785863 | Blankenship | Aug 2004 | B2 |
6810502 | Eidson | Oct 2004 | B2 |
6970511 | Barnette | Nov 2005 | B1 |
6986098 | Poeppelman | Jan 2006 | B2 |
7047474 | Rhee | May 2006 | B2 |
7058873 | Song | Jun 2006 | B2 |
7073118 | Greenberg | Jul 2006 | B2 |
7093179 | Shea | Aug 2006 | B2 |
7117427 | Ophir | Oct 2006 | B2 |
7133228 | Fung | Nov 2006 | B2 |
7184486 | Wu | Feb 2007 | B1 |
7191378 | Eroz | Mar 2007 | B2 |
7203887 | Eroz | Apr 2007 | B2 |
7248630 | Modrie | Jul 2007 | B2 |
7257764 | Suzuki | Aug 2007 | B2 |
7308061 | Huang | Dec 2007 | B1 |
7310768 | Eidson | Dec 2007 | B2 |
7313750 | Feng | Dec 2007 | B1 |
7370258 | Iancu | May 2008 | B2 |
7415651 | Argon | Aug 2008 | B2 |
7421017 | Takatsu | Sep 2008 | B2 |
7502189 | Sawaguchi | Mar 2009 | B2 |
7523375 | Spencer | Apr 2009 | B2 |
7587657 | Haratsch | Sep 2009 | B2 |
7590168 | Raghavan | Sep 2009 | B2 |
7646829 | Ashley | Jan 2010 | B2 |
7702986 | Bjerke | Apr 2010 | B2 |
7705761 | Tietjen et al. | Apr 2010 | B2 |
7715471 | Werner | May 2010 | B2 |
7752523 | Chaichanavong | Jul 2010 | B1 |
7779325 | Song | Aug 2010 | B2 |
7802172 | Vila Casado | Sep 2010 | B2 |
7958425 | Chugg | Jun 2011 | B2 |
7996746 | Livshitz | Aug 2011 | B2 |
8018360 | Nayak | Sep 2011 | B2 |
8046666 | Park et al. | Oct 2011 | B2 |
8201051 | Tan | Jun 2012 | B2 |
8208213 | Liu | Jun 2012 | B2 |
8291284 | Savin | Oct 2012 | B2 |
20060123285 | De Araujo et al. | Jun 2006 | A1 |
20080069373 | Jiang | Mar 2008 | A1 |
20080304558 | Zhu et al. | Dec 2008 | A1 |
20090002862 | Park et al. | Jan 2009 | A1 |
20090132893 | Miyazaki | May 2009 | A1 |
20090185643 | Fitzpatrick | Jul 2009 | A1 |
20110072335 | Liu et al. | Mar 2011 | A1 |
20110075569 | Marrow | Mar 2011 | A1 |
20110164332 | Cao | Jul 2011 | A1 |
20110167227 | Yang et al. | Jul 2011 | A1 |
20120019946 | Aravind | Jan 2012 | A1 |
20120056612 | Mathew | Mar 2012 | A1 |
20120069891 | Zhang | Mar 2012 | A1 |
20120124119 | Yang | May 2012 | A1 |
20120236430 | Tan | Sep 2012 | A1 |
Entry |
---|
Axvig et al., “Average Min-Sum Decoding of LDPC Codes”, 5th International Symposium on Turbo Codes and Related Topics (2008). |
Bahl et al., “Optimal decoding of linear codes for minimizing symbol error rate”, IEEE Trans. Inform. Theory, vol. 20, pp. 284-287 (Mar. 1974). |
Blaum, “High-Rate Modulation Codes for Reverse Concatenation”, IEEE Transactions on Magnetics, vol. 43, No. 2 (Feb. 2007). |
Casado et al., Multiple-rate low-density parity-check codes with constant blocklength, IEEE Transations on communications, Jan. 2009, vol. 57, pp. 75-83. |
Cui et al., “High-Throughput Layered LDPC Decoding Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, No. 4 (Apr. 2009). |
Fan et al., “Constrained coding techniques for soft iterative decoders” Proc. IEEE Global Telecommun. Conf., vol. 1b, pp. 631-637 (1999). |
Fossorier, Marc P.C. “Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Maricies” IEEE Transactions on Information Theory, vol. 50, No. 8 Aug. 8, 2004. |
Gross, “Stochastic Decoding of LDPC Codes over GF(q)”, HDPCC Workshop, Tel Aviv (Mar. 2, 2010). |
Gunnam et al., “VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax”, IEEE ICC Proceedings (2007). |
Hagenauer, J. et al A Viterbi Algorithm with Soft-Decision Outputs and its Applications in Proc. IEEE Globecom, pp. 47. 11-47 Dallas, TX Nov. 1989. |
Han and Ryan, “Pinning Techniques for Low-Floor Detection/Decoding of LDPC-Coded Partial Response Channels”, 5th International Symposium on Turbo Codes &Related Topics, 2008. |
Kautz, “Fibonacci Codes for Synchronization Control”, IEEE Trans. Info. Theory, vol. 11, No. 2, pp. 284-292 (Apr. 1965). |
Kschischang et al., “Factor Graphs and the Sum-Product Algorithm”, IEEE Transactions on Information Theory, vol. 47, No. 2 (Feb. 2001). |
Leduc-Primeau et al., “A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes”, IEEE Communications Society, IEEE Globecom proceedings (2009). |
Lee et al., “Partial Zero-Forcing Adaptive MMSE Receiver for DS-CDMA Uplink in Multicell Environments” IEEE Transactions on Vehicular Tech. vol. 51, No. 5, Sep. 2002. |
Li et al “Efficient Encoding of Quasi-Cyclic Low-Density Parity Check Codes” IEEE Transactions on Communications on 53 (11) 1973-1973, 2005. |
Lim et al. “Convergence Analysis of Constrained Joint Adaptation in Recording Channels” IEEE Trans. on Signal Processing vol. 54, No. 1 Jan. 2006. |
Lin et al “An efficient VLSI Architecture for non binary LDPC decoders”—IEEE Transaction on Circuits and Systems II vol. 57, Issue 1 (Jan. 2010) pp. 51-55. |
Moon et al, “Pattern-dependent noise prediction in signal-dependent Noise,” IEEE JSAC, vol. 19, No. 4 pp. 730-743, Apr. 2001. |
Moon et al., “Maximum transition run codes for data storage systems”, IEEE Trans. Magn., vol. 32, No. 5, pp. 3992-3994 (Sep. 1996). |
Shokrollahi “LDPC Codes: An Introduction”, Digital Fountain, Inc. (Apr. 2, 2003). |
Spagnol et al, “Hardware Implementation of GF(2Λm) LDPC Decoders”, IEEE Transactions on Circuits and Systems{hacek over (s)}i: Regular Papers, vol. 56, No. 12 (Dec. 2009). |
Tehrani et al., “Fully Parallel Stochastic LDPC Decoders”, IEEE Transactions on Signal Processing, vol. 56, No. 11 (Nov. 2008). |
Todd et al., “Enforcing maximum-transition-run code constraints and low-density parity check decoding”, IEEE Trans. Magn., vol. 40, No. 6, pp. 3566-3571 (Nov. 2004). |
U.S. Appl. No. 13/239,719, Unpublished, filed Sep. 22, 2011 (Haitao Xia). |
Vasic, B., “High-Rate Girth-Eight Codes on Rectangular Integer Lattices”, IEEE Trans. Communications, vol. 52, Aug. 2004, pp. 1248-1252. |
Vasic, B., “High-Rate Low-Density Parity-Check Codes Based on Anti-Pasch Affine Geometries,” Proc ICC 2002, pp. 1332-1336. |
Weon-Cheol Lee et al., “Vitierbi Decoding Method Using Channel State Info. In COFDM System” IEEE Trans. on Consumer Elect., IEEE Service Center, NY, NY vol. 45, No. 3 Aug. 1999. |
Yeo et al., “VLSI Architecture for Iterative Decoders in Magnetic Storage Channels”, Mar. 2001, pp. 748-755, IEEE trans. Magnetics, vol. 37, No. 2. |
Zhang et al., “Analysis of Verification-Based Decoding on the q-ary Symmetric Channel for Large q”, IEEE Trans. on Information Theory, vol. 57, No. 10 (Oct. 2011). |
Zhong et al., “Design of VLSI Implementation-Oriented LDPC Codes”, IEEE, pp. 670-673, 2003. |
Zhong et al., “High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor”, ISCAS, IEEE pp. 3546-3549, May 2006. |
Zhong et al., “Joint Code-Encoder Design for LDPC Coding System VLSI Implementation”, ISCAS, IEEE pp. 389-392, May 2004. |
Zhong et al., “Quasi Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VSLI Implementation”, IEEE Transactions on Magnetics, v. 43, pp. 1118-1123, Mar. 7. |
Zhong, “Block-LDPC: A Practical LDPC Coding System Design Approach”, IEEE Trans. on Circuits, Regular Papers, vol. 5, No. 4, pp. 766-775, Apr. 2005. |
Number | Date | Country | |
---|---|---|---|
20130097213 A1 | Apr 2013 | US |