Patent Application
20120319241
The present invention relates to techniques for reducing voltage offsets that can arise in integrated circuits and, specifically, to those voltage offsets that can arise in semiconductor resistors within such integrated circuits.
In semiconductor resistors, a voltage offset is a voltage that is generated at the junction between a metal and a semiconductor material. Voltage offsets cause integrated circuits to behave in non-ideal manners. Although electrical engineers typically model a resistor according to the equation V=I*R , where V represents a driving voltage across the resistor, I represents a current passing through the resistor and R represents the resistance of the material that constitutes the resistor, in practice the resistor may behave as V=I*R+ΣVOFFi, where VOFFi represents the voltages induced by various metal-to-semiconductor junctions within the resistor. In applications requiring high precision operation, the voltage offsets cause a loss of precision.
Voltage offsets arise in other circuit systems, such as amplifiers. Various techniques to reduce voltage offsets are utilized such systems, such as chopper stabilizers and auto-zero circuits, however, such techniques are unable to combat all offset phenomena. For example, chopper stabilizers reduce offset voltages generated in amplifiers by modulating the offset voltages and suppressing them in low pass filters. Although chopper stabilizers are effective in reducing offset voltages generated in amplifiers, they are unable to reduce offset voltages generated by other circuit components. The present disclosure focuses on reducing offset voltages generated by a resistor structure that has a resistor body made of semiconductor material and terminals made of conductive material.
If there is a temperature difference between the metal tracks 110 of the poly silicon resistor 100, a voltage potential (or offset voltage) is observable. In other words, the resistor becomes a “thermocouple” in this condition. The typical value of the voltage potential generated in a metal-silicon junction is approximately 400 μV/° C. In such circumstances, a mere 0.01° C. temperature difference across poly silicon resistor 100 will generate a few μV potential difference between the metal tracks 110. Modern circuit applications often require offset to be reduced to 0.01 μV. The situation is more serious when circuits dissipate significant power which induces greater temperature differences across resistors. Therefore, a need exists for an offset reducing technique that accounts for temperature variances across resistors.
Embodiments of the present invention provide an integrated circuit structure for a resistor that minimizes offset voltages that occur at material junctions in typical semiconductor resistor circuits. The invention may include at least two resistor segments that may be interconnected via metal conductors. The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type (i.e., current flow direction type) that is spaced to form respective same junction type centroids (i.e., geometric centers). The different junction type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit.
Additionally, because the centroids of paired junctions are substantially coincident, the junction voltages are likely to vary with temperature in an equal but opposite manner. Thus, the cancellation effect should persist even when temperature varies.
The principles of the present invention may find application in any resistor structure that has a resistor body made of semiconductor material. For example, the resistor segments of the present invention may be poly silicon resistors, N-type or P-Type diffusion resistors, or N-type or P-type well resistors. The resistor segments of the embodiments are coupled with metal conductors. However, other conductive materials may be utilized instead of metal. Moreover, the resistor segments may be utilized as connection pads, for example bonding pads.
The resistor segments 210, 220 may be placed in a spatial region of an integrated circuit. As illustrated in
Each junction may be paired with a similar type (i.e., N-type or P-type) counterpart where the pair form a centroid of that junction type. Junction type may be classified based on current flow direction through the resistor segments. For example, a junction with current flow from a metal portion to resistor may be classified as a first type of junction, and another junction with current flow from resistor to metal portion may be classified as a second type of junction. Further, each junction and its pair counterpart may be spaced from the resistor centroid at a common distance. For instance, junctions TCA and TCc are arranged symmetrically with respect to the resistor centroid and may be classified as the first type of junction, JMR (Junction with metal-to-resistor current flow). Similarly, junctions TCB and TCD are arranged symmetrically with respect to the centroid and may be classified as the second type of junction, JRM (Junction with resistor-to-metal current flow). The paired junctions may have opposite polarities to each other. Consequently, the junction voltages associated with paired junctions TCA and TCC are likely to cancel out junctions voltages associated with paired junctions TCB and TCD in the resistor 200.
Furthermore, the resistor 200 may be used as a resistor connecting to a pad. For example, the conductors 230, 240, 250 may be coupled to a conductive bonding pad.
The total thermoelectric potential (or offset voltage), Vtot, developed between tracks 330 and 340 is:
V
tot
=V
a
−V
b
+V
c
−V
d Eq.(1.)
Therefore, the thermoelectric potential (or offset voltage) of the resistor circuit 300 can be cancelled as long as:
V
a
+V
c
=V
b
+V
d Eq. (2.)
In the present embodiment, illustrated in
TEMPTCa+TEMPTCc=TEMPTCb+TEMPTCd Eq. (3.)
Where TEMPTCa is the temperature at TCA, TEMPTCb is the temperature at TCB, TEMPTCc is the temperature at TCc, and TEMPTCd is the temperature at TCD.
Because the thermoelectric potential is a linear function of temperature, the overall thermoelectric potential (or offset voltage), Vtot, should be:
V
a
−V
b
+V
c
−V
d
=K* (TEMPTCa+TEMPTCc−TEMPTCb−TEMPTCd) Eq. (4.)
Where K is a constant related to the conductive materials that form the junction. Again, the overall thermoelectric potential (or offset voltage) becomes zero when TEMPTCa+TEMPTCc=TEMPTCb+TEMPTCd.
Intermediate conductors 470, 480, 490 may connect the resistor segments 410, 420, 430, 440. Intermediate conductors 470, 480, 490 and resistor segments 410, 420, 430, 440 may form a conductive pathway from track 450 to track 460. Conductor 470 may connect resistor segments 410 and 420, conductor 480 may connect resistor segments 420 and 430, and conductor 490 may connect resistor segments 430 and 440. Each junction between conductors 470, 480, 490 and resistor segments 410, 420, 430, 440 forms a junction. The junction between conductor 470 and resistor segment 410 is shown as TCB, the junction between conductor 480 and resistor segment 420 is shown as TCC, etc.
Resistor segments 410, 420, 430, 440 may be placed in the spatial region of an integrated circuit. As illustrated in
The total thermoelectric potential (or offset voltage), Vtot, developed between tracks 550 and 560 is:
V
tot
=V
a
−V
b
+V
c
−V
d
+V
e
−V
f
+V
g
−V
h Eq. (5.)
As described in the discussion of
In another embodiment, the resistor may be utilized in integrated circuit systems made up of active and passive devices that generate heat. In such an embodiment it may be beneficial to distribute paired junctions symmetrically about a thermal centroid of the system to achieve offset voltage cancellation. In this case, the centroid of the system may be different than the centroid of the resistor.
In another embodiment, shown in
The resistor segments in the foregoing embodiments are illustrated as generally linear segments, however, the principles of the present invention are not so limited. The principles of the present invention may accommodate any other geometric shapes—such as circular arcs or elbows—as long as there are an even number of metal-silicon junctions arranged symmetrically about a common centroid and connected in series. Arranging the metal-silicon junctions in such a manner minimizes the voltages generated by the metal-silicon junctions due to the Seebeck effect.
Although the foregoing discussion suggests perfect cancellation of voltages will occur, these represent idealized cases. Perfect cancellation is unlikely to occur when the resistors are manufactured in integrated circuits. When resistors are fabricated, they are unlikely to behave exactly as described in the circuit models illustrated in
Several embodiments of the invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.
This application claims the benefit of priority afforded by provisional application Ser. No. 61/498,244, filed Jun. 17, 2011.
| Number | Date | Country | |
|---|---|---|---|
| 61498244 | Jun 2011 | US |
