On-demand transfer engine

Abstract

An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to a memory transfer device. More particularly, it relates to a memory transfer device allowing a large number of transfer blocks to be passed over a Peripheral Component Interconnect (PCI) bus in a personal computer.

2. Background of Related Art

In traditional Industry Standard Architecture (ISA) based personal computing systems, a Direct memory Access (DMA) controller is responsible for transferring data between host system memory and peripheral input/output (I/O) devices, e.g., a floppy disk, a hard drive, an audio device, etc.

FIG. 9 shows a conventional personal computer (PC) based system including a host processor 906 , and a plurality of peripheral devices 902 - 904 . A DMA controller 910 in communication with a PCI bus 140 through the PCI to ISA bridge 907 facilitates the transfer of blocks of data to and from peripheral to peripheral or host to peripheral.

A conventional DMA controller is typically capable of handling a maximum of only four block transfer channels in a single DMA controller mode. One such conventional DMA controller is a Model 8237 available from Intel and found in many personal computers. In enlarged systems, a secondary DMA controller 912 may be included in a master-slave configuration to the master DMA controller 910 to provide a total of up to 7 data stream transfer channels.

FIG. 10 shows the centrally located input/output (I/O) mapped registers defined for each channel in a DMA controller 910 , 912 . These registers are typically programmed only by the host 906 .

Typical registers in a DMA controller 910 , 912 are a 16-bit host buffer address (e.g., source start address) register 940 , a destination start address register 942 , a 16-bit transfer count (e.g., byte count) register 944 , and perhaps even an 8-page buffer (not shown). The conventional DMA controller 910 , 912 is programmed with a value of the source start address 940 , the destination start address 942 , and the length of the data block to be transferred (byte count) 944 for each of the 7 data transfer channels.

To initiate a data transfer, a host device must program each of the source start address 940 , the destination start address 942 , and the byte count 944 , and, whenever the peripheral desires to transfer data, send a request to the DMA controller 910 , 912 to initiate the data transfer. To transfer buffered blocks of data relating to a continual data stream, particularly buffered blocks of data having a variable length, the byte count register 944 relating to the appropriate DMA channel must be programmed before the transfer of each block of data. Unfortunately, the time required for communication over the PCI bus 140 to affect the appropriate change in the length of the data block (i.e., to update the byte count register 944 ) limits the total amount of data which may be transferred in any given amount of time.

Although the centralized concept of a DMA controller provides the ability to transfer as many as 7 data blocks, the transfer requires communication with the centrally located DMA controller 910 , 912 . Because the conventional DMA controller is centrally located, access may be limiting to certain applications transferring large amounts of data. Moreover, as discussed, applications transferring blocks of data which have a variable length (e.g., some audio applications) require arbitration for the PCI bus 140 and communication with the DMA controller by the requesting device to reset the block length before each data transfer, potentially wasting time, increasing traffic on the PCI bus 140 , decreasing efficiency in the data transfer, and expending valuable MIP (million instruction per second) capacity in the requesting device. Thus, management of the data buffer to be transferred is quite limited and does not offer much flexibility to the user in a DMA controller-based system.

Many conventional agents such as an IDE hard disk controller or a SCSI controller have been implemented to use one or two channels of a DMA controller. However, today's computing advances are becoming limited by the relatively small number of block transfer channels made available by conventional DMA controllers. For instance, hardware accelerated multimedia applications would benefit greatly from the ability to transfer more than 7 channels (i.e., data streams) between host memory and peripherals available using today's technology.

There is thus a need for a more versatile and distributed apparatus and method for allowing the transfer of more than 7 data streams in a personal computer (PC) related application.

SUMMARY OF THE INVENTION

In accordance with the principles of the present invention, a block memory transfer module comprises a start address for a block of memory to be transferred. The start address is maintained in memory of a first device, while a length of the block of memory to be transferred is maintained in memory of a second device separate from the first device.

A method of transferring a large plurality of blocks of data over separate data transfer channels in accordance with another aspect of the present invention comprises distributing a plurality of data transfer engines among a respective plurality of devices connected to a data bus, each data transfer engine including a length of a respective at least one of the plurality of blocks of data. A centralized data buffer is maintained relating to one of a source and destination of each of the plurality of blocks of data to be transferred. Each of the plurality of blocks of data is transferred over a separate one of the plurality of data transfer channels based on the length of the plurality of blocks of data established by each of the distributed plurality of data transfer engines.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings, in which:

FIG. 1 shows a computer system including one or more peripherals having an on-demand transfer (ODT) engine in accordance with the principles of the present invention.

FIG. 2 shows the contents of a memory block within the PC system, e.g., in or relating to the host processor, in accordance with the principles of the present invention.

FIGS. 3 A and 3 A( 1 ) show a circular, dynamic stream interrupt queue in the memory block shown in FIG. 2 .

FIG. 3B shows a stream pointer buffer in the memory block shown in FIG. 2 .

FIG. 3C shows one of up to 128 data stream cyclic buffers in the memory block shown in FIG. 2 .

FIG. 4 shows in more detail an on-demand transfer (ODT) engine shown in FIG. 1 .

FIG. 5A shows a stream request queue in the ODT engine shown in FIG. 4 .

FIG. 5B shows a stream parameter table in the ODT engine shown in FIG. 4 .

FIG. 5C shows a stream data storage block in the ODT engine shown in FIG. 4 .

FIG. 6 shows the status and control registers of FIG. 4 in more detail.

FIGS. 7A , 7 A( 1 A) and 7 A( 1 B) show the ODT system and control register of FIG. 6 in more detail.

FIGS. 7 B and 7 B( 1 A), 7 B( 1 B), 7 B( 2 ), 7 B( 3 A), 7 B( 3 B) to 7 B( 5 ) show the ODT transfer status and control register of FIG. 6 in more detail.

FIGS. 7 C and 7 C( 1 ) show the host peripheral queue depth register of FIG. 6 in more detail.

FIGS. 7D , 7 D( 1 ) and 7 D( 2 ) show the peripheral stream pointers register of FIG. 6 in more detail.

FIGS. 7 E and 7 E( 1 A), 7 E( 1 B), 7 E( 1 B), 7 E( 2 A), 7 E( 2 B) to 7 E( 5 ) show the ODT stream parameter table of FIG. 6 in more detail.

FIGS. 7F , 7 F( 1 ) and 7 F( 2 ) show the ODT's host interrupt pointer registers of FIG. 6 in more detail.

FIGS. 8A and 8B show an operative flow of register information in the disclosed ODT engine constructed in accordance with the principles of the present invention.

FIG. 9 shows a conventional personal computer (PC) based system including a host processor and a plurality of peripheral devices.

FIG. 10 shows the basic registers in a DMA controller relating to each data transfer channel.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A motivation for development of the ODT engine as disclosed herein is the proliferation of new modem and multimedia applications surrounding “Direct-X” function calls in Microsoft Windows™ operating system. The ODT engine provides a maximum amount of flexibility for a host and any agent to manage transfers across the PCI bus with the smallest impact to processing “million instructions per second” (MIPS) as well as memory relating to both the host and the agents.

Most personal computers (PCs) are conventionally equipped with a Peripheral Component Interconnect (PCI) bus. The PCI bus is a versatile bus over which any agent connected to the PCI bus can acquire ownership of the bus.

The PCI bus is currently a best candidate bus to provide access to system resources in a burst mode with low processor overhead. The PCI bus standard was developed in response to a marketplace which was becoming crowded with various permutations of local bus architectures implemented in short-sighted fashions.

The first release of the PCI bus specification, version 1.0, became available on Jun. 22, 1992; Revision 2.0 became available in April of 1993, and Revision 2.1 of the specification became available in the first quarter of 1995. All three of these revisions are specifically and explicitly incorporated herein by reference.

The PCI bus can be populated with adapters requiring fast access to each other and/or system memory, and that can be accessed by a host processor at speeds approaching that of the processor's full native bus speed. It is important to note that all read and write transfers over the PCI bus are burst transfers.

The length of the burst is negotiated between the initiator and target devices and may be of any length.

In the disclosed embodiment, the ODT engine is situated between PCI Bus Interface Logic and multi-ported random access memory (RAM) shared by two DSPs.

The PCI bus, unlike the conventional ISA bus, has the capability for peer-to-peer transfers. In a peer-to-peer transfer, any agent on the bus can transfer data directly to another agent on the bus. The capabilities of PCI bus has enabled the development of a distributed data transfer architecture including what is referred to herein as an on-demand transfer engine in each relevant peripheral which will transfer blocks of data.

In this distributed architecture, any agent that requires transfer of data to or from the host memory or to or from a peer agent preferably defines required block data capabilities consistent with the needs of the agent. For example: a hard disk controller may require only one or two block transfer channels for data transfer, whereas an audio accelerator for multimedia applications may require as many as 8 or many more block transfer channels. Other multimedia applications which can benefit from a high bandwidth data transfer capability include MPEG decoders and video accelerators. Conventional DMA architecture is not only limited as to the number of available data transfer channels, but also becomes quite cumbersome as a centrally located device as the number of data transfer channels increases, e.g., up to 128 as are provided by the disclosed embodiment.

The present invention defines a scaleable architecture, i.e., an ODT engine which is targeted for use in any data transfer application. An ODT engine in accordance with the principles of the present invention provides many features that are not available using conventional DMA controllers, including the ability to support large numbers of block transfer channels.

The disclosed embodiment of an ODT engine is a scaleable data transfer module that can support the transfer across a PCI bus of anywhere from 1 to 128 (or more) independent data streams or block data transfer channels for high bandwidth applications. The data can be transferred from host to agent or agent to agent. Each of these 128 streams of data can be of any arbitrary data type, e.g., stereo audio samples, voice samples, modem data, modem bulk delay data, filter coefficients, command control data, and/or DSP program code.

The disclosed ODT engine includes a set of registers that are preferably located in a shared memory location which is accessible by the host and/or any relevant peripheral agent (e.g., a Digital Signal Processor (DSP)). Preferably, as in the disclosed embodiment, the shared memory location is I/O mapped into host I/O memory space.

All pertinent channel information, i.e., start address, word count, and block count for each channel, is programmable. However, as will be described in more detail, the block count for each data transfer block is maintained in a separate memory location, e.g., in the ODT of the relevant peripheral to enable the peripheral to change the length of the data block “on-the-fly”. This greatly reduces MIP overhead, particularly with respect to ongoing data streams having variable block sizes as are present in audio applications.

The disclosed ODT engine also includes a flexible interrupting scheme to both the host and to the relevant peripheral agent. Moreover, a plurality of transfer modes are available, e.g., for transfer of data or code overlays.

FIG. 1 shows a computer system including one or more peripherals having an on-demand transfer (ODT) engine in accordance with the principles of the present invention.

In particular, a typical computer system will include a host processor 106 and one or more peripheral devices 102 - 104 . In accordance with the disclosed embodiment, each peripheral device 102 - 104 which will request the transfer of data will include an ODT engine 100 , e.g., ODTs 100 a and 100 b in the peripheral devices 104 and 102 , respectively.

The host 106 and the peripheral devices 102 , 104 communicate with one another over an industry standard PCI bus 140 . Although the present invention has been described with respect to an embodiment utilizing the PCI standard bus, the principles of the present invention are equally applicable to other bus standards, but particularly to a bus standard implementing burst communications.

A memory block 110 is located somewhere in the PC system, e.g., in the host 106 . However, in accordance with the principles of the present invention, the memory block 110 may be located anywhere accessible by the PCI bus 140 , including in either of the peripheral devices 102 , 104 .

FIG. 2 shows the contents of an exemplary memory block 110 within the PC system, e.g., in the host 106 , in accordance with the principles of the present invention.

The memory block includes a dynamic stream interrupt queue 202 , a buffer of from 1 to 128 stream pointers 204 , and from 1 to 128 data stream cyclic buffers 206 .

FIGS. 3 A and 3 A( 1 ) show an exemplary circular, dynamic stream interrupt queue in the memory block shown in FIG. 2 .

In particular, column 330 in FIG. 3A indicates whether or not the entry in the dynamic stream interrupt queue 202 is a valid entry (‘1’) or an invalid entry (‘0’). Column 332 indicates the bank number which is to be transferred, e.g., see FIG. 3 C. Column 334 indicates a direction of the data transfer, e.g., a ‘0’ indicates a transfer from a peripheral to the host, and a ‘1’ indicates a transfer from host to the peripheral. Column 336 includes the status bits indicating the type of interrupt which is being activated. These bits relate to the host's perspective, and are preferably the same as the six bits from the peripheral's perspective shown in the ODT Stat register 716 of FIG. 7 B. Column 338 represents the stream number, i.e., channel number.

FIG. 3 A( 1 ) is a table showing one exemplary implementation of a host stream interrupt queue pointer register.

FIG. 3B shows an exemplary stream pointer buffer in the memory block shown in FIG. 2 . Each entry 340 - 346 is a 32 bit stream pointer indicating the current address of the ODT engine. Two 32-bit stream pointers 340 , 342 or 344 , 346 correspond to each data stream. Each 32-bit stream pointer indicates the starting address in the host cyclic buffer 206 , e.g., as shown in FIG. 3 C.

FIG. 3C shows one of up to 128 data stream cyclic buffers in the memory block shown in FIG. 2 , and is otherwise known as a host cyclic buffer. Note, for instance, that the 32-bit stream pointer 340 in the example of FIG. 3B indicates the address of the top of bank 350 shown in FIG. 3 C.

The entries 361 - 363 shown in FIG. 3C represent the blocks of data being transferred. In operation, after, for example, data block 361 is transferred, the memory address of the starting address of the data block 362 is input into the 32-bit stream pointer 342 (FIG. 3 B).

Data blocks 371 - 373 are similar blocks of data to be transferred, but from/to the alternate bank 352 . The use of two banks 350 , 352 allow operation in a ping-pong fashion. Preferably, to avoid conflicts, host and peripherals do not operate on both banks 350 , 352 simultaneously.

In operation, the ODT engine generates a stream interrupt to the host whenever the ODT engine reaches the end of a bank 350 , 352 . At substantially the same time, an entry is written into the host stream interrupt queue 202 to initiate a service interrupt.

FIG. 4 shows in more detail an on-demand transfer (ODT) engine shown in FIG. 1 .

In particular, as shown in FIG. 4 , the disclosed embodiment of an ODT engine 100 includes various status and control registers 408 , a stream request queue 402 , a stream parameter table 404 , and stream data storage 406 .

FIG. 5A shows a stream request queue 402 in the ODT engine shown in FIG. 4 .

Each row in FIG. 5A represents individual entries 520 - 522 , and the columns 502 - 510 represent the contents of each entry 520 - 522 . For instance, column 502 is a mask bit to allow masking of the relevant interrupts. Column 504 is a flag indicating whether or not the stream request is active (‘1’) or inactive (‘0’). Column 506 indicates the direction of the data transfer being requested. Column 508 indicates the size of the block of data being transferred, e.g., the number of words to be transferred. For instance, in the disclosed embodiment, the actual number of words transferred is one more than that indicated in the size column 508 . Column 510 is the stream number.

The entry 504 is a flag bit in the stream request queue 402 which represents the validity of an entry. For instance, a flag bit 504 of ‘1’ indicates a valid interrupt request, whereas a flag bit 504 of ‘0’ is generated after the peripheral has serviced the relevant interrupt and clears the flag bit 504 .

FIG. 5B shows a stream parameter table in the ODT engine 100 shown in FIG. 4 . The stream parameter table 404 shown in FIG. 5B shows three separate entries relating to three respective data streams. Each entry includes a set of information relevant to where the data is located both on the peripheral side and the host side.

FIG. 5C depicts a stream data storage block 406 in the ODT engine 100 shown in FIG. 4 . The stream data storage block 406 includes a plurality of data streams to be transferred.

FIG. 6 depicts various status and control registers implemented in the ODT engine 100 in the embodiment shown in FIG. 4 . The disclosed embodiment includes an ODT system and control register 602 , an ODT transfer status and control register 604 , a host and peripheral queue depth register 606 , peripheral stream pointers register 608 including a peripheral stream request pointer and a peripheral stream parameter table pointer, an ODT stream parameter table 610 , and the host interrupt pointer register 612 . The ODT system and control register 602 is shown in more detail in FIGS. 7A , 7 A( 1 ) and 7 A( 2 ), the ODT transfer status and control register 604 is shown in more detail in FIGS. 7 B and 7 B( 1 ) to 7 B( 5 ), the host and peripheral queue depth register 606 is shown in more detail in FIGS. 7 C and 7 C( 1 ), the peripheral stream pointers register 608 is shown in more detail in FIGS. 7D , 7 D( 1 ) and 7 D( 2 ), the ODT stream parameter table 610 is shown in more detail in FIGS. 7 E and 7 E( 1 ) to 7 E( 5 ), and the ODT's host interrupt pointer register 612 is shown in more detail in FIGS. 7F , 7 F( 1 ) and 7 F( 2 ).

A time-out event may be established with a programmable ODT timer that is under host or peripheral control. Such a timer would provide an automatic method of setting the “Go” bit in the ODT Transfer status and control register 604 , e.g., every 1 usec to every 100 msec. The “Go” Bit may be automatically cleared when the ODT has sequenced through one complete pass of the Stream Request Queue.

The ODT preferably enters an idle state (e.g., goes to ‘sleep’) when the “Go” bit is deactivated. This provides the host and peripherals with a mechanism to determine whether any ODT engine is actively transferring data or is idle. Additionally, this scheme allows the relevant ODT transfer rate to adjust dynamically to match stream bandwidth requirements at any given time, and also saves power by reducing the number of memory accesses.

FIG. 8 shows an operative flow of register information in the disclosed ODT engine constructed in accordance with the principles of the present invention.

A specific implementation of the various registers in the ODT engine 100 are described in the following tables. It is to be understood that the specific bits, sizes, addresses and other features of the registers and memory in or relating to the ODT engine 100 may be quite different from those disclosed herein but remain covered by the principles of the present invention.

In operation, an agent or particular application will request a data stream transfer from the ODT engine 100 by programming an entry 520 - 524 in the Stream Request Queue (SRQ) 402 . The disclosed SRQ entry 520 - 524 comprises a block transfer size 508 , a stream ID number 510 , a direction of transfer 506 , a transfer request flag 504 , and a host interrupt mask bit 502 .

The SRQ 402 preferably has a programmable depth and is completely relocateable within the memory space of the relevant peripheral via an SRQ base address register (not shown).

Each data stream identified by a stream ID number 510 in the SRQ 402 has an associated Stream Parameter Table (SPT) 404 . The SPT 404 is initialized by the requesting peripheral or host to provide the start address 542 of the data block to be transferred, and the number of data blocks 540 to be transferred. The SPT 404 is preferably located in the same memory map as the SRQ 402 , and is also relocateable within the respective memory maps of the host and/or peripheral.

Thus, any device requesting a data transfer inputs an entry 520 - 524 in the SRQ 402 and initializes a corresponding SPT 404 . Once the peripheral or host has initialized the relevant data streams for block transfers, the ODT engine 100 will be given a ‘GO’ command 712 ( FIG. 7B ) by the requesting peripheral or host to initiate the start of data transfer.

Upon receiving the GO command 712 via the ODT transfer status and control register 604 (FIG. 7 B), the ODT engine 100 will monitor the SRQ 402 for a valid request. If a valid request is present in the SRQ 402 , then the ODT engine 100 will fetch the corresponding SPT 404 for the data stream and complete the data transfer.

Upon completion of the single block transfer, the ODT engine 100 will update the SRQ entry 520 - 524 by resetting its transfer request flag in the ODT stream request queue entry 504 , and will update the corresponding SPT entry 520 - 524 with new pointers. After going through the entire stream request queue, the ODT engine will reset its transfer request flag in the ODT transfer status and control register 604 . The ODT engine 100 will also update the host address pointer 204 in the host memory 110 after each block transfer. This is a useful feature and enables the host driver to query the current position of the buffer pointer 204 relating to the requesting ODT engine 100 simply by reading a memory location in the host memory 110 .

If the ODT engine 100 has reached, e.g., a half buffer mark H as shown in FIG. 3C , it will cause an entry to be made in the host's dynamic stream interrupt queue 202 and will initiate an interrupt to the host (if the interrupt is enabled). The entry 310 - 324 comprises the status of the interrupt 336 and the data stream ID 338 .

The ODT engine 100 will continue to monitor the SRQ 402 until all the SRQ entries 520 - 524 are exhausted.

The requesting peripheral can request the transfer of a subsequent block of data by making another entry in the SRQ 402 and issuing a GO command 712 to the ODT engine 100 .

In accordance with the disclosed embodiment, buffer pointers 204 (including the wrap-around of buffer pointers at the end of a bank) are handled by the ODT engine 100 without further involvement from the host.

Different modes can be established in the ODT engine 100 based on the needs of the particular application. For instance, the ODT engine 100 can include a code download mode allowing the transfer of up to 16 K words in a single block transfer, i.e., with one SRQ entry 520 - 524 and a single GO command 712 .

The register definitions and operation of the ODT engine 100 are described herein with respect to a modem and audio application. The ODT engine 100 has a wide-range of applications, including but not limited to sample rate conversion, off-loading bulk delays, dynamic coefficient downloading, in-place block processing schemes, and other large block transfers of data or program code.

In general, the disclosed ODT engine 100 supports data transfers of from 1 to 128 independent data streams. Each data stream is associated with its own data storage buffer of, e.g., from 1 to 64 words. Each data stream storage block is on a word aligned boundary.

Moreover, each data stream has its own host cyclic buffer 206 in the host memory 110 . Each host cyclic buffer 350 , 352 ( FIG. 3C ) is programmable to be from 4 to 64K Bytes deep. Each host cyclic buffer 350 , 352 can overlap, e.g., Direct-Sound memory allotments.

Host applications can query each data stream and determine the current position being transferred within each stream's host cyclic buffer 350 , 352 without accessing the registers of the ODT engine 100 and without involvement of the peripheral supporting the memory. The current position can be determined to an accuracy of the number of words in a block.

Bus master accesses to the host system memory 110 will be 32-bit wide accesses with 26 bits of accuracy. The beginning address of the host cyclic buffer 350 , 352 of each data stream is on a 4 byte aligned boundary. In the disclosed embodiment, the ODT engine 100 resides within a 64 MByte system memory space.

The ODT engine 100 supports both WORD and DWORD data size transfers across the PCI bus 140 to optimize throughput across the PCI bus 140 .

The dynamic host stream interrupt queue (SIQ) 202 allows a host interrupt service routine (ISR) to independently service the ODT engine's interrupt for each data stream. Entries in the dynamic host stream interrupt queue 202 are updated by the relevant ODT engine 100 .

The ODT engine 100 identifies which data stream is requesting a block transfer, and passes ODT status information through each entry 520 - 524 in the stream request queue 402 .

The ODT engine 100 requires low host MIP overhead in servicing the individual interrupts from the various ODT engines 100 a , 100 b even when supporting large numbers of data stream transfers.

The ODT engine 100 provides programmable depth control for the dynamic stream interrupt queue 202 up to a maximum of, e.g., 256 word entries. The dynamic stream interrupt queue 202 allows the ODT engine 100 to recognize that the peripheral or host has requested one or more data blocks to be transferred.

Entries in the stream request queue 402 preferably provide sufficient information for the ODT engine 100 to i) identify the data stream block which has been requested for transfer; ii) identify the word size of the data stream block; and iii) identify the direction of transfer for the request. The entries 520 - 524 in the stream request queue 402 include a request flag bit 504 set by the requesting peripheral and monitored by the relevant ODT engine 100 to determine whether the previously requested data block has already been transferred.

The interrupts to the host 106 are preferably independently maskable to allow the requesting peripheral to make multiple entries in the dynamic stream interrupt queue 202 without requiring an actual interrupt to the host 106 to occur.

The stream request queue 402 has programmable depth control to minimize the amount of RAM required for usage by the ODT engine 100 .

The ODT engine 100 supports a transparent transfer mode which allows the peripheral (e.g., including a DSP) to use host system memory as an extension of the peripheral's RAM block size without any involvement by the host 106 .

Preferably, the ODT engine 100 does not generate an entry to the dynamic stream interrupt queue 202 , and does not generate an interrupt to the host 106 . The ODT engine 100 generates an interrupt to the peripheral when the peripheral has reached the end of each host bank, which is half the host cyclic stream buffer as shown in FIG. 3 C. This implies two interrupts to the peripheral, one for read (RX) transfers and the other for write (TX) transfers.

The ODT engine 100 does not wait for the peripheral to respond to the interrupt. Instead, the interrupt to the peripheral by the ODT engine 100 would be cleared by the peripheral via a read of an ODT engine interrupt status register. In the disclosed embodiment, the ODT engine's interrupt is double buffered to prevent the peripheral from missing an interrupt event.

The ODT engine 100 allows the peripheral to control where in the data stream cyclic buffer 206 the transfer request is to occur. This implies that the peripheral can control, e.g., 26 bits of the current 32 bit stream pointer 204 used during a block transfer.

The ODT engine 100 supports the transfer of larger than 64 continuous words per stream by allowing a transfer request for the transfer of multiple blocks (1 to 64 words each) without managing any peripheral or host address pointers.

The ODT engine 100 includes an auto-increment flag bit which the peripheral would set once. This bit is used by the ODT engine 100 to indicate that the next peripheral address which will be used by the ODT engine 100 for the beginning of the next block transfer will be stored back into the peripheral's RAM as part of the Stream Parameter Table (SPT) 404 . The default value of this auto-increment flag bit assumes that the peripheral is not using auto-increment mode, and that the peripheral is responsible for updating the peripheral's address if necessary.

Since this feature may be used to download agent code, e.g., DSP code, “on-the-fly”, the peripheral requires an interrupt from the ODT engine 100 indicating that a set of multiple consecutive entries for a given data stream has been transferred.

All data stream transfer information is preferably grouped per stream by the ODT engine 100 in a common area in memory, i.e., in the SPT 404 .

Each stream's block data storage area in memory is allowed to be allocated in independent, non-contiguous areas, i.e., stream data storage. Each stream's host cyclic buffer storage area is allocated in separate independent noncontiguous areas as well.

In accordance with the principles of the present invention, the ODT registers for the ODT engine 100 of each peripheral device are distributed among the respective peripheral devices. Moreover, the ODT registers are accessible by the host or another peripheral.

Preferably, in the ODT engine 100 , maskable peripheral interrupts are established for the following:

(a) When the ODT engine 100 has detected a collision with the host 106 due to the host not clearing the HI bit 532 in the stream parameter table 404 .

(b) When the ODT engine 100 has completed a stream transfer and the ODT engine 100 passes a stream ID number 718 via the ODT transfer status and control register 604 . This interrupt is preferably self-cleared when the peripheral reads the ODT transfer status and control register 604 .

(c) When the ODT engine 100 has detected a collision with the dynamic stream interrupt queue 202 via the MSB bit 330 ( FIG. 3A ) not being cleared. The host 106 must service each stream's cyclic buffer 350 , 352 indicated by each entry in the dynamic stream interrupt queue 202 , then clear the MSB bit 330 in the relevant entry to inform the ODT engine 100 that the host 106 has completed the relevant cyclic buffer service request.

(d) When the ODT engine 100 has detected a wait to access to the peripheral RAM 804 , in which case the ODT engine 100 will generate an interrupt. This interrupt is preferably cleared by a read of the ODT transfer status and control register 604 by the peripheral.

(e) When the ODT engine 100 has detected a PCI bus event that has caused a PCI bus latency counter to time-out, or a premature termination of a PCI bus master access, either of which causes a maskable interrupt. Preferably, this interrupt is cleared by a read of the ODT transfer status and control register 604 by the peripheral.

(g) When an emergency ODT engine stop condition has occurred due to a mis-match of ODT's upper 6 Bits of the host interrupt queue pointer register 204 with the declared range of the host Interrupt queue pointer register 204 . When this state has been detected, the ODT engine 100 will immediately halt and terminate a current block transfer, then cause a non-maskable (or maskable) interrupt to the peripherals and to the host 106 .

A maskable interrupt may be generated for the host 106 when the ODT engine 100 has completed one or a multiple number of stream's block transfer, and ODT engine 100 will generate a maskable interrupt to the host 106 . This interrupt from ODT engine 100 is intended to be used by the host 106 to manage specified stream's cyclic buffers 206 . This interrupt is cleared when the host 106 reads the relevant entry in the dynamic stream interrupt queue 202 .

Another maskable interrupt may be generated for the host 106 when the ODT engine 100 has detected a collision with the dynamic stream interrupt queue 202 via its MSB bit 330 not being cleared. The host 106 must service each stream's cyclic buffer 206 indicated by each entry in the dynamic stream interrupt queue 202 , then clear the MSB 774 (or other designated bit) in the relevant entry to inform the ODT engine 100 that the host 106 has completed the relevant cyclic buffer service request. This interrupt is preferably cleared when the host 106 reads the dynamic stream interrupt queue 202 .

Thus, in accordance with the principles of the present invention, an efficient, high capacity, flexible, and distributed block data transfer system is provided.

While the invention has been described with reference to the exemplary embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention.

Claims

1. A block memory transfer module comprising:a start address for a block of memory to be transferred, maintained in memory of a first device; and a length of said block of memory to be transferred, maintained in memory of a second device separate from said first device; wherein said length of said block of memory to be transferred is variable without requiring intervention by said first device.

2. The block memory transfer module according to claim 1, wherein:said first device is a host.

3. The block memory transfer module according to claim 2, wherein:said second device is a peripheral device including said block of memory.

4. The block memory transfer module according to claim 1, wherein:said second device is a peripheral device including said block of memory.

5. The block memory transfer module according to claim 1, further comprising:a burst type data transfer bus between said first device and said second device.

6. The block memory transfer module according to claim 5, wherein:said burst type data transfer bus is a Peripheral Components Interface bus.

7. The block memory transfer module according to claim 6, wherein:said first device is a host processor of a personal computer; and said second device is a peripheral in said personal computer.

8. A method of transferring a large plurality of blocks of data over separate data transfer channels, said method comprising:distributing a plurality of data transfer engines among respective devices connected to a data bus, each data transfer engine including a length of a respective at least one of said plurality of blocks of data; maintaining a centralized data buffer in a host relating to one of a source and destination of each of said plurality of blocks of data to be transferred; transferring each of said plurality of blocks of data over a separate one of said plurality of data transfer channels based on said length of said plurality of blocks of data established by each of said distributed plurality of data transfer engines; and changing said length of said respective at least one of said plurality of blocks of data without requiring intervention by said host.

9. The method of transferring a large plurality of blocks of data over separate data transfer channels according to claim 8, said method further comprising:maintaining a centralized start address relating to a starting address of a source of each of said plurality of blocks of data to be transferred separate from a storage device for storing said lengths of said plurality of blocks of data.

10. The method of transferring a large plurality of blocks of data over separate data transfer channels according to claim 8, wherein:said data buffer is cyclic.

11. The method of transferring a large plurality of blocks of data over separate data transfer channels according to claim 8, wherein:said data bus is a burst type data transfer bus.

12. The method of transferring a large plurality of blocks of data over separate data transfer channels according to claim 11, wherein:said burst type data transfer bus is a PCI bus.

13. The method of transferring a large plurality of blocks of data over separate data transfer channels according to claim 8, wherein :said large plurality is more than seven.

14. Apparatus for transferring a large plurality of blocks of data over separate data transfer channels, said method comprising:a plurality of data transfer means for transferring at least one block of data, said plurality of data transfer means being distributed among a respective plurality of devices connected to a data bus, each data transfer means including a length of a respective at least one of said plurality of blocks of data; centralized data buffer means maintained in a host for containing one of a source and destination of each of said plurality of blocks of data to be transferred; means for transferring each of said plurality of blocks of data over a separate one of said plurality of data transfer channels based on said length of said plurality of blocks of data established by each of said distributed plurality of data transfer engines; means for changing said length of said respective at least one of said plurality of blocks of data without requiring intervention by said host.

15. The apparatus for transferring a large plurality of blocks of data over separate data transfer channels according to claim 14, further comprising:means for maintaining a centralized start address relating to a starting address of a source of each of said plurality of blocks of data to be transferred separate from a storage device for storing said lengths of said plurality of blocks of data.

16. The apparatus for transferring a large plurality of blocks of data over separate data transfer channels according to claim 14, wherein:said centralized data buffer means is cyclic.

17. The apparatus for transferring a large plurality of blocks of data over separate data transfer channels according to claim 14, wherein:said data bus is a burst type data transfer bus.

18. The apparatus for transferring a large plurality of blocks of data over separate data transfer channels according to claim 17, wherein:said burst type data transfer bus is a PCI bus.

19. The apparatus for transferring a large plurality of blocks of data over separate data transfer channels according to claim 14, wherein:said large plurality is more than seven.

20. A system adapted for transferring a large plurality of blocks of data over separate data transfer channels, said system comprising:a plurality of computer devices each comprising a respective data transfer engine, each of said plurality of computer devices interconnected via a data bus, each data transfer engine including storage for a length of a respective at least one of said plurality of blocks of data; and a host computer device including a centralized data buffer relating to one of a source and destination of each of said plurality of blocks of data to be transferred, said host computer device including a starting address of each of said plurality of blocks of data; wherein said length of said respective at least one of said plurality of blocks of data is variable without requiring intervention by said host computer device.

21. The system adapted for transferring a large plurality of blocks of data over separate data transfer channels according to claim 20, wherein:said data bus is a PCI bus.

22. The system adapted for transferring a large plurality of blocks of data over separate data transfer channels according to claim 20, wherein:said data bus is a burst type data bus.